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• SERIElectronique - training systems and evaluation boards for 68HC11, 68HC12, 8051, VHDL , CAN bus ,Robot kits, I2C , CAN , USB , RS 485 and IRDA    Rate this link - Click here to go to page where this link is listed (/links/companies.html)
• Using VHDL-AMS to model complex heterogeneous systems, part 2 - You can implement DSP-controller algorithms using the mixed-signal features of the VHDL-AMS modeling language.    Rate this link - Click here to go to page where this link is listed (/links/dsp.html)
• GHDL - GHDL is a VHDL simulator, using the GCC technology. GHDL implements the VHDL language according to the IEEE 1076-1987 or the IEEE 1076-1993 standard. GHDL compiles VHDL files and creates a binary which simulates (or executes) your design. GHDL does not do synthesis: it cannot translate your design into a netlist.    Rate this link - Click here to go to page where this link is listed (/links/fpga.html)
• Opencores.org - This is a good site containing free (GPL) tested Verilog/VHDL models.    Rate this link - Click here to go to page where this link is listed (/links/fpga.html)
• PLD code creates PWM generators - This PLD (programmable-logic-device) code creates arbitrary-resolution, pulse-width-modulated (PWM) generators. PWM generators are useful as low-bandwidth D/A converters in hardware of microprocessor-based systems. When you pass it through a simple RC lowpass filter, a PWM waveform becomes a voltage that's approximately equal to the PWM duty cycle times the supply voltage. This code is written for Altera's devices, but you can quite easily translate the design structure and flow into VHDL or Verilog.    Rate this link - Click here to go to page where this link is listed (/links/fpga.html)
• Counter provides divide-by-4.5 function - some VHDL code, a 9-bit shift register, and some OR gates produce a divide-by-4.5 circuit, you can can adapt the concept for other noninteger dividers    Rate this link - Click here to go to page where this link is listed (/links/fpga.html)
• VHDL code implements 50%-duty-cycle divider - realizing a 50%-duty-cycle, divided-down clock is not always a trivial task, particularly when the divisor rate is an odd number but this example code will help youn in this task    Rate this link - Click here to go to page where this link is listed (/links/fpga.html)
• Getting a handle on HDLs - Programmable-logic chips and designs are growing more complex. As a result, you?ll sooner or later need to add HDL expertise to your skills if you want to keep hitting those project deadlines. For this Hands-On Project, I learn VHDL, complete a mixed logic and embedded-memory design in an FPGA, and share observations along the way.    Rate this link - Click here to go to page where this link is listed (/links/fpga.html)
• 10 tips for generating reusable VHDL - Your ability to reuse blocks expressed in an HDL is critical to designing systems on chips. Here are some tips you can use to generate VHDL-based blocks that you and others can reuse in subsequent chip designs.    Rate this link - Click here to go to page where this link is listed (/links/fpga.html)
• HDL basic training: top-down chip design using Verilog and VHDL    Rate this link - Click here to go to page where this link is listed (/links/fpga.html)
• Using VHDL-AMS to model complex heterogeneous systems, part 1 - HDLs bridge the gap between math-based tools and physics-based tools to help you meet model-development requirements.    Rate this link - Click here to go to page where this link is listed (/links/fpga.html)
• Using VHDL-AMS to model complex heterogeneous systems, part 2 - You can implement DSP-controller algorithms using the mixed-signal features of the VHDL-AMS modeling language.    Rate this link - Click here to go to page where this link is listed (/links/fpga.html)
• VHDL and Verilog fundamentals--expressions, operands, and operators - data objects in VHDL and Verilog form expression operands, knowing the operand differences between the two HDLs helps you write more efficient chip-design code    Rate this link - Click here to go to page where this link is listed (/links/fpga.html)
• VHDL and Verilog fundamentals--design entities, data types, and data objects    Rate this link - Click here to go to page where this link is listed (/links/fpga.html)
• VHDL emerges as a commercial design tool - despite the initial challenges imposed by VHDL, the language, born of the military, has made the commercial sector sit up and take notice    Rate this link - Click here to go to page where this link is listed (/links/fpga.html)
• VHDL Synthesis Tutorial    Rate this link - Click here to go to page where this link is listed (/links/fpga.html)
• HDL basic training: top-down chip design using Verilog and VHDL    Rate this link - Click here to go to page where this link is listed (/links/fpga.html)
• VHDL and Verilog fundamentals--expressions, operands, and operators - data objects in VHDL and Verilog form expression operands, knowing the operand differences between the two HDLs helps you write more efficient chip-design code    Rate this link - Click here to go to page where this link is listed (/links/fpga.html)
• VHDL and Verilog fundamentals--design entities, data types, and data objects    Rate this link - Click here to go to page where this link is listed (/links/fpga.html)
• Superlog - superset of Verilog, borrows features from VHDL and C++    Rate this link - Click here to go to page where this link is listed (/links/fpga.html)

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