Electronics trends for 2015

Chip designs that enable everything from a 6 Gbit/s smartphone interface to the world’s smallest SRAM cell will be described at the International Solid State Circuits Conference (ISSCC) in February 2015. Intel will describe a Xeon processor packing 5.56 billion transistors, and AMD will disclose an integrated processor sporting a new x86 core, according to a just-released preview of the event. The annual ISSCC covers the waterfront of chip designs that enable faster speeds, longer battery life, more performance, more memory, and interesting new capabilities. There will be many presentations on first designs made in 16 and 14 nm FinFET processes at IBM, Samsung, and TSMC.

There is push to go to even smaller processes, and it seems that next generation of lithography equipment are started to being used. Earlier expectation was for chipmakers to use traditional immersion lithography for production of 10 nm chip, but it seems that extreme ultraviolet (EUV) scanners that allows allow scaling to 10 nm or even smaller is being used. TSMC to Use EUV for 7nm, Says ASML. Intel and TSMC have been injecting money in ASML to push process technology.

2015 promises to see initial FPGA product releases and (no doubt) a deluge of marketing claims and counter-claims. One thing is certain: 2015 will not be boring. There will be FPGA products that use processes beyond 20nm, for example Altera and  Xilinx have committed to use the TSMC 16nm FinFET technology. There is  publicized (and rumored) race to get to production at 14nm has seen time frames for initial samples move into 2015. However, with both FPGA companies reporting gross margins of close to 70 percent, it would be possible for either company to take an initial hit on margin to gain key socket wins.

It seems that the hardware becomes hot again as Wearables make hardware the new software. Apple invest its time when it released the Apple Watch last quarter, going up against the likes of Google’s Android Wear and others in the burgeoning wearables area of design. Once Apple’s bitten into a market, it’s somewhat a given that there’s good growth ahead and that the market is, indeed, stable enough. As we turn to 2015 and beyond  wearables becomes an explosive hardware design opportunity — one that is closely tied to both consumer and healthcare markets. It could pick up steam in the way software did during the smartphone app explosion.

There will be more start-up activity within hardware sector. For recent years, the software has been on the main focus on the start-ups, and the hardware sector activity has been lower. Hardware sector has seem some start-up activity with many easy to use open hardware platforms became available (make development of complex devices easier and reachable for smaller companies). The group financing (Kickstarter, Indiegogo, etc.) have made it possible to test of new hardware ideas are market-worthy and get finance to get them to production.

EEs embrace hackathons aand accelerators. Design 2.0 is bubbling up in the engineering community, injecting new energy into the profession. In many ways, it’s the new Moore’s Law. Easy to use open hardware development platforms have made it possible to design working hardware device prototypes within hackathons.

Silicon Startups Get Incubator article tells that there will be new IC start-up activity as semiconductor veterans announced plans for an incubator dedicated to helping chip startups design their first prototypes. Keysight, Synopsys, and TSMC have signed exclusive deals to provide tools and services to the incubator. Silicon Catalyst aims to select its first batch of about 10 chip startups before April.

1,206 Comments

1. June 25, 2015 at 10:35 am

   Tomi Engdahl says:

   Analysing AMOLED Power Efficiency Improvements
   by Andrei Frumusanu on June 23, 2015 8:00 AM EST
   http://www.anandtech.com/show/9394/analysing-amoled-power-efficiency

   Over the last few years we’ve been repeatedly reporting how Samsung was able to improve AMOLED power efficiency by employing better emitter materials on each new device generation. This went largely unverified as nobody really tried to accurately measure the actual power consumed by the screen.

   AMOLED screens are emissive displays, meaning they emit light on their own without having to resort to backlights in transmissive technologies such as LCD screens. This causes white to be the most power-intensive color for an OLED screen to display because it requires all sub-pixels to operate at high emission. The advantage of OLED screen though is that for dynamic content, the technology is able to save power in comparison to transmissive displays because only the pixels which are actually used are powered up.

   Because white is a worst-case power scenario, it serves well as good representation of general efficiency gains in OLED devices.

   One has to keep in mind that most of this power is not due to the display itself, but due to the lack of Panel Self Refresh on past generation devices. PSR is able to achieve better power efficient in static screen scenarios by not re-sending frame-buffer information to the screen’s display controller IC.

   The good news though is that this gap keeps decreasing with each generation and the disadvantage is limited to pure white background content. Having even slightly grey or colored content will start shifting the scales back in favour of AMOLED devices. Running dark themes and dark backgrounds can really be advantageous for AMOLED device as they are able to achieve factors of 3-4x in luminance-power advantage over LCD devices.
   I would say that Samsung still needs to achieve another 15-20% improvement in power before AMOLED is consistently more efficient than LCD devices in even the worst-case APL and high white-percentage scenarios.

   Reply
2. June 25, 2015 at 10:57 am

   Tomi Engdahl says:

   Modern Avionics Rely on Robust, Flexible FPGA Designs
   http://rtcmagazine.com/articles/view/110541

   Thanks to advances in programmable logic, today’s FPGAs can now be used to make high-reliability systems such as those in avionics both flexible and configurable as well as dramatically reduce the chance of errors that could compromise safety.

   AFDX in Today’s Avionics

   Asynchronous Full Duplex Switched Ethernet (AFDX, designated ARINC-664) has been designed to account for the growing number of avionic subsystems in modern aircraft and their complex interaction. It resembles a true IP and UDP packet based on switched Ethernet compliant to the IEEE 802.3 industry standard. Based on these well-established standards, the AFDX technology adds protocol extensions to provide reliable packet transport and bounded transport latency to make it suitable for avionic applications.

   At the application level, ADFX emulates logical point-to-point connections with clear separation of data streams and bandwidth allocation. In fact, a logic path that provides the same properties to an application as an ARINC-429 connection exists in AFDX. In addition, several of these connections are now multiplexed and run through one Ethernet wire, making AFDX a network architecture that significantly reduces the amount of cable runs.

   An AFDX network consists of switches and end systems, which are components connected to the network capable of handling all AFDX-related protocol operations. Usually, an end system is part of an avionic or aircraft subsystem, which needs to send or receive data over the AFDX network. Depending on the network hierarchy, one or more switches are located on the data path between two end systems.

   At the application level, AFDX is intended to replace ARINC-429 connections. With ARINC-429 representing point-to-point or point-to-multipoint connections, it is not surprising, that AFDX has similar characteristics, with the ARINC-429 connections represented by AFDX virtual links (VLs).

   FPGA Technology in an AFDX End System

   End systems must continuously receive non-redundant packets on both interfaces with full wire speed without packet loss. Traditionally this was carried out on ASIC technology or on pure software implementations of the protocol stack.

   A hardware implementation in general has advantages, because the logic and its timing are easier to prove, due to the synchronous nature and the true parallelism in execution. And today’s high end FPGAs are fast, large and robust enough to implement the AFDX protocol for handling the requirements of modern avionics systems.

   Any safety-relevant system design needs to consider all possible failure modes of the component, their effects at the interface level, and finally, the probability for them to occur during the period of operation.

   Safety and Reliability

   Since AFDX provides the main interconnect between the major subsystems of today’s aircraft, it is literally the backbone of the avionics. The integrity of the data travelling along this path, its timely delivery, and the availability of the transport service to the clients that need them, at the time they are needed, are key factors in a truly safe and reliable AFDX-based system.

   An AFDX end system needs to be robust with respect to its failure rates, specifically defined in this instance as follows: the probability of the failure mode “loss of function” must be very low, usually in the magnitude of less than 10-6 per flight hour.

   The triple-module redundancy (TMR) architecture in the FPGA is a way to affect this rate.

   As AFDX End-Systems are deployed in avionics subsystems a line-replaceable units (LRUs), a certification according to DO-254 has to be considered in the design of the FPGA, as well as the process that is established to achieve the design and its verification.

   Reply
3. June 25, 2015 at 11:00 am

   Tomi Engdahl says:

   Intel Architecture versus the FPGA: The Battle of Time, Complexity and Cost
   http://rtcmagazine.com/articles/view/108876

   The continued evolution of Intel architecture (IA) enables electronic OEMs to consider it for applications previously requiring an FPGA. The benefits brought by IA are decreased development time, lower project cost, and high performance with feature integration.

   Reply
4. June 26, 2015 at 6:35 am

   Tomi Engdahl says:

   Power analysis has a new look
   http://www.edn.com/electronics-blogs/eda-power-up/4439756/Power-analysis-has-a-new-look?_mc=NL_EDN_EDT_EDN_today_20150625&cid=NL_EDN_EDT_EDN_today_20150625&elq=5da50c1973a44c499de2fd88166fcb90&elqCampaignId=23630&elqaid=26676&elqat=1&elqTrackId=68804d5767874ee3afa73aa2bb7b9daa

   Power continues to be a primary concern for handheld and smart devices, with their high resolution screens that require long battery life, as well as for wall-plugged equipment in datacenters and network configurations, for which the cost of operation is a key market factor. While FinFET process technology reduces static leakage, dynamic power remains a challenge.

   However, a new usage model for handheld and smart devices is driving a methodology shift in the way power is analyzed. Complex system-on-chip (SoC) designs are now verified using live applications that require booting the operating system and running software applications on an emulator. In this verification model, it is more effective to use the power switching activity plot, which is generated during emulation, to pass real-time switching activity information to power analysis tools where potential power issues can be evaluated.

   Reply
5. June 26, 2015 at 6:35 am

   Tomi Engdahl says:

   A Guide to using FETS for Sensor Applications, Part 1
   http://www.edn.com/design/analog/4439728/A-Guide-to-using-FETS-for-Sensor-Applications–Part-1?_mc=NL_EDN_EDT_EDN_weekly_20150625&cid=NL_EDN_EDT_EDN_weekly_20150625&elq=0dd6c755e76142a68941acc7d620b499&elqCampaignId=23611&elqaid=26649&elqat=1&elqTrackId=16dcb2efb8bb437e9c4748603a477b4f

   Reply
6. June 26, 2015 at 6:53 am

   Tomi Engdahl says:

   Silicon photonics: Will the hare finally catch the tortoise?
   http://www.edn.com/electronics-blogs/eye-on-standards/4439755/Silicon-photonics-Will-the-hare-finally-catch-the-tortoise-?_mc=NL_EDN_EDT_EDN_weekly_20150625&cid=NL_EDN_EDT_EDN_weekly_20150625&elq=0dd6c755e76142a68941acc7d620b499&elqCampaignId=23611&elqaid=26649&elqat=1&elqTrackId=660361e001a949b0b8a9b0a018b81558

   My question: at what data rate do you think engineers will have to focus on designs that use photons to push data? Her answer: 50 Gbps per optical carrier for transmission farther than two meters.

   By overcoming the signal degrading characteristics of electrical interconnects—loss, messy frequency response, crosstalk, and impedance matching difficulties—with clever technologies such as pre/de-emphasis, embedded clocking, and equalization, the need for silicon photonics has been pushed into the future, beyond 28 Gbps. Optical interconnects at 10-100 Gbits/s suffer chromatic and polarization-mode dispersion, which are tiny levels of loss and reflections, but only after propagating hundreds of meters. Optical eyes stay wide open and awake over reaches of dozens of meters.

   The people who actually do silicon photonics are comfortable when it comes to including fiber-optic applications in their field. Being a fan in the cheap seats, however, I think it’s fair to distinguish fiber optics from silicon photonics. A purist’s silicon photonics is not infected with fibers, that’s fiber optics. Genuine silicon photonics applications transmit photonic signals across waveguides within a chip, or chip-to-chip, or what have you, but not through transceivers coupled to fibers. Last year at the Intel Developer’s Forum they had a whole silicon photonics demo area but all I saw was fiber optics.

   Which brings us to the cost issue. Verdiell said, “Cost of developing the chips is much higher than for regular transceivers” and isn’t “amortized over volume enough to be competitive (yet).” The second cost issue, Verdiell said, is packaging: “Silicon Photonics does not have a cost and size competitive single’mode packaging solution (yet).” Remember, single mode, as opposed to multi-mode, fibers are the ones capable of transmitting over kilometers.

   The path from electrical signaling to the purist’s Si photonics will include intermediate steps.

   Genuine silicon photonic systems without fibers transmit signals through waveguides integrated into the silicon. Because light doesn’t behave nicely in pure silicon waveguides—due to nonlinearities like two-photon absorption, stimulated raman scattering, and the kerr effect—nicely behaving optical channels are made by depositing polymer waveguides onto the silicon that includes the laser, modulator, and receiver—usually an APD (avalanche photodiode). See Figure 2. These systems don’t require independently packaged transceivers, connectors, and fibers, but they do face the developmental problem of coupling optical signals from pure silicon to polymer.

   Verdiell said that they’re pushing forward.

   Reply
7. June 26, 2015 at 7:20 am

   Tomi Engdahl says:

   EDA Retrospective: 30+ Years of Highlights, Lowlights
   … and what comes next
   http://www.eetimes.com/author.asp?section_id=36&doc_id=1326972&

   Technology journalist Richard Goering is about to retire after 30 years covering electronic design automation. He sums up some important EDA milestones.

   EDA Retrospective: 30+ Years of Highlights and Lowlights, and What Comes Next
   http://community.cadence.com/cadence_blogs_8/b/ii/archive/2015/06/25/eda-retrospective-30-years-of-highlights-and-lowlights-and-what-comes-next

   EDA is a Highlight

   The biggest highlight in EDA is the existence of a commercial EDA industry! Marching hand in hand with the fabless semiconductor revolution, commercial EDA made it possible for hundreds of companies to design semiconductors, as opposed to a small handful that could afford large internal CAD operations and fabs. With hundreds of semiconductor companies as opposed to a half-dozen, there’s a lot more creativity, and you get the level of sophistication and intelligence that you see in your smartphone, video camera, tablet, gaming console, and car today.

   CAE + CAD = EDA. This is not just a terminology issue

   IC functional verification underwent huge changes in the late 1990s and early 2000s, largely due to new technology developed by Verisity, which was acquired by Cadence in 2005.

   Where Does ESL Fit?

   In some ways, electronic system level (ESL) design is both a lowlight and a highlight. It’s a lowlight because people have been talking about it for 30 years and the acceptance and adoption have come very slowly. ESL is a highlight because it’s finally starting to happen, and its impact on design and verification flows could be dramatic. Still, ESL is vaguely defined and can be used to describe almost anything that happens at a higher abstraction level than RTL.

   Where Is EDA Headed?

   Now we come to what you might call “headlights” and look at what’s coming. My list includes:

   System Design Enablement. This term has been coined by Cadence to describe a focus on whole systems or end products including chips, packages, boards, embedded software, and mechanical components. There are far more systems companies than semiconductor companies, leaving a large untapped market that’s looking for solutions.
   New frontiers for EDA. At a 2015 Design Automation Conference speech, analyst Gary Smith suggested that EDA can move into markets such as embedded software, mechanical CAD, biomedical, optics, and more.
   Vertical markets. EDA has until now been “horizontal,” providing the same solution for all market segments. Going forward, markets like consumer, automotive, and industrial will have differing needs and will need optimized tools and IP.
   Internet of Things. This is a current buzzword, but the impact on EDA remains uncertain. Many IoT devices will be heavily analog, use mature process nodes, and be dirt cheap. Lip-Bu Tan, Cadence CEO, recently pointed out that the silicon percentage of IoT revenue will be small and that a lot of the profits will be on the service side.

   Reply
8. June 29, 2015 at 10:08 am

   Tomi Engdahl says:

   JTAG Boundary scan: Four test cases
   http://www.edn.com/design/test-and-measurement/4439727/JTAG-Boundary-scan–Four-test-cases?_mc=NL_EDN_EDT_EDN_weekly_20150625&cid=NL_EDN_EDT_EDN_weekly_20150625&elq=0dd6c755e76142a68941acc7d620b499&elqCampaignId=23611&elqaid=26649&elqat=1&elqTrackId=e11bcf911d7a40eb9cb8503502210184

   When developing a new board, many problems can occur. Bare, unpopulated boards can have shorts and opens that can cause circuits not to work or software to fail once the board is populated. After assembly of components, solder bridges of poor solder joints can cause problems. Fortunately, you can employ Boundary Scan, also known as JTAG or IEEE 1149, to find problems that you can then fix.

   Boundary scan, based on the IEEE 1149.x set of standards, is the structural testing of printed circuit boards and its installed components. Scan results include information on typical electric circuit faults that occur during PCB manufacturing and include bridging (short circuit) faults, opens, stuck-at faults (stuck at 0, stuck at 1), and line breaks.

   Reply
9. June 29, 2015 at 10:10 am

   Tomi Engdahl says:

   Home> Community > Blogs > The EMC Blog
   Beware of hidden antennas!
   http://www.edn.com/electronics-blogs/the-emc-blog/4439771/Beware-of-hidden-antennas-

   There are many causes of radiated emissions and the product designer needs to be able to identify the “hidden antennas” that cause this.

   An important concept to grasp is the electrical dimension of an electromagnetic radiating structure. EMC engineers often call any radiator of electromagnetic energy an “antenna,” whether it is an actual antenna or another radiator, such as a cable or circuit-board trace.

   Figure 1 – An example where two PC bards form a “hidden dipole”. I’m using a Rohde & Schwarz RT-ZD10 1 GHz differential probe to measure the voltage between the connector ground shells of two boards. If the boards are bonded together well enough, the voltage should read zero.

   These dipole structures could include:

   • Cables (I/O or power)
   • PC boards with attached cables
   • Seams/slots in shielded enclosures as they approach 1/2 λ
   • Apertures in enclosures as they approach 1/2 λ
   • Poorly bonded sheet metal (of enclosures)
   • Internal interconnect cables
   • Peripheral equipment connected to the equipment under test (EUT)

   For example, as a cable or slot approaches 1/2-wavelength (or a multiple) at the frequency of concern, it becomes an efficient transmitting or receiving antenna for interference. To reduce the antenna currents (common-mode currents) on these structures, the solution might be to install ferrite chokes or filters on cables and seal up slots in enclosure seams.

   As the structures approach the resonant length of a dipole, their antenna properties become more efficient.

   Reply
10. June 29, 2015 at 2:46 pm

    Tomi Engdahl says:

    Embedded development support needs expansion
    http://www.edn.com/electronics-blogs/embedded-insights/4439791/Embedded-development-support-needs-expansion?_mc=NL_EDN_EDT_EDN_today_20150629&cid=NL_EDN_EDT_EDN_today_20150629&elq=1424320750924042b5cd182614a2d810&elqCampaignId=23656&elqaid=26697&elqat=1&elqTrackId=096cf32c0792407686cc1c48a34ac760

    back then we also had to program everything in assembly language using home-brew tools because there was almost no design support ecosystem available. Embedded development has come a long way since then, including the growth of a substantial ecosystem of tool and software support for processor, yet that support ecosystem may have to dramatically expand again to meet the needs of the coming generations of embedded designs.

    Unlike in the embedded dark ages, performance is not the key factor that developers use when evaluating processors. According to the Embedded Market Studies UBM has conducted annually for more than 20 years, processor performance is a very distant second (45%) to the availability of development tools (71%) in importance when evaluating a processor. It’s almost inconceivable that in today’s market a vendor would introduce a new processor without having a slew of IDEs, debuggers, operating systems, drivers, protocol stacks, and the like ready and waiting.

    Adding network connectivity to an embedded system design seems like it should be straightforward, like adding another peripheral or IO port to the design. It’s not. The link to the network means that the Internet with all of its capabilities and drawbacks now become part of the product. In addition to the protocol stacks and drivers needed for the link itself, the product design will need support for things like remote device provisioning and management, security against cyber-attack, cloud and gateway interactions, browser-based or mobile device user apps, analytics, the ability to deal with slow or lost network connections, and a host of other capabilities.

    Few development teams have expertise in all these areas.

    “Customers don’t want to know how to put an IoT system together,” he said, “they want a solution. They don’t have the bandwidth and knowledge to develop it themselves.” This means that processor vendors are going to have to develop a support ecosystem to provide most of elements needed to meet the network requirements of the IoT.

    But there is still a long way to go. The IoT as a market is highly fragmented. What works for one type of application may be ill-suited to another.

    No vendor today would dream of offering a processor without tool and library support. The availability of tools and libraries does not encourage use of a processor, but their absence certainly discourages processor adoption. In the same way, a decade from now it’s likely that no one would dream of offering a processor without wireless, cloud, apps, security, and other IT support. The IoT will require such functions, and development teams will not want to spend their time acquiring or creating them. They’ll want to spend their time developing their unique value proposition. And for that to happen, the embedded support ecosystem will need to expand substantially.

    Reply
11. June 30, 2015 at 8:24 am

    Tomi Engdahl says:

    Smartphone Saturation Becomes OEM Conundrum
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1327001&

    Smartphone sales are down and OEMs should be worried. Creating new features to enhance brand differentiation is getting harder and harder.

    Phones are generally part of our way of life now. No self-respecting teenager is without one, and they are the businessman’s (and soccer mum’s) most valuable tool. Most of us can’t remember life before the cell-phone.

    Our somewhat irrational desire for more and better led us to replacing the phone every two years. Telco contracts even encouraged that

    Sadly, the days of massive improvements in features in a new release are behind us.

    The reality is that phone features are about capped out. There isn’t a whole lot more they can do. Moreover, everything Apple can do, Android does too! (A secret here: It was never the hardware that mattered. It was always software, and the only reason for a hardware upgrade was to get the new software features and perhaps to have enough memory to run them.)

    Reply
12. June 30, 2015 at 8:25 am

    Tomi Engdahl says:

    Carbon Nanotubes Are Ready for Prime Time
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1326993&

    Carbon nanotubes’ material cost is now a negligible in overall chip cost, making memory-based on carbon nanotubes more compelling than ever. Including NRAM.

    Demand for a new generation of memory that combines high speed and nonvolatility, as well as scalability below 5nm, is now stronger than ever. After years of development and testing, carbon nanotubes (CNTs) have proven to be the most suitable material for to deliver fast, high-density, low-power memory.

    And CNTs are no longer only found in research labs. A number of production fabs have been quietly and successfully using CNTs without issues. Not only have CNTs been proven to work on leading-edge CMOS fabrication lines with no new tools or processes required, the cost of the CNT material on a per-chip basis for memory has been reduced by more than 10X also in the last two years alone. This means the CNT material cost is now negligible with respect to chip cost, making the value proposition of CNT memory more compelling than ever.

    In fact, the potential for CNTs to be used anywhere silicon is used is significant, and a number of devices can be fabricated beginning with nonvolatile random access memory (NRAM), as well as sensors, transistors and interconnects.

    Reply
13. June 30, 2015 at 8:27 am

    Tomi Engdahl says:

    Back in the Driver’s Seat on Global Trade
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1327005&

    The Trade Promotion Authority (TPA) is a major victory for free trade and the semiconductor industry, says CEO of the Semiconductor Industry Association.

    It’s no secret the semiconductor industry thrives on free trade. The customers, suppliers, and R&D providers chip companies rely on are located across the globe, from New York to New Delhi. Free and open access to global markets helps our industry spur economic growth, create jobs, and make new discoveries.

    Congress last week scored a major victory for free trade by approving an initiative called Trade Promotion Authority (TPA), which makes it easier for the United States to strike deals on free trade agreements. President Obama signed TPA into law earlier today (June 29).

    The semiconductor industry, in particular, stands to gain from TPA. Eighty-two percent of U.S. semiconductor companies’ customers are outside the United States. TPA will make it easier for semiconductors to reach those customers and remain one of America’s top exports. Additionally, the U.S. semiconductor industry directly employs nearly 250,000 people in high-skilled, high-wage jobs in America, and free trade is critical to creating and supporting these U.S. jobs.

    But let’s not lose sight of the fact that TPA is really a means to an end. With TPA passage, the United States is in a far stronger position to get the Trans-Pacific Partnership (TPP) across the finish line this year.

    Reply
14. June 30, 2015 at 8:30 am

    Tomi Engdahl says:

    MRAM Maker Everspin Remembers Its Industrial Roots
    http://www.eetimes.com/document.asp?doc_id=1326992&

    Magnetoresistive RAM (MRAM) is one of those memories that is still relatively niche and poised to replace conventional memories in some applications. What makes it even more unique is that only one company has really made any progress in getting it to market.

    Everspin Technologies recently announced that Koyo Electronics Industries is designing Everspin’s MRAM into its Direct Logic 205 (DL205) Series programmable logic controllers (PLCs). Koyo manufactures automotive equipment and factory automation systems; one of its major Japanese automotive customers was looking for a PLC that does not require battery backup. Everspin’s MRAM fit the bill with its instant event save function in case of power loss, Everspin’s VP of marketing Scott Emley said in an interview with EE Times, and it is also well-suited for harsh environments.

    Koyo Electronics is using 1-Megabit parallel interface (MR0A16A) MRAM from Everspin in its DL205 Series PLCs and expansion modules. This type of industrial application is “old hat” for Everspin, said Emley. “It’s where we started. We continue to pay attention to the market we’ve been developing over past eight years.”

    While industrial and automotive applications have been Everspin’s bread and butter, Emley said the company is looking at broader uses for both its MRAM and Spin-Torque MRAM (ST-MRAM), particularly for applications that require data persistence and integrity, low latency, and security.

    A Coughlin Associates report released last year suggested MRAM was poised for a 50% compound annual growth rate, with MRAM and STT-MRAM revenue increasing from about $190 million in 2013 to $2.1 billion in 2019, with one of its most appealing aspects being its compatibility with CMOS processes.

    Reply
15. June 30, 2015 at 8:32 am

    Tomi Engdahl says:

    Wafer-Level Packaging Not Enough, say OSATS
    Larger chips, higher I/O counts vs. rapiding shrinking device sizes
    http://www.eetimes.com/document.asp?doc_id=1326998&

    The focus of the discussions there was on large format fan-out packaging, or the necessity that OSATS felt, under yield and packaging cost pressures, to move from Fan-Out Wafer-Level-Packaging (FO-WLP) to Fan-Out Panel-Level-Packaging (FO-PLP).

    She illustrated this with seven generations of iPhones, thinning from around 12mm to 7mm while increasing their WLP content from 2 dies to over 26 dies.

    The conventional WLPs trends, she said, include higher I/O counts and larger dies. And together with shrinking geometries, the number of I/Os per die dramatically increased over the years from a few dozens to well over 400, calling for multi-die packages or a move to larger FO-WLP where the I/Os can be distributed not only underneath the die but at the package’s periphery (like extra margins surrounding the die).

    Typically, FO-WLP benefit from the same thinness (under 0.4mm) but can integrate multiple dies from different technology nodes, as well as some passives. Nanium offered a good example by moulding together two active dies and 10 surface-mounted passives within a 9x8mm package.

    As the declining average selling price for end products creates further price pressure, it drives OSATS to develop lower cost package options too, moving to large area packaging beyond today’s wafer sizes. “This is where the wafer fab side, back end assembly, and PCB segments are merging” she said.

    Reply
16. June 30, 2015 at 9:13 am

    Tomi Engdahl says:

    DAC Trip Report: Expanding EDA’s Charter & Topical Hardware Emulation
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1326999&

    Dr. Lauro Rizzatti paid close attention to trends at DAC two weeks ago and wrote them up in a trip report for EETimes readers.

    Today, 20% of Mentor’s revenue is generated by the automotive industry. It seems that of the three EDA leaders, Mentor is the one with the deepest penetration into this different world of design automation.

    As for the IoT, a presentation that will stay with me for long time was delivered by Brian Otis from Google in his Monday keynote. He described at length the development of a Smart Lens to monitor the level of glucose in the human body to detect the presence or the potential presence of diabetes. The lens includes an entire digital computer, a sensor, RF circuitry, and antenna to connect it to the cloud for uploading and processing the monitored data. A minuscule capacitor accumulates enough energy collected from the cloud to keep the circuit alive and working. It is mindboggling. In fact, I know that Google is using hardware emulation, but it may or may not be for this application.

    Hardware emulation had its own buzz on the exhibit floor. I lost count of the number of attendees who stopped me to talk about emulation this year. It’s seemingly on everyone’s mind. And, yes, the “big three” EDA vendors who are also emulation suppliers have been listening and responded to project teams’ needs with additional capabilities and use models.

    When asked how he used emulation and for what during a panel session, a well-known and respected verification engineer smiled and said, “Everything.” He’s not the only one. I heard around the DAC exhibit floor that emulation saved at least one recent chip design project from failure and an expensive respin.

    In fact, it’s not only topical, it’s gone mainstream. Design and verification teams are using it. Software developers have become believers. Big groups dispersed all over the world are delighted emulation has become a data center resource… and none too soon.

    An executive from one of the big three has been known to remark that emulation is the fastest growing segment of the EDA business. It is the cheapest form of verification available today; especially considering the fact that a respin at 14nm would cost several million dollars. Save one respin and the project team paid for a large emulation platform that can be reused for many more designs.

    Reply
17. June 30, 2015 at 9:26 am

    Tomi Engdahl says:

    Etching PCBs With A 3D Printer
    http://hackaday.com/2015/06/29/etching-pcbs-with-a-3d-printer/

    There are dozens of circuit board printers out there that lay down traces of conductive ink and ask you to glue down components to a fragile circuit board. This is a far cry from the old way of making PCBs, but these printers are going gangbusters, cashing in on the recent popularity of hardware startups and rapid prototyping.

    People who think deeply about a problem are few and far between, but lucky for us [Arvid] is one of them. He’s come up with a way of creating PCBs with any 3D printer and steel rod. The results are better than anything you could make with a circuit board printer, and the technique is very, very cheap.

    [Arvid] is using the traditional method of etching away copper, just some ferric chloride and a bit of time.

    Making PCB with 3D printer and permanent marker
    https://www.youtube.com/watch?v=sNh0ubRcTYU

    Reply
18. July 1, 2015 at 7:44 am

    Tomi Engdahl says:

    Synopsys Acquires Elliptic Technologies, Beefs up Security
    http://www.eetimes.com/document.asp?doc_id=1327012&

    EDA software company Synopsys, Inc. announced (June 29) its acquisition of security intellectual property company Elliptic Technologies. Elliptic, a founding member of the prpl Foundation’s Security Working Group, has been working on an open security framework for deploying secured and authenticated virtualized services in the IoT and related emerging markets. Its security IP is already in many devices, from mobile, automotive, digital home, Internet of Things (IoT) and cloud computing applications, according to the press release.

    Synopsys also recently announced acquisition of Codenomicon and plans to acquire Quotium’s Seeker product.

    Synopsys Expands Security Solutions with Acquisition of Elliptic Technologies
    Acquisition Complements DesignWare IP Portfolio with a Broad Range of Security IP
    http://news.synopsys.com/2015-06-29-Synopsys-Expands-Security-Solutions-with-Acquisition-of-Elliptic-Technologies

    Reply
19. July 1, 2015 at 7:46 am

    Tomi Engdahl says:

    Micron Remains Optimistic Despite Down Quarter
    http://www.eetimes.com/document.asp?doc_id=1327008&

    Micron Technology was bullish about the coming year at a conference in May, but its latest quarterly earnings released in late June have investors less optimistic.

    Micron’s competitors appear to be doing better with regards to DRAM, as new numbers from IHS show that Samsung saw its DRAM sales reach a record level in the first quarter of this year; its market share also hit its highest since 2011 at more than 44%. Samsung shipped $5.28 billion worth of DRAM products in the first quarter of 2015, up more than 41% compared with the same quarter last year. SK Hynix came in second, grabbing nearly 28% of the global market by shipping $3.31 billion worth of DRAM. Micron was third, selling $2.53 billion and taking just over 21% of the market.

    Right now, roughly 30% of the company’s DRAM business is focused on PCs, 25% on mobile applications, 20% on enterprise and cloud data center servers with the remaining on networking, industrial and automotive applications. At the beginning of June, it expanded its flash storage portfolio with new TLC NAND built on its 16nm process for use in USB drives and consumer SSDs. It also highlighted that its automotive-grade eMMC hit all-time high record sales. Micron also sees opportunities in mobile and in-memory computing.

    The growth of onboard infotainment systems and connected vehicles makes the automotive segment worth Micron’s focus.

    Reply
20. July 1, 2015 at 7:49 am

    Tomi Engdahl says:

    8 FD-SOI Questions You’re Afraid to Ask
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1326997&

    Paul Boudre, CEO of Soitec, told us last week in Grenoble, “Evidence [for FD-SOI’s advantages] is there. But some choose not to see it.”

    To be fair, FD-SOI is a technology three decades in the making and perfecting. FD-SOI’s genuine advantage wasn’t obvious at process nodes such as 40nm or 32nm, but “we are seeing a window [of opportunity] now at 28-nm node,” said Marie-Noëlle Semeria, CEA-Leti CEO, during the Leti’s open house event last week.

    As “small things that are highly connected” become the focus of innovation for mobility and IoT, she explained FD-SOI is a critical ingredient that enables low-power, low-cost, connected miniature products.

    Reply
21. July 1, 2015 at 7:54 am

    Tomi Engdahl says:

    Sneak Peak! RTOS Smackdown at ESC Silicon Valley 2015
    http://www.eetimes.com/author.asp?section_id=216&doc_id=1327015&

    At ESC Silicon Valley, seven of the leanest, meanest, coolest, hottest contenders in the RTOS multi-universe will take it in turns to explain why their RTOS is the bestest of the best.

    Following a meandering introduction by yours truly, the proceedings will kick off with one industry expert playing the Devil’s Advocate by arguing that an RTOS is superfluous to requirements and that we shouldn’t even think about using one. A second industry expert will then seize the microphone and contend that an RTOS is an invaluable, “must-have” asset, even if your embedded application performs only a handful of tasks.

    After the dust dies down, proponents of seven of the leanest, meanest, coolest, hottest contenders in the RTOS multi-universe will take it in turns to explain why their RTOS is the bestest of the best.

    The end result will be an action-packed, fun-filled session that will leave attendees dazed and delighted and saying things like “Well, I never knew that” and “Max is even more magnificent than I expected.” Have you signed up for ESC Silicon Valley yet? If not, why not?

    Reply
22. July 1, 2015 at 7:59 am

    Tomi Engdahl says:

    Back in the Driver’s Seat on Global Trade
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1327005&

    The Trade Promotion Authority (TPA) is a major victory for free trade and the semiconductor industry, says CEO of the Semiconductor Industry Association.

    It’s no secret the semiconductor industry thrives on free trade. The customers, suppliers, and R&D providers chip companies rely on are located across the globe, from New York to New Delhi. Free and open access to global markets helps our industry spur economic growth, create jobs, and make new discoveries.

    Reply
23. July 2, 2015 at 7:26 am

    Tomi Engdahl says:

    Talking Sheets, Thinking Shorts
    RFID chips, antennas are woven into a yarn
    http://www.eetimes.com/document.asp?doc_id=1327013&

    The tagging of garments via RFID-based labels has been commonplace for more than a decade. But what if electronic components could be threaded into the very fabric of clothes and even survive the washing machine?

    Enter Primo1D, an E-Thread company based in Grenoble.

    The startup has effectively pushed the concept of “wearables” to new extremes.

    Instead of wearable devices typically housed in an external electronics package that can be inserted into (or removed from) a slot in clothing, Primo1D developed a microelectronic package that allows an RFID chip to be directly connected to a set of two conductive wires ( which function as antennas) and woven into a yarn. Within the E-Thread is a passive RFID tag that requires no power supply and can be read by any standard UHF RFID reader.

    Emmanuel Arene, Primo1D CEO, told EE Times that he expects his company to generate its first revenue in 2016. The initial applications of E-Thread technology will be in linens and textile products used by hospitals and hotels, which need to be professionally laundered and whose inventories need to be managed.

    We buy 8-inch wafer-level chips from Impinj. Then we add process steps on wafers so that we can make these packages durable,” explained Arene. That process technology was originally developed in a clean room by CEA-Leti.

    Primo 1D’s E-Thread solution is protected by 20 patents

    Reply
24. July 2, 2015 at 10:49 am

    Tomi Engdahl says:

    Intel Becomes An ARM Chip Maker
    http://seekingalpha.com/article/3229806-intel-becomes-an-arm-chip-maker

    Intel has announced the purchase of Altera for $16.7 billion.
    Altera’s product portfolio includes ARM chips fabricated on Intel’s most advanced process.
    Intel has indicated that it will allow fabrication of Altera’s ARM chips to continue, even into the next more advanced fabrication process.

    Reply
25. July 2, 2015 at 11:12 am

    Tomi Engdahl says:

    Workshop opened my eyes to the latest in test
    http://www.edn.com/design/test-and-measurement/4439800/Workshop-opened-my-eyes-to-the-latest-in-test?_mc=NL_EDN_EDT_EDN_today_20150701&cid=NL_EDN_EDT_EDN_today_20150701&elq=e786f3605ce5425e977be6f48875ce19&elqCampaignId=23714&elqaid=26783&elqat=1&elqTrackId=8c548290f2124796a85f937cd32d04b2

    Oscilloscope lab
    The oscilloscope lab began with spending some time to familiarize ourselves with the basic ergonomics of the touch-screen interfaces on the Infiniium oscilloscopes

    we began the first part of the lab, observing the voltage and current fluctuations in a USB interface, and using this to compute the energy consumption of a mouse

    We used a USB breakout board to measure the signals from a mouse.

    To make the measurement, we used a current probe and a typical 10:1 voltage probe, then multiplied the signals to derive the mouse’s power waveform.

    Analyzing wireless RF signals

    Network analyzer measurements
    In the final lab of the day, we learned how to use a network analyzer to characterize passive and active RF devices. We began by exploring the user interface of Keysights new E5080A ENA vector network analyzer.

    Reply
26. July 2, 2015 at 11:17 am

    Tomi Engdahl says:

    Address E-band cost and reliability issues in MMIC packaging
    http://www.edn.com/design/systems-design/4439805/Address-E-band-cost-and-reliability-issues-in-MMIC-packaging?_mc=NL_EDN_EDT_EDN_today_20150701&cid=NL_EDN_EDT_EDN_today_20150701&elq=e786f3605ce5425e977be6f48875ce19&elqCampaignId=23714&elqaid=26783&elqat=1&elqTrackId=e0c5c433c641409d91e52fe45cdeba31

    Millimeter-wave RF systems have great potential for automotive applications, if they can be made cost effective. Traditional semiconductor packaging approaches are either far too expensive or suffer from signal integrity issues at the frequencies involved. But new techniques are becoming available that can address these problems.

    Whether it’s highway cruising or neighborhood trip, automobile travel would be far safer, especially at night and in bad weather, if all new cars were equipped with long-range, radar-based collision-avoidance systems. Shorter-range collision avoidance systems now in the market, typically operating at 24 GHz, can activate braking and tighten seat belts before an imminent front or rear crash. But long-range systems can warn drivers well in advance that they are closing on slower vehicles or obstructions not yet in their line of sight, and can dynamically adjust the speed of cruise controls to avoid the need for sudden braking.

    Such long-range systems operate in the millimeter-wave domain, specifically between 76 GHz and 77 GHz in the E band, to provide better object resolution and extended reach compared to the collision-avoidance radar systems that operate at 24 GHz.

    For their part, semiconductor companies have not been remiss, with cost-saving CMOS E-band transceiver chips recently announced as near-future alternatives to SiGe devices already in production. But although economy at the die level would help, the real concern is not semiconductor processes but interconnects. How do you maintain the integrity of millimeter-wave signals going between a chip and its package, between the package and a PCB, across a PCB, and through a connector at the board edge, using inexpensive, high-yield technologies compatible with existing volume manufacturing and assembly practices? Approaches common to military and aerospace radar systems, for which cost is no object, are unfeasible.

    Chip packaging

    Packages for millimeter-wave devices typically are constructed on ceramic substrates that route controlled-impedance microstrip or coplanar waveguide interconnects up to the mounted chip, which connect to the die by wire bonds, or flip-chip bumps. But even the shortest wire bond that can be produced acts as an inductor at such frequencies, as do bumps. Neither are impedance-controlled structures. This means that a matching network is necessary within the package to cancel the effect of each bond wire’s or bump’s stray inductance and thereby maintain signal integrity everywhere along the path from each die pad outward within the package. Unfortunately, the matching networks, though needed to prevent signal reflections, tend to limit the bandwidth the package can serve.

    Yet QFN cavity-type plastic packages are in use with MMICs (monolithic microwave ICs) that operate at 24 GHz. The packages have standard JEDEC outlines and footprints compatible with pick-and-place machines and surface-mount assembly processes. The main limitation for using those packages at the higher, millimeter-wave frequencies is the bond wire.

    But this is changing, making SMT plastic packages practical for millimeter-wave devices. A new commercial manufacturing process is becoming available that can transform bond wires into coaxial connections with tightly-controlled impedance characteristics

    Bond wires are only one step. To ensure signal integrity from the PCB, into the package, through the internal connections, and to the chip the whole signal path should be viewed as a waveguide. Fortunately, lead frames, if properly architected, can behave as impedance-controlled waveguide structures, and waveguide structures can also be built on the substrate.

    JEDEC does not define the dimensions and spacing internal to the QFN package, merely the external elements, so package developers have the freedom they need.

    Reply
27. July 2, 2015 at 1:15 pm

    Tomi Engdahl says:

    LG Chem develops hexagonal battery
    https://www.koreatimes.co.kr/www/news/tech/2015/06/133_181765.html

    LG Chem has started shipping hexagon-shaped batteries to global consumer electronics firms in order to help them promote their smart-watch business.

    광고
    “LG Chem has started selling hexagonal batteries to global tech firms,” company spokesman Woo Byeong-min said Sunday. “The batteries, manufactured in Nanjing, China, where LG operates massive battery factories, will be used in upcoming smart watches.”

    LG said the hexagon-shaped battery improved storage capacity by 25 percent compared with rectangular batteries.

    “The development will help users have four hours more for their smart watch,”

    Gartner, a market research firm, expects smart watches to make up at least 40 percent of wearable devices by next year.

    Reply
28. July 3, 2015 at 7:12 am

    Tomi Engdahl says:

    Ian King / Bloomberg Business:
    Intel President Renée James stepping down to seek CEO role elsewhere
    http://www.theglobeandmail.com/report-on-business/international-business/us-business/intel-president-steps-down-to-seek-ceo-role-elsewhere/article25226400/

    Intel Corp. president Renée James will step down to seek a chief executive officer role elsewhere, in a reshuffle that cements CEO Brian Krzanich’s control over the world’s largest chip maker.

    Intel’s highest-ranking woman, who sent a letter to employees Thursday, didn’t specify where her next job will be.

    Reply
29. July 3, 2015 at 8:51 am

    Tomi Engdahl says:

    New Part Day: Memristors
    http://hackaday.com/2015/07/02/new-part-day-memristors/

    For the last few years, the people in the know have been wondering about the memristor. The simplest explanation of what a memristor is comes from the name itself – it’s a memory resistor. In practice it’s a little more complex

    Now you can buy one. Actually, you can buy eight in a 16-pin DIP package. It will, reportedly, cost $240 for the 16-pin DIP. That’s only $30 per memristor, and it’s the first time you can buy them.
    http://www.bioinspired.net/products-1.html

    These memristors are based on a silver chalcogenide (Ge2Se3). When a circuit ‘writes’ to this memristor and applies a positive voltage, silver ion migrate to the chalcogenide, forming what the datasheet (PDF) calls dendrites. This lowers the resistance of the memristor. When a negative voltage is applied to the device, these dendrites are removed, the memristor is ‘erased’, and the memristor returns to a high-resistance state.

    This silver chalcogenide memristor is different from the titanium oxide memristors developed by HP Labs that is most frequently cited when it comes to this forgotten circuit element.

    As far as applications for memristors go, there are generally two schools of thought on that. The most interesting, in terms of current computer technology, is storage. Memristors can hold either a binary 0 or a 1 in a fraction of the space NAND Flash or old-fashioned magnetic hard drives ever will.

    The second major expected use for memristors is neural nets.

    Reply
30. July 3, 2015 at 9:54 am

    Tomi Engdahl says:

    Biodegradable Electronics Debut
    Landfills safely dispose of the obsolete
    http://www.eetimes.com/document.asp?doc_id=1327040&

    Today our landfills are being overrun by discarded electronic devices fabricated on silicon substrates that do not biodegrade for decades or even longer if left in their sealed plastic cases.

    The Electronics TakeBack Coalition (Oakland, Calif.), for instance, estimates that over 55 million tons of old smartphones, personal computers, televisions and other silicon-based devices are discarded each year, only about 14 percent of which are recycled. But if researchers at the University of Wisconsin-Madison have their way, the same-silicon-based devices will biodegrade in just a few weeks in the environment of a landfill. An additional advantage to these cellulose nano-fibrillated fiber (CNF) substrates is that they are transparent and flexible yet able to handle almost any high-speed (300-MHz to 300-GHz) silicon electronic or radio-frequency circuit transferred to them.

    According to professor Zhenqiang (Jack) Ma at the University of Wisconsin-Madison, after transferring single-crystal silicon circuitry to the CNF substrate, their normal lifetime within the smartphone, or other similar electronic device, is the same as if it was left on its original silicon substrate.

    “The lifetime of our biodegradable transistors are of no difference from the regular transistors. As long as the transistors are not put into touch with fungi together with moisture, they will not degrade at all,” Ma told EE Times. “Their performance is also the same, because our transistors are also made of single crystal silicon. There is no difference at all.”

    “I really want to push the application into many devices including smartphones, but it may take some time, say a few years,

    The U.S. Environmental Protection Agency reports that over 152 million mobile devices are discarded every year, only 10 percent of which are recycled, nevertheless the EPA may lack the power and motivation to force manufacturers to adopt the new CNF substrates, which after all only solve a part of the problem (the plastic case and toxic chemicals used will still be going into the landfills).

    CNF substrates could be inexpensively manufactured from the cellulose found in wood fibers

    Reply
31. July 3, 2015 at 9:55 am

    Tomi Engdahl says:

    FinFETs + FD-SOI Proposition: May Save Power
    Why not combine best-of-both worlds?
    http://www.eetimes.com/document.asp?doc_id=1327035&

    In the typical black-or-white / one-or-the-other manner in which many of us think, the choice that most semiconductor makers have made is FinFET (finned field effect transistors) or FD-SOI (fully depleted silicon-on-insulator). However, since the foundries like the Taiwan Semiconductor Manufacturing Company, Limited (TSMC), GlobalFoundries Inc. (Santa Clara, California) and Samsung (Seoul, South Korea) have to offer both capabilities to their customers, more semiconductor manufacturers are considering offering the best-of-both-worlds.

    Freescale Semiconductor, Inc. (Austin, Texas), for instance, has just revealed to EE Times that it is using FinFETs for the 14-to-16 nanometer node as well as FD-SOI for 28-nanometer to achieve the same goal—faster speed and lower power consumption—but for different segments of their semiconductor portfolios. They are also toying with the idea of combining the two for next-generation semiconductor nodes.

    Martino even suggested that the future may hold some surprises by merging the best-of-both-worlds from the FinFET versus SD-SOI debate—perhaps merging the two at next-generation semiconductor nodes—while simultaneously maintaining the 28-nanometer FD-SOI for lower-end devices for many years into the future.

    Reply
32. July 3, 2015 at 9:56 am

    Tomi Engdahl says:

    News & Analysis
    IBM-GlobalFoundries Deal Finalized
    http://www.eetimes.com/document.asp?doc_id=1327029&

    Following final approval by U.S. regulators, IBM closed the sale of its chip manufacturing operations to GlobalFoundries. IBM will pay $1.5 billion to the world’s second largest chip foundry.

    GlobalFoundries will be IBM’s exclusive semiconductor processor technology provider for the next 10 years. The deal could expand GlobalFoundries’ current capacity by more than 10%.

    IBM’s fabs had been losing significant money in recent years

    Under the deal, GlobalFoundries will get ownership of more than 10,000 IBM semiconductor patents. No layoffs or plant closures are anticipated by either company.

    Reply
33. July 6, 2015 at 9:33 am

    Tomi Engdahl says:

    Micron fires off some in-memory flash data rockets
    New unit will go beyond selling chips and standard components
    http://www.theregister.co.uk/2015/06/26/microns_inmemory_flash_data_rockets/

    Micron’s Storage Business Unit (SBU) wants to shake up the server status quo with a dynamic upstart duo: in-memory app accelerating data processing rockets and instant access, cold data flash vaults.

    How it’s going to do that begins with its NAND chip development plans, which we learned about at a Silicon Valley briefing. It starts at the chip level.

    Reply
34. July 6, 2015 at 1:00 pm

    Tomi Engdahl says:

    Could India’s Analog Wafer Fab be Moving South?
    http://www.eetimes.com/document.asp?doc_id=1327053&

    Cricket Semiconductor, a company set up with the purpose of building and operating $1 billion analog and power semiconductor wafer fab in India has been in talks with state government of Telangana, according to a report in the New Indian Express.

    Reply
35. July 6, 2015 at 1:01 pm

    Tomi Engdahl says:

    Intel President, Execs Step Down
    http://www.eetimes.com/document.asp?doc_id=1327042&

    Intel President Renée James is among several top executives who announced plans to resign from the chip giant. Three other executives from various divisions will also leave the company.

    During her past two years as president, James has been second in-command to CEO Brian Krzanich. She became responsible for manufacturing, software, security tech, and corporate strategy/planning following a 2013 reorganization.

    “I have made the very difficult decision to step down as President of Intel in order to pursue an external CEO role,”

    James’ announcement will result in reorganization

    Reply
36. July 6, 2015 at 2:51 pm

    Tomi Engdahl says:

    Merger-mania: Has test and measurement gone MAD?
    http://www.edn.com/electronics-blogs/test-cafe/4439792/Merger-mania–Has-test-and-measurement-gone-MAD-?_mc=NL_EDN_EDT_EDN_today_20150706&cid=NL_EDN_EDT_EDN_today_20150706&elq=6da8f422e79d457c8c484bfe7d684d14&elqCampaignId=23773&elqaid=26852&elqat=1&elqTrackId=e2a7befb079346379c449e97653ada2c

    Keysight acquiring Anite. Teradyne acquiring Universal Robotics. Cobham acquiring Aeroflex. Danaher splitting in two, divesting Tektronix. Has the industry gone MAD?

    Yes, but not crazy mad or angry mad. MAD, as in mergers, acquisitions, and divestitures. The pace of MAD has recently accelerated.

    The key to MAD success in this dance is twofold: find the right partner, do the right dance steps. Do this right, and 1 + 1 = 3. Synergy! Do it wrong, and 1 + 1 = 1.5. Loss of value.

    Reply
37. July 6, 2015 at 2:52 pm

    Tomi Engdahl says:

    Top-cooled GaN transistor handles 60 A
    http://www.edn.com/electronics-products/other/4439844/Top-cooled-GaN-transistor-handles-60-A?_mc=NL_EDN_EDT_EDN_today_20150706&cid=NL_EDN_EDT_EDN_today_20150706&elq=6da8f422e79d457c8c484bfe7d684d14&elqCampaignId=23773&elqaid=26852&elqat=1&elqTrackId=15bc8bbcb6404a3387a93647571f1fd5

    GaN Systems’ latest addition to its range of enhancement-mode GaN-on-silicon high-power transistors, the GS65516T 650-V power switch boasts a continuous drain-current rating at 25°C of 60 A, while leveraging topside cooling and a low-inductance, thermally efficient package that is just 9.0×7.6×0.45 mm. Topside cooling allows the part to be cooled using conventional heat-sink or fan-cooling techniques, while dual gate pads help design engineers achieve optimal board layout.

    The GS65516T E-mode HEMT provides an on-resistance of 27 mΩ, reverse-current capability, integral source sense, and zero reverse recovery loss.

    Reply
38. July 7, 2015 at 5:55 am

    Tomi Engdahl says:

    With the increasing hardware and software complexity in today’s SoCs, designers need more from their IP providers to help meet their project schedules. Delivering IP blocks alone is no longer adequate to address their growing SoC design and integration challenges. Designers require solutions that ease IP configuration and integration into the overall SoC and accelerate their software development effort.

    Source: https://webinar.techonline.com/19810?elq_mid=6872&elq_cid=303473&elq=c213b32eb62f4e8cb53006f530c173fc&elqCampaignId=434&elqaid=6872&elqat=1&elqTrackId=034ec15d18b24e9c9379e696fee2f626

    Reply
39. July 7, 2015 at 6:55 am

    Tomi Engdahl says:

    8 Views of the Chip Horizon
    It’s crunch time (again) for EUV lithography
    http://www.eetimes.com/document.asp?doc_id=1327056&

    BRUSSELS — Looking down the semiconductor road map, researchers at the Imec research institute see small, medium and large challenges on the horizon. In presentations and interviews at their annual event here, they and some of their partners shared a bit of what’s ahead.

    Reducing costs per transistor at the next-generation, the 10nm node, will be tricky. Even more challenging will be getting extreme ultraviolet lithography ready to enable a full 7nm node.

    Further out, scaling to and beyond the 5nm node may require a whole new kind of chip technology. Increasingly experts speculate the answer will emerge as some sort of stacking that is not yet on the whiteboard.

    The mid-term challenges are currently the most pressing. The 7nm process will be an expensive half node if the long delayed extreme ultraviolet lithography systems are not ready for early production in 2017.

    Researchers here are upbeat EUV will arrive in time, but there are plenty of challenges ahead

    “We are confident EUV will enter manufacturing most likely starting at the 7nm node,” Luc Van den Hove, chief executive of Imec said at a press conference here.

    Reply
40. July 7, 2015 at 6:56 am

    Tomi Engdahl says:

    TSMC Overtakes Intel in Chip Capex Ranking
    http://www.eetimes.com/document.asp?doc_id=1327060&

    Intel, the world’s largest chip company, is set slip to third place in a ranking of chip companies compiled by Semico Research, based on forecast capital expenditure in 2015.

    The other notable move in the top 15 ranking is the projected year-on-year doubling of capex planned by Sony for the manufacture of CMOS image sensors to take it to $2 billion and seventh position.

    In 2015 the total spend across the industry is set to be $68.7 billion, up 9 percent from $63.3 billion in 2014.

    The top 15 companies account for 89 percent of the total spending. Samsung retains a top spot it held in 2014 but foundry TSMC jumps to second place overtaking Intel. At positions four and five Globalfoundries switched positions with SK Hynix as the foundry expects to increase spending 22 percent this year versus Hynix’s 5 percent increase.

    The bulk of Sony’s increased capex is to expand CMOS image sensor production capacity, but some will also be spent on camera module production capacity, a relatively new market for Sony.

    Reply
41. July 8, 2015 at 2:53 pm

    Tomi Engdahl says:

    Nano Wires replace the LEDs in five years?

    LEDs are rapidly replacing traditional incandescent bulbs, but LED dominance will not be long-lived, if Danish researchers, the vision is realized. Niels Bohr Institute has found that with nano wires different colors can be produced with significantly lower power consumption than currently used LEDs.

    Nano wires have a length of two microns and a thickness of 10-500 nanometers tubes which consist of galliumnitride core and indium gallium nitride outer layer. Both materials are semiconductors.

    Nano tuube advantage is that they need to radiate light to only a fraction of the energy of the LED needs. In addition, the radiant light is more natural LEDs.

    Source: http://etn.fi/index.php?option=com_content&view=article&id=3014:nanojohdot-korvaavat-ledit-viidessa-vuodessa&catid=13&Itemid=101

    Reply
42. July 8, 2015 at 3:03 pm

    Tomi Engdahl says:

    GaN technology and the potential for EMI
    http://www.edn.com/electronics-blogs/the-emc-blog/4439839/GaN-technology-and-the-potential-for-EMI?_mc=NL_EDN_EDT_EDN_today_20150708&cid=NL_EDN_EDT_EDN_today_20150708&&elq=db178978bd0643008a659ebb5fe80a32&elqCampaignId=23816&elqaid=26897&elqat=1&elqTrackId=3811ffc80fb24e6bacd7ab580cdd0362

    Because of the fast switching speeds and related higher efficiencies of these new power switches, we’ll expect to see them primarily applied to switch-mode power supplies and RF power amplifiers. They may broadly replace existing MOSFETs and have lower “on” resistance, less parasitic capacitance, are smaller, and faster. I’m already noticing new products using these devices. Other applications include telecom DC-DC, wireless power, LiDAR, and class D audio. Obviously, any semiconductor device that switches in a few picoseconds is likely to generate large amounts of EMI. In order to evaluate these GaN devices, Sandler arranged for me to test some evaluation boards.

    Summary

    The value of GaN power switches is clear, in that efficiencies are vastly better than MOSFET devices. While GaN technology is here to stay, I see little information on how these picosecond switching devices might affect product EMC emissions. I’ve listed a few references below and hate to be a “party-pooper” on the GaN bandwagon, but I believe much more study needs to be done in EMI consequences. As for us EMI engineers and consultants, it appears we’ll be employed for years to come!

    Reply
43. July 8, 2015 at 3:05 pm

    Tomi Engdahl says:

    Home> Analog Design Center > How To Article
    Is a general-purpose Analog Front-End practical?
    http://www.edn.com/design/analog/4439831/Cleanly-elegant–Overfeatured–Too-expensive–Is-a-general-purpose-Analog-Front-End-practical-?_mc=NL_EDN_EDT_EDN_today_20150708&cid=NL_EDN_EDT_EDN_today_20150708&&elq=db178978bd0643008a659ebb5fe80a32&elqCampaignId=23816&elqaid=26897&elqat=1&elqTrackId=f29320a7861a4dff8d4658e2a2ca9831

    Most engineers with a few years’ experience have encountered “feature creep”—the tendency to keep adding extra features onto a piece of equipment so the original product becomes more complicated and more difficult to use. Meanwhile, there is also a real danger that we will burden every customer with the cost of things/features that only a small percentage of them need or want. This is exactly the problem with a general-purpose analog front-end (AFE).

    Now, turn back to our main subject, the AFE. An AFE connects our analog world to a digital processor so decisions can be made. A first reaction might be, “let’s make a universal AFE,” a design that will work for every application. As we start, reality sets in. The list of sensors, voltage-limiting devices, current-limiting devices, risetime reducers, and many other devices (Table 1) to accommodate gets really long, really fast. So, how can a general-purpose AFE really be elegant? Can it have too many features? Then be too expensive? We think so.

    For the last few years many schools have taught digital computer science to engineering students, but addressed very little analog engineering. Consequently, it is not unusual to find a small company with many digital and computer engineers, but no one with analog engineering knowledge. Faced with critical projects and the lack of analog expertise, some managers may think: “The project is mostly digital. Only a few percent is analog and it is in the front-end. I’ll just assign someone to pick up the analog.” Now the digital engineer has to scramble to develop new expertise. Many AFE reference designs are available, but they tend to be very application specific. In practice, the general-purpose AFEs do not usually help much.

    What about a machine’s interface to the analog world? Is a general-purpose AFE better than one specific to an application? No. Experience tells us that “one size,” a general AFE design, does not fit all because of the large range of applications and their different requirements.

    What can we do with Figure 3 to optimize AFE performance? Everything and not much. Until we define what we are going to sense and until we really understand the end application, we cannot optimize this basic design for a specific application. The operational amplifier (op amp) before the analog-to-digital converter (ADC) suggests many possible functions, including gain, impedance conversion, electrostatic discharge (ESD) protection, filtering for Nyquist, and protection from radio frequencies (RF).

    For example, we need to anticipate the majority of ESD, electromagnetic interference (EMI), and radio frequency interference (RFI) vulnerabilities in the application.

    Reply
44. July 9, 2015 at 5:52 am

    Tomi Engdahl says:

    John Markoff / New York Times:
    IBM has developed the first 7nm chips with four times the capacity of today’s most powerful chips

    IBM Announces Computer Chips More Powerful Than Any in Existence
    http://www.nytimes.com/2015/07/09/technology/ibm-announces-computer-chips-more-powerful-than-any-in-existence.html?_r=0

    IBM said on Thursday that it had made working versions of ultradense computer chips, with roughly four times the capacity of today’s most powerful chips.

    The announcement, made on behalf of an international consortium led by IBM, the giant computer company, is part of an effort to manufacture the most advanced computer chips in New York’s Hudson Valley, where IBM is investing $3 billion in a private-public partnership with New York State, GlobalFoundries, Samsung and equipment vendors.

    Intel, which for decades has been the industry leader, has faced technical challenges in recent years. Moreover, technologists have begun to question whether the longstanding pace of chip improvement, known as Moore’s Law, would continue past the current 14-nanometer generation of chips.

    Each generation brings roughly a 50 percent reduction in the area required by a given amount of circuitry. IBM’s new chips, though still in a research phase, suggest that semiconductor technology will continue to shrink at least through 2018.

    The company said on Thursday that it had working samples of chips with seven-nanometer transistors. It made the research advance by using silicon-germanium instead of pure silicon in key regions of the molecular-size switches.

    The new material makes possible faster transistor switching and lower power requirements. The tiny size of these transistors suggests that further advances will require new materials and new manufacturing techniques.

    As points of comparison to the size of the seven-nanometer transistors, a strand of DNA is about 2.5 nanometers in diameter and a red blood cell is roughly 7,500 nanometers in diameter. IBM said that would make it possible to build microprocessors with more than 20 billion transistors.

    The semiconductor industry must now decide if IBM’s bet on silicon-germanium is the best way forward.

    It must also grapple with the shift to using extreme ultraviolet, or EUV, light to etch patterns on chips at a resolution that approaches the diameter of individual atoms. In the past, Intel said it could see its way toward seven-nanometer manufacturing. But it has not said when that generation of chip making might arrive.

    IBM also declined to speculate on when it might begin commercial manufacturing of this technology generation. This year, Taiwan Semiconductor Manufacturing Company said that it planned to begin pilot product of seven-nanometer chips in 2017. Unlike IBM, however, it has not demonstrated working chips to meet that goal.

    It is uncertain whether the longer exposure times required by the new generation of EUV photolithographic stepper machines would make high-speed manufacturing operations impossible.

    An IBM official said that the consortium now sees a way to use EUV light in commercial manufacturing operations.

    Reply
45. July 9, 2015 at 6:27 am

    Tomi Engdahl says:

    IBM says it’s cracked the 7nm process barrier – take that, Moore’s Law
    Big Blue: Just don’t ask when our 7nm chips will go on sale. They don’t exist (yet)
    http://www.theregister.co.uk/2015/07/09/ibm_cracks_7nm_barrier/

    IBM reckons the megabucks R&D investment in next-gen chip technology it announced a year ago is already paying off, having apparently reached a major milestone in its efforts to shrink transistor gates far below today’s proportions.

    On Thursday, Big Blue will announce that it has successfully produced test chips with functional transistors using a 7nm (nanometer) process technology, and claim an industry first.

    Generally speaking, the smaller you can shrink the transistor gates on a chip, the more efficient the chip will be.

    Today’s best chips are fabbed using process technologies at scales of 22nm or 14nm. Moore’s law suggests the number of transistors on dense integrated circuits tends to double every couple of years, so 10nm and 7nm processes are expected to be the next natural rungs in the ladder.

    But while the industry’s current chippery techniques have got us to 14nm, going down to 7nm is another matter. At that scale, it gets extremely difficult to control the electrons flowing through the transistors. And the next step – getting beyond 7nm – is going to be even more challenging.

    As IBM explained in an email to The Register: “Pursuing such small dimensions through conventional processes has degraded chip performance and negated the expected benefits of scaling – higher performance, less cost and lower power requirements.”

    That’s why, 12 months ago, IBM announced that it would invest $3bn over five years to develop new chipmaking technologies that have a shot of breaking the 7nm barrier.

    Working with partners GlobalFoundries, Samsung, and State University of New York’s SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering, IBM now says it is getting closer to achieving such a breakthrough.

    They then managed to develop new process technologies that allowed them to stack the fins of their FinFET transistors closer together, so they’re stacked at a pitch of less than 30nm. By comparison, the fins on Intel’s 14nm “Broadwell” process are stacked at a 42nm pitch.

    Finally, they managed to use multiple levels of extreme ultraviolet (EUV) lithography to achieve area scaling that IBM says is nearly 50 per cent better than today’s most advanced 10nm process technology – which hasn’t even made it to market yet.

    “These efforts could result in at least a 50 per cent power/performance improvement for the next generation of systems that will power the Big Data, cloud and mobile era,” IBM said – which of course it would.

    That’s still some way off; industry observers suggest we won’t see commercial 7nm parts hit the market until 2020 at the earliest.

    What’s more, moving past 7nm to 5nm and beyond is going to be even harder than solving the 7nm problem. For one thing, SiGe channel material probably won’t do the job. IBM’s chip boffins will likely need to look to other materials, such as gallium-arsenide or carbon nanotubes, or to new techniques like silicon photonics, neurosynaptic computing, or quantum computing.

    Reply
46. July 9, 2015 at 6:28 am

    Tomi Engdahl says:

    Intel’s tablet CPU share to DROP: analyst
    Chipzilla will struggle to sell 50 million CPUs into mobile devices says Digitimes
    http://www.theregister.co.uk/2015/07/09/intels_tablet_cpu_share_to_drop_analyst/

    Researchers at Taiwan’s Digitimes have bad news for Intel: it just isn’t going to sell many chips for mobile devices.

    Intel’s thrown a lot of time, money and effort at mobile devices, but its efforts have resulted in red ink, a re-org to combine mobile and desktop products, and rumours of imminent layoffs.

    Digitimes now says that 2015 will see just 10.8 million Intel-powered Android tablets reach punters, “down from 14.23 million shipped a year earlier.” There’s some growth for Chipzilla in Android handsets, more than 10 million of which are expected to have Intel inside this year.

    Both figures are, however, drops in the Great Gadget Ocean. IDC reckons the world will make about 230 million tablets and phablets this year, plus another 1.447 billion smartphones. If Digitimes is right, Intel’s going to win slivers of those markets. And nasty thin slivers at that.

    There’s some solace in growing demand for two-in-one typoslabs that blend a PC and tablet, which Digitimes thinks will kick Intel’s overall mobile CPU sales up to 46 million a year.

    No wonder the company’s mobile division is bleeding: Intel’s experiencing a famine amidst a feast of mobile device sales and things don’t look like turning around despite its best engineering and ecosystem-building efforts.

    Reply
47. July 9, 2015 at 9:49 am

    Tomi Engdahl says:

    German-Estonian Skeleton Technologies has launched a super-or, as it calls it, ultra-capacitor family of products whose energy density company boasts of the best in the market. The patented grafene material using SkelCap 4500 family capacitance capacitors reach 4500 farad.

    Currently SC4500-capacitors nearest competitor reaches 3400 farad.

    Energy density is a key feature of supercapacitors if you want to eventually replace the batteries of energy saving. SkelCap-energy density supercapacitors opens the way for heavy-duty vehicles and industrial applications.

    Graphene has been known to be a promising material for energy storage

    Skeleton supercapacitors have already been selected for the European Space Agency’s future projects

    Skeleton is in their products reach the ESF to read the resistance value of 0.095 micro-ohms, which is the lowest in the sector.

    Skeleton has set itself the objective to develop a 20 watt-hours per kilogram-storing supercapacitor by 2020.

    Source: http://etn.fi/index.php?option=com_content&view=article&id=3061:maailman-energiatihein-superkondensaattori&catid=13&Itemid=101

    Reply
48. July 9, 2015 at 9:54 am

    Tomi Engdahl says:

    The development of the semiconductor industry continues to define the major categories, such as microprocessors and memories. From time to time the market will be new product categories, which span the fast growth of high-end. Micro Electro Mechanical components, namely MEMS circuits are now such a sector.

    Last year, the MEMS chips were sold to Semico Research, 14.3 billion dollars. Component deliveries increased by 36.6 percent in terms of units, which in practice means nearly 17 billion sold MEMS circuit. A large part of the increase is explained by the fact that smartphones are sold constantly growing variety of MEMS-based sensor solutions.

    By 2018, MEMS components, the annual sales volume is already growing to 43.3 billion units.

    Biggest MEMS manufacturer is currently Sensortech Bosch, whose turnover last year exceeded $ 1.2 billion. The second largest is still STMicroelectronic

    At the moment, the success of the MEMS market is divided into three camps, depending on the application areas the company plays. At the ends of printer sales are shrinking steadily. Car Electronics sales remain quite the same level. The fastest growth will enjoy a variety of motion sensors for smartphones and other mobile devices to develop. For example, the growth of Bosch’s sales last year, largely based on the design victory to Apple’s new iPhone 6 models.

    Source: http://etn.fi/index.php?option=com_content&view=article&id=3064:mems-vetaa-vauhdilla&catid=13&Itemid=101

    Reply
49. July 10, 2015 at 6:13 am

    Tomi Engdahl says:

    Sebastian Anthony / Ars Technica UK:
    IBM unveils world’s first functional 7nm test chip, targets 50% power/performance improvement from 10nm chips — Beyond silicon: IBM unveils world’s first 7nm chip — With a silicon-germanium channel, and EUV lithography, IBM crosses the 10nm barrier.

    Beyond silicon: IBM unveils world’s first 7nm chip
    With a silicon-germanium channel, and EUV lithography, IBM crosses the 10nm barrier.
    http://arstechnica.co.uk/gadgets/2015/07/ibm-unveils-industrys-first-7nm-chip-moving-beyond-silicon/

    IBM, working with GlobalFoundries, Samsung, SUNY, and various equipment suppliers, has produced the world’s first 7nm chip with functional transistors. While it should be stressed that commercial 7nm chips remain at least two years away, this test chip from IBM and its partners is extremely significant for three reasons: it’s a working sub-10nm chip (this is pretty significant in itself); it’s the first commercially viable sub-10nm FinFET logic chip that uses silicon-germanium as the channel material; and it appears to be the first commercially viable design produced with extreme ultraviolet (EUV) lithography.

    First, the facts and figures. This is a 7nm test chip, built at the IBM/SUNY (State University of New York) Polytechnic 300mm research facility in Albany, NY. The transistors are of the FinFET variety, with one significant difference over commercialised FinFETs: the channel of the transistor is a silicon-germanium (SiGe) alloy, rather than just silicon. To reach such tiny geometries, self-aligned quadruple patterning (SAQR) and EUV lithography is used.

    Somewhat extraordinarily, due to incredibly tight stacking (30nm transistor pitch), IBM claims a surface area reduction of “close to 50 percent” over today’s 10nm processes. All told, IBM and its partners are targeting “at least a 50 percent power/performance improvement for the next generation of systems”—that is, moving from 10nm down to 7nm. The difference over 14nm, which is the current state of the art for commercially shipping products, will be even more pronounced.

    Reply
50. July 10, 2015 at 6:15 am

    Tomi Engdahl says:

    IBM demos first fully integrated monolithic silicon photonics chip
    Electro-optical chips could bring big bandwidth gains and lower power consumption.
    http://arstechnica.co.uk/information-technology/2015/05/ibm-demos-first-fully-integrated-monolithic-silicon-photonics-chip/

    At a conference in the US, IBM has demonstrated what it claims to be the first fully integrated wavelength multiplexed silicon photonics chip. This is a big step towards commercial computer chips that support both electrical and optical circuits on the same chip package, and ultimately the same die. Optical interconnects and networks can offer much higher bandwidth than their copper counterparts, while consuming less energy—two factors that are rather beneficial as the Internet grows and centralised computing resources continue to swell.

    The first step is to bring optical channels onto the motherboard, then onto the chip package, and ultimately onto the die so that electrical and optical pathways run side-by-side at a nanometer scale.

    IBM’s latest nanophotonic chip belongs to the second category: it can be placed on the same package as an electronic chip, bringing the electro-optical conversion a lot closer to the logic. It’s important to note that the lasers themselves are still being produced off-chip, and brought into the nanophotonic chip through the “laser input ports” that you can see in the diagram above. Once the chip has been fed some lasers, there are four receive and transmit ports, each capable of transporting data at 25 gigabits per second, which are bundled up into 100Gbps channels via wavelength multiplexing.

    That’s just this chip, though; IBM says that, in theory, its technology could allow for chips with up to eight channels. 800Gbps from a single optical transceiver would be pretty impressive.

    Reply