Electronics trends for 2015

Chip designs that enable everything from a 6 Gbit/s smartphone interface to the world’s smallest SRAM cell will be described at the International Solid State Circuits Conference (ISSCC) in February 2015. Intel will describe a Xeon processor packing 5.56 billion transistors, and AMD will disclose an integrated processor sporting a new x86 core, according to a just-released preview of the event. The annual ISSCC covers the waterfront of chip designs that enable faster speeds, longer battery life, more performance, more memory, and interesting new capabilities. There will be many presentations on first designs made in 16 and 14 nm FinFET processes at IBM, Samsung, and TSMC.

There is push to go to even smaller processes, and it seems that next generation of lithography equipment are started to being used. Earlier expectation was for chipmakers to use traditional immersion lithography for production of 10 nm chip, but it seems that extreme ultraviolet (EUV) scanners that allows allow scaling to 10 nm or even smaller is being used. TSMC to Use EUV for 7nm, Says ASML. Intel and TSMC have been injecting money in ASML to push process technology.

2015 promises to see initial FPGA product releases and (no doubt) a deluge of marketing claims and counter-claims. One thing is certain: 2015 will not be boring. There will be FPGA products that use processes beyond 20nm, for example Altera and  Xilinx have committed to use the TSMC 16nm FinFET technology. There is  publicized (and rumored) race to get to production at 14nm has seen time frames for initial samples move into 2015. However, with both FPGA companies reporting gross margins of close to 70 percent, it would be possible for either company to take an initial hit on margin to gain key socket wins.

It seems that the hardware becomes hot again as Wearables make hardware the new software. Apple invest its time when it released the Apple Watch last quarter, going up against the likes of Google’s Android Wear and others in the burgeoning wearables area of design. Once Apple’s bitten into a market, it’s somewhat a given that there’s good growth ahead and that the market is, indeed, stable enough. As we turn to 2015 and beyond  wearables becomes an explosive hardware design opportunity — one that is closely tied to both consumer and healthcare markets. It could pick up steam in the way software did during the smartphone app explosion.

There will be more start-up activity within hardware sector. For recent years, the software has been on the main focus on the start-ups, and the hardware sector activity has been lower. Hardware sector has seem some start-up activity with many easy to use open hardware platforms became available (make development of complex devices easier and reachable for smaller companies). The group financing (Kickstarter, Indiegogo, etc.) have made it possible to test of new hardware ideas are market-worthy and get finance to get them to production.

EEs embrace hackathons aand accelerators. Design 2.0 is bubbling up in the engineering community, injecting new energy into the profession. In many ways, it’s the new Moore’s Law. Easy to use open hardware development platforms have made it possible to design working hardware device prototypes within hackathons.

Silicon Startups Get Incubator article tells that there will be new IC start-up activity as semiconductor veterans announced plans for an incubator dedicated to helping chip startups design their first prototypes. Keysight, Synopsys, and TSMC have signed exclusive deals to provide tools and services to the incubator. Silicon Catalyst aims to select its first batch of about 10 chip startups before April.

1,206 Comments

1. August 20, 2015 at 7:30 am

   Tomi Engdahl says:

   China Startup Offers Non-Volatile FPGAs
   http://www.eetimes.com/document.asp?doc_id=1327459&

   Gowin Semiconductor Corp. (Foshan, Guangdong, China), a startup formed and backed to produce FPGAs has announced the availability of a non-volatile family of devices.

   The family thus far comprises two FPGAs implemented in 55nm embedded flash process from TSMC; the GW1N-1K and the GW1N-9K with the corresponding approximate number of lookup tables per device.

   Gowin’s also provides the GW2A SRAM based family with complexity up to 50,000 look up tables and lists on its website the GW3S family covering complexity up to about 100,000 LUTs.

   Reply
2. August 20, 2015 at 7:36 am

   Tomi Engdahl says:

   Microcontroller Market Plagued by Price Erosion
   http://www.eetimes.com/document.asp?doc_id=1327470&

   Microcontroller shipments are growing tremendously as electronics companies roll out new products for the Internet of Things (IoT), but unprecedented price erosion means MCU vendors are seeing only a slight increase in sales, according to market research firm IC Insights.

   According to the latest update to IC Insights’ McClean report, microcontroller shipments are on pace to increase by a whopping $25.4 billion in 2015, thanks to a huge upsurge in units for smartcards and 32-bit applications, many of which are aimed at the IoT. But total revenue from microcontrollers is expected to grow by just 4% to a record $16.6 billion, according to the report.

   Rob Lineback, a senior market research analyst at IC Insights, said in an email exchange that microcontroller average selling prices (ASPs) are being driven down the most in the 32-bit segment, as suppliers battle each other and attempt to hit low price points needed for emerging IoT applications.

   “The pressure is on suppliers to dramatically lower ASPs on 32-bit for Internet of Things applications that need $3 to $4 total semiconductor cost for IoT connectivity functions and handling web-attached sensors,” Lineback said. “Wearables, wireless sensor nodes, and other embedded IoT functions are pushing down ASPs.”

   Reply
3. August 20, 2015 at 7:43 am

   Tomi Engdahl says:

   Electrical Overstress Detection and Debugging
   New Constraints Require New Techniques
   http://www.eetimes.com/author.asp?section_id=36&doc_id=1327453&

   Identifying and removing EOS susceptibility from integrated circuit (IC) designs is essential to ensuring successful performance and reliability when the products reach the market.

   Electrical overstress (EOS) is one of the leading causes of integrated circuit (IC) failures, regardless of where the chip is manufactured. EOS events can result in a wide spectrum of outcomes, from no damage, to degrees of performance degradation, up to catastrophic damage where the IC is permanently non-functional. Identifying and removing EOS susceptibility from integrated circuit (IC) designs is essential to ensuring successful performance and reliability when the products reach the market.

   EOS in its broadest definition includes electrostatic discharge (ESD) events. However, these two effects are generally differentiated, with EOS being more narrowly defined as the occurrence of overvoltage or overcurrent to a device.

   With these differences in mind, we’ll use EOS to describe the thermal damage that may occur when an electronic device is subjected to a current or voltage that is beyond the specification limits of the device. This thermal damage is the result of the excessive heat generated during the EOS event, which in turn is a result of resistive heating in the connections within the device. The high currents experienced during the EOS event can generate very localized high temperatures, even in the normally low resistance paths. These high temperatures cause destructive damage to the materials used in the device’s construction

   Reply
4. August 20, 2015 at 8:50 am

   Tomi Engdahl says:

   Protecting Your Electronic Product from Copying
   http://aa-pcbassembly.com/design-insights/protecting-your-electronic-product-from-copying/?utm_source=Promotion&utm_medium=Digital%20Magazine&utm_content=Protecting%20from%20Copying&utm_campaign=Aspen%20Core

   We have all heard about pirated copies of electronic products. One company started to notice a larger number of returns on a particular Internet router. Upon further investigation, it found the returns were a poor copy of its product but still they kept coming in; same box, same product and same literature. Even though the company took the blame from unsatisfied customers and initiated a serial number return policy, the damage to its reputation was done. The question is: how can a company protect itself from those who attempt to copy products?

   One strategy is to use available technologies to make a product hard to copy. Most pirates do not want to spend the money to redesign a product if it costs too much. They want to make quick money by doing an easy reverse engineering job and then make a few hundred thousand cheap knockoffs. By making it difficult to copy a design you can increase the thieves’ cost and reduce their potential to make money. Time is their enemy.

   The first step in slowing down the possible theft of your product, is to customize the printed circuit board (PCB). Most PCBs have green solder mask because, in the past, it was believed people did a better job assembling green boards. However, in today’s world of machine-placement, the circuit board color does not matter. Therefore, one easy trick to prevent fraud is to request a custom blended mask color. Solder mask companies make many different colors of solder mask, allowing you to create your own spectacular color by simply supplying the PCB manufacturer with the ink. It may cost a few cents more per board, but the vividly different color may slow down potential piracy.

   On the board assembly side, it may be possible to slow down pirates by adding a tamper-proof coating to both sides of the most important chip areas. A good tamper-proof coating will be dense enough to stop x-ray examination, i.e. contain tungsten carbide ceramic nano particles. It should also be hard enough to deter easily picking it away and be opaque enough to stop easy tracing of the PCB tracks.

   To add additional speed bumps to the pirates’ progress, further techniques can be used. For example, you can have a series of resistors and capacitors made that display the wrong value. These have been used on special protected government products where the resistor clearly was printed as a 10 ohm but actually was a 47 mega-ohm resistor, put across a couple of signal lines. While this may seem easy to get around, a pirate will have no idea that the number is intentionally incorrect.

   Many companies can make PCBs with embedded components such as resistors and even capacitors. There are companies who will either embed 0201 components inside the multilayer or put them in film resistors. Again, you may know they are inside but a pirate does not. If he cannot get the prototype to reverse engineer the board working, it may slow down the pirate enough to stop the attempt. HDI boards are very hard to reverse engineer due to their complexity and small size vias.

   The circuit boards had fake traces, hidden micro-sized wire bond wires over the chip and then tamper-proof coatings

   Reply
5. August 20, 2015 at 8:52 am

   Tomi Engdahl says:

   8 Cost Saving Steps for Your Next Design
   http://aa-pcbassembly.com/design-insights/8-cost-saving-steps-next-design/?utm_source=Promotion&utm_medium=eNewsletter&utm_content=Cost%20Saving%20Steps&utm_campaign=Aspen%20Labs

   Large or small, every company wants to decrease costs without affecting the quality of their products or services. There is rarely a perfect way to achieve this and PCB design and assembly is no exception. Accurately assembling PCBs is not an easy task; it takes experience, technology and, above all, dedicated people to ensure your projects are done right. When searching for a low-volume assembly shop to populate your boards, it may be tempting to use a low-cost shop to save money. However, doing so may end up costing more in the long term due to reliability concerns and lower throughput, which could result in a damaged reputation.

   1. Design within Standard Specifications
   2. Consider the Costs of Mixed Mount Technologies
   3. Panelize your Boards
   4. Minimize Overages
   5. Seek External Review
   6. Take Advantage of First Article Service
   7. Order in Volume
   8. Provide Helpful Information to the Manufacturer

   Conclusion

   It is possible to decrease costs without giving up quality. Instead of using cut-rate manufacturers and assembly houses, follow these low-to-no cost recommendations that will save you the money you need to make sure that your designs are produced to the highest quality possible. Never settle for less than the standards that you and your customers expect.

   Reply
6. August 20, 2015 at 12:20 pm

   Tomi Engdahl says:

   7 Steps to a Successful Analog ASIC
   http://www.edn.com/design/analog/4440174/7-Steps-to-a-Successful-Analog-ASIC?_mc=NL_EDN_EDT_EDN_analog_20150820&cid=NL_EDN_EDT_EDN_analog_20150820&&elq=50c7956843dc4f64a2989c292257fb22&elqCampaignId=24455&elqaid=27634&elqat=1&elqTrackId=d67813a59711427195894afc6cce6927

   I’m willing to bet that there are tens of thousands of analog applications out there that would benefit financially from ASIC integration. So what’s the holdup? Based on my 40+ years in the Analog IC business, I can boil it down to one word. Misinformation. This is a combination of a lack of information, incorrect information, and of course, FUD (Fear, Uncertainty and Doubt). Misinformation comes from numerous unreliable sources. It’s time to dispel the myths that often surround incorrect decision making and expose the bare bones truth about Analog ASIC integration; Most of the time, it’s the sensible thing to do, but confusion about all the preparatory steps you must take leading up to getting a proposal for NRE and Tooling is often an early show stopper.

   Proper planning in anticipation of having an Analog ASIC developed and produced for your company is not to be taken lightly. There are five key elements you need to explore internally before engaging an Analog ASIC semiconductor company to design and produce a custom chip for you. Once you are comfortable with this internal analysis, then you can explore possible suppliers.

   Reply
7. August 20, 2015 at 12:20 pm

   Tomi Engdahl says:

   Prototyping methods
   http://www.edn.com/electronics-blogs/benchtalk/4440159/Prototyping-methods?_mc=NL_EDN_EDT_EDN_analog_20150820&cid=NL_EDN_EDT_EDN_analog_20150820&elq=50c7956843dc4f64a2989c292257fb22&elqCampaignId=24455&elqaid=27634&elqat=1&elqTrackId=11e4522ddad0406c92d5e85328a73ac8

   Reply
8. August 21, 2015 at 7:44 am

   Tomi Engdahl says:

   Pause Forecast for CMOS Image Sensor Market
   http://www.eetimes.com/document.asp?doc_id=1327468&

   LONDON — The strong annual growth rates of 18.9, 14.8 and 16.8 percent in 2014, 2015 and 2016, respectively, are due to increasing application diversity after a climb in the first half of the decade on the back of smartphone proliferation, the market analysis company said. Now similar resolutions and lower-resolution sensors are moving into automotive applications, machine vision, surveillance and sensors for Internet of Things, the firm argued.

   IC Insights gave no reason for the expected pause in sales growth in 2017 although this may represent an expected market reaction to a potential oversupply of sensors.

   In 2015 the CMOS image sensor market will climb 14.8 percent to reach a value of $10.1 billion, IC Insights reckons. CMOS image sensor unit shipments are now projected to grow 19 percent in 2015 to reach 3.7 billion units after rising 20 percent in 2014 and 2013.

   In 2014, about 70 percent of CMOS image sensor sales – about $6.2 billion – were for embedded cameras in mobile phones, but that percentage is expected to fall to 49 percent in 2019 or about $7.3 billion, which represents a compound annual growth rate (CAGR) of just 3.4 percent. In comparison, total CMOS image sensor sales are projected to grow by a CAGR of 11.1 percent in the five-year forecast period to reach $15.0 billion in 2019.

   During the same period sales of CMOS image sensors for automotive safety systems will climb at a CAGR of 57.4 percent to $2.1 billion in 2019 by which time they will represent 14 percent of the market’s total dollar volume that year compared to just 3 percent in 2014.

   CMOS image sensor sales for security systems and surveillance applications are expected to grow by a CAGR of 38.4 percent in the five-year forecast period to $899 million in 2019, which will represent 6 percent of the market’s total sales that year versus 2 percent in 2014. Medical and scientific imaging applications of CMOS image sensors are expected to enjoy a CAGR of 36.0 percent to $824 million in 2019 or about 6 percent of the total market compared to about 2 percent in 2014.

   Toys and video game applications are expected to increase sales of CMOS image sensors by a CAGR of 32.7 percent to $255 million by 2019, which will represent 2 percent of the market’s total revenue compared to 1 percent in 2014.

   Sony, the leading CMOS image sensor supplier, is now aiming at confirming a leading position in the automotive image sensor market just as it has done in the mobile phone market.

   Reply
9. August 21, 2015 at 9:02 am

   Tomi Engdahl says:

   Antenna violations resolved using new method
   http://www.edn.com/design/integrated-circuit-design/4440143/Antenna-violations-resolved-using-new-method?_mc=NL_EDN_EDT_EDN_weekly_20150820&cid=NL_EDN_EDT_EDN_weekly_20150820&elq=5f53db4ce5b84888a7f42133b14a1d32&elqCampaignId=24462&elqaid=27641&elqat=1&elqTrackId=f2134f52bafd4b4bb785902a73373244

   Antenna rules are used in SoC design to check for excessive accumulation of charge on metal during fabrication. One of the ways to remove these antenna violations is by using metal jumpers. In higher technology nodes the number of antenna violations that occur are huge as compared to lower technologies, and resolving them with jumpers using the traditional technique is excessively time consuming and at the same time ineffective. In this paper, we propose an effective, faster, and non-iterative way to resolve the different types of antenna violations that occur in higher-technology nodes using metal jumpers.

   During IC fabrication, the wafer usually undergoes various processing steps, one of them being etching (to make the surface flat). A typical net in an integrated circuit has a driver (source or drain) which is then connected to a receiver gate electrode over a thin gate dielectric. The modern wafer processing uses plasma etching techniques which apart from its various benefits over wet etching techniques also has a lot of unwanted results like accumulation of charges. Now the gate dielectric is so thin that there is always the danger of it getting damaged due to potentials higher than its breakdown potential. This phenomenon is known as antenna effect and the FAB has its own set of rules (which differs with technology node) to avoid such antenna violations while designing the integrated circuit.

   In lower technologies, the dielectric used has a high dielectric coefficient and hence the antenna rules are not that stringent. But the antenna rules are more difficult to meet in higher technologies, hence 130nm and above technologies are more antenna prone.

   Reply
10. August 24, 2015 at 7:39 am

    Tomi Engdahl says:

    SK Hynix Invests in Hyperspectral Sensor Startup
    http://www.eetimes.com/document.asp?doc_id=1327491&

    SK Hynix has invested 2.2 billion won (about $1.8 million) in Stratio Technology Inc. (Menlo Park, Calif.), a startup developing germanium-based hyperspectral image sensors, according to Korea Times article. SK Hynix has acquired a 9.1 percent stake the article said.

    Stratio was founded in 2013 by four PhD graduates from Stanford University. The core technology is a germanium-based sensor that utilizes a proprietary hybrid process that combines selective germanium epitaxial growth with established silicon CMOS technology to overcome the limitations and costs of conventional InGaAs-based short wavelength infrared (SWIR) sensors.

    Hyperspectral imaging is expected to have applications in food processing, automotive and industrial vision and sorting, construction and medical applications, such as providing diabetic sufferers with bloodless glucose monitoring

    Reply
11. August 24, 2015 at 7:42 am

    Tomi Engdahl says:

    Smart-Meter ICs on Rise, Predicts Report
    http://www.eetimes.com/document.asp?doc_id=1327494&

    The global market for smart meters is going to be 132 million units in 2015 rising to 150 million units in 2019 — i.e., a compound annual growth rate of 3.2% — providing significant growth opportunities for ICs, according to research firm IHS,

    Global revenues for semiconductors used in water, gas and electric meters reached $1.2 billion in 2014, with a year-over-year growth of 11% and a five-year compound annual growth rate of 8%, the market research firm claims. The average cost of chips used in two-way meters was approximately $11 in 2014, IHS estimates. About two thirds of that semiconductor revenue comes from microcontroller and analog components, said IHS.

    Unusually, even though volumes and competition will increase over time, average selling prices (ASPs) are expected to increase rather than fall. This is because the industry will be transitioning from low-cost 8-bit microcontrollers to more expensive 32-bit MCUs with additional memory requirements and system-on-chip components with increased security.

    “The semiconductor industry for electric meters is moving toward a single-chip solution for measuring and communicating with the grid station, which is an important industry trend to watch,”

    Reply
12. August 24, 2015 at 8:11 am

    Tomi Engdahl says:

    All of NIWeek 2015 can be reduced to one diagram
    http://www.edn.com/electronics-blogs/test-cafe/4440104/All-of-NIWeek-2015-can-be-reduced-to-one-diagram?_mc=NL_EDN_EDT_EDN_funfriday_20150821&cid=NL_EDN_EDT_EDN_funfriday_20150821&elq=2b21cf85ccb240b0ac39262799afd09a&elqCampaignId=24480&elqaid=27657&elqat=1&elqTrackId=9ba706fa076242da9c714540db54132a

    NIWeek is National Instruments’ annual conference held every August in Austin, Texas, attracting some 3200 attendees.

    NIWeek is always a revealing conference as NI unveils new products and applications.

    However, the 5G system was just one of a wide diversity of new applications and technologies shown at the conference. If I had to reduce NIWeek this year to just a single diagram, it would be this:

    The LabView RIO architecture positions fast, flexible FPGAs towards the measurement edge. LabView is used by the users to generate code for the processors and FPGAs from the same development environment.

    Admittedly, saying all of NIWeek can be reduced to the above LabView RIO (reconfigurable I/O) diagram is a bit of hyperbole. But just a bit. NI’s major announcements orbited around this diagram, as does much of their partner strategy.

    Reply
13. August 24, 2015 at 8:18 am

    Tomi Engdahl says:

    New Opportunities in the $2.2 Billion Conductive Ink Market
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1327495&

    Conductive inks and pastes remain one of the largest and most dynamic sectors in printed electronics.

    Conductive inks and pastes remain one of the largest sectors in the greater printed electronics market, generating $2.2 billion in 2015. IDTechEx Research forecasts this market to grow to $3 billion in 2025

    Fresh enthusiasm for silver nanoparticles
    The market for silver nanoparticles remains small, but the mood is changing. Larger companies have entered the scene, helping change a landscape that was previously in exclusive possession of small players. Some firms have exited the stage, but most have been replaced with fresh stock.

    Silver nanoparticles set out to offer more performance for less cost compared to traditional pastes, but they turned out initially to be “less for more.” There is now, however, a sense that they finally offer “more for same.”

    Growth is back in the PV sector, but so is animosity
    The photovoltaic (PV) market has traditionally dominated the conductive paste market. Here, firing-type silver pastes are screen-printed atop billions of photovoltaic silicon wafers. The PV market experienced a drastic consolidation period between 2007 and 2014, causing the paste market to dip and also to consolidate. Growth is, however, now back in the underlying PV sector, causing volume demand to grow despite the gradual annual decline in silver content per wafer. The previous big boys dominated sales although there is now renewed friction on the top with heightened risk of IP battles.

    Copper to penetrate the touch screen markets
    The touch screen market is growing even though the uptake of large-sized touch has largely disappointed. Here, low-temperature silver paste is screen-printed as the edge electrodes. A big trend is towards narrowing the bezel even more, reducing the linewidth-to-spacing (L/S) ratio of edge (bezel) electrodes. This trend will ultimately push screen printing beyond its limits in the long term and will open the door for other printing methods.

    Wearable Electronics: Wearable electronics are now trending, so this topic is on all suppliers’ agendas, including those who supply conductive inks. Many detect an opportunity in creating speciality inks that can be washed and stretched. The idea is that the printed inks can act either as interconnect or as piezo resistive sensors on textiles.

    Antennas and Printed Circuit Boards: Using printing to rapidly prototype PCBs is being given a second chance. This time the market is emerging at two extreme ends: the hobbyist and the professional. In the former, small and simple machines create crude and simple (single-sided and — more rarely — double-sided) circuits with low conductivity and wide tracks (e.g., 500um). These machine makers raise money using crowd funding and price their products at the low end. This trend will soon fizzle out because the incumbent — a low priced CNC machine — offers much more for less, so the chances are that the substitute will not succeed. The consumable costs for printing will be a further handicap as will be their inability to cost-effectively create a continuous ground plane.

    The professional end is a different story. Here, complex inkjet printing systems are being engineered that can deposit alternating layers of silver nanoparticle and insulting inks, thereby creating multi-layer PCBs with narrow tracks compatible with most SMDs. The target market here is rapid prototyping or low volume manufacture of boards with four layers or higher (etching PCBs gets more tricky with increasing layer numbers). This approach seeks to reduce prototyping turnaround time for multi-layer circuits while keeping all the circuit IP in house.

    Combining Printed Electronics and 3D Printing: Yet another trend is combining printed electronics and 3D printing. The idea is to weave electronics into 3D printed objects. Various approaches are being developed in parallel. Conductive filaments are improving, but they remain barely conductive, not even coming close to levels that enable useful circuits. Aerosol deposition is making good progress, but it is at its best for depositing on the final surface. Standard printed conductive inks have a high sintering temperature, often above the glass temperature of 3D plastic, while UV curing can have many side effects on polymer properties.

    Conductive inks and pastes remain one of the largest and most dynamic sectors in printed electronics. It is often perceived that this technology is “old hat,” but the industry keeps itself dynamic by offering new products and by finding new markets. The technology is not stale, even in the more mature sectors like PV

    Reply
14. August 24, 2015 at 9:29 am

    Tomi Engdahl says:

    New Advances in FPGA Security
    http://www.eetimes.com/document.asp?doc_id=1327477&

    As I mentioned in my Cyber Insecurity column a few days ago, any system is only as secure as its weakest link. In order to protect a system, we need a layered approach to secure:

    The Hardware: DPA resistance, NIST-certified crypto accelerators, a secure supply chain, etc.

    The Design: Bitstream (FPGAs), firmware (MCUs and SoC FPGAs), and application software, including tamper detection and protection against copying, cloning, and reverse engineering

    The Data: Key storage using physically unclonable function (PUFs), advanced crypto accelerators, DPA resistance, etc.

    There is a hierarchy to potential attacks, starting at the low-cost, low expertise high-school hacker protocol level (eavesdropping, main-in-the-middle, replay, relay, and other protocol-focused attacks), and ranging all the way to the high-cost, high-expertise semi-invasive and invasive (e.g., optical, electron microscope, focused ion beam (FIB)) and cryptographic attacks mounted by well-funded adversaries like nation states.

    Between these two extremes, we find insidious non-invasive side-channel attacks, including timing, simple power analysis (SPA), differential power analysis (DPA), and differential electromagnetic analysis (DEMA). Secrets such as cryptographic keys can “leak out” via these unintended side-channels.

    In the case of FPGAs, for example, if left unprotected, side-channel attacks can be used to extract secret keys by measuring power consumption during cryptographic operations like bitstream loading. A simple, readily available $400 setup can end up costing the owners and users of an unsecured system millions of dollars.

    But the bottom line is that it behooves the creators of electronic, computer, and embedded systems to make the security of these systems a top priority, and the folks at Microsemi are making this much easier for the rest of us.

    Reply
15. August 24, 2015 at 1:03 pm

    Tomi Engdahl says:

    Design rule checking for SERDES PCB layouts
    http://www.edn.com/design/pc-board/4440135/Design-rule-checking-for-SERDES-PCB-layouts?_mc=NL_EDN_EDT_pcbdesigncenter_20150824&cid=NL_EDN_EDT_pcbdesigncenter_20150824&elq=587eeb0fa33f4c4eafe6ef87245d7d43&elqCampaignId=24489&elqaid=27683&elqat=1&elqTrackId=6f2d4226a6304b91ab46c1333219fe75

    Despite running at much faster speeds than parallel interfaces, SERDES buses tend to be much easier to implement, as there is a specific set of problems to overcome. As long as the high-level architecture of the SERDES interface is sound, a successful implementation of a SERDES bus boils down to “implementation details.” Such details must usually be verified by manual inspection of the routed board, but an automated inspection methodology, like that facilitated through the use of design rule checking (DRC), can make the task of reviewing SERDES buses much easier. Here are examples where DRC can be useful

    Reply
16. August 24, 2015 at 1:06 pm

    Tomi Engdahl says:

    Getting the heat out of PCBs demands intelligent simulation
    http://www.edn.com/design/pc-board/4440112/Getting-the-heat-out-of-PCBs-demands-intelligent-simulation?_mc=NL_EDN_EDT_pcbdesigncenter_20150824&cid=NL_EDN_EDT_pcbdesigncenter_20150824&elq=587eeb0fa33f4c4eafe6ef87245d7d43&elqCampaignId=24489&elqaid=27683&elqat=1&elqTrackId=0686be701ecb4cfabfffaf10b56e64d0

    The drive for miniaturization means that more heat is being generated in very restricted spaces inside electronic and electrical equipment. Accurate thermal simulation of system behaviour can accelerate the design of products that perform better, are smaller, and prove to be more reliable.

    Until recently, thermal simulation of PCB assemblies was relatively crude, using approximations of questionable accuracy to predict real-world thermal performance. That’s beginning to change. Here, we examine the key issues around the thermal design of PCBs, and how some of the latest simulation tools are making good thermal design easy to achieve.

    Like any aspect of design, creating the optimal printed circuit board (PCB) involves trade-offs.

    In addition, you need to consider the issue of thermal design – something that becomes ever more critical with product miniaturization. The heat generated by active components often has few places to go, and the build-up of this heat has implications for product performance, reliability, size, and cost.

    To complicate things further, the best PCB layout for electrical performance is usually the worst for thermal performance. A wide swath of copper can be great for conductivity, as it can minimize the heating effect of currents passing through it. However, it also creates unwanted capacitive coupling with conductors on other layers of the board, and it takes up too much space at a time when board layouts are becoming ever more complex and dense.

    Here are just a few of the unwanted effects of elevated temperatures on circuit components:

    Class III (Z5U) ceramic capacitors, used for coupling and decoupling, can lose as much as 56% of their capacitance before they reach their operating limit of 85°C ambient.
    Tantalum and aluminum electrolytic capacitors have to be derated as temperatures rise, and high temperatures dramatically affect reliability. A rule of thumb for aluminum electrolytic capacitors is that the Mean Time Between Failures (MTBF) is halved for every 10°C rise in temperature above 20°C.
    The maximum operating voltage of capacitors declines with temperature. High temperatures may lead to a requirement for capacitors with a higher nominal operating voltage, making these components larger and more expensive.
    High temperatures can change the characteristics of semiconductor devices. For example, some power rectifiers do not operate correctly above 75°C.
    Quartz crystals shift frequency with temperature. The most popular type, AT-cut crystals, have an inflection point of 25°C. Low-cost crystals may shift frequency by 50 ppm at 85°C. You can specify more stable parts, but costs increase significantly.
    Temperature affects the power output of batteries, and some types (Li-Ion included) are prone to catastrophic failure if they overheat.

    Factors to consider in designing PCBs for good thermal characteristics

    Component placement should be the first consideration. Within the given electrical and mechanical constraints, try not to bunch heat-generating components together as this will create hotspots. Wherever possible, place them near ventilation outlets in packaging, or in places where they are less likely to impede convection of air across the surface of the PCB.

    Component temperature limits need to be determined.

    Improved simulation techniques for understanding heat transfer through a PCB

    To be most effective, thermal simulation should be done at an early stage in PCB layout design. It can be too late, or too expensive, to redesign boards when thermal management issues are discovered.

    A PCB is a complex part, with many layers and hundreds of traces, holes, and vias. This is a challenge for thermal simulation, as small objects can lead to impractically long processing times for a simulation tool’s mathematical solvers. So, the goal is to reduce the complexity of PCB traces without reducing simulation accuracy.

    Reply
17. August 24, 2015 at 1:07 pm

    Tomi Engdahl says:

    How to verify control loop design
    http://www.edn.com/design/pc-board/4423589/How-to-verify-control-loop-design

    The non-invasive stability assessment is a method that uses an output impedance measurement to accurately determine stability without access to the control loop. The non-invasive stability assessment, whether performed as a physical test or with a circuit simulation, is a fast, simple, and inexpensive means to verify or optimize any control loop design. This measurement is useful in almost all systems, though especially in high-speed, instrumentation, and RF systems. Improving stability reduces noise in a system, allowing better SNR, dynamic range, clock jitter and many other performance characteristics to be enhanced. Issues related to noise can be very difficult to trace and fix. Non-invasive testing is sometimes the only way to single out and eliminate potential stability problems.

    #1: Sometime Bode Plots Aren’t a Choice
    #2: The non-invasive stability test is an exact solution for second-order systems including the capacitor ESR.

    Reply
18. August 24, 2015 at 4:07 pm

    Tomi Engdahl says:

    Direct-AC LED modules feature universal input, high reliability
    http://www.edn.com/electronics-blogs/led-zone/4440173/Direct-AC-LED-modules-feature-universal-input–high-reliability

    LUXTECH’s recently introduced platform for Universal Input integrated Direct-AC LED modules provides another proof point for the old maxim “good things come in small packages.”

    combines the LEDS, a thermal interface, and a compact power supply/driver circuit, capable of operating from any AC power source ranging from 120 to 277V at 50 or 60Hz.

    So what’s so revolutionary about LUXTECH’s direct LED driver? Let’s begin with the fact that it eliminates the switch-mode power supplies and constant current LED drivers found in virtually all of today’s LED lighting products.

    Instead, LUXTECH uses an inductor-less voltage-based converter/driver circuit. Besides the reduced component count of the driver itself, LUXTECH’s modules also eliminate the need for EMI filtering or power factor correction circuitry.

    There are a few other companies, such as Seoul Semiconductor, which offer direct-drive LED products, but they use conversion architectures which are much less efficient and can only run the LEDs at a much smaller fraction of their rated output (typically 50%-60%). This is because the output pulses created by their “chopper-style” drivers must be sharply limited to prevent the peak current they deliver to the LEDs from exceeding the levels defined by the LM80 lifetime standard.

    LUXTECH says that, in a typical application, their modules are able to safely drive LEDs to 80% of their maximum rated output while maintaining 80% overall efficiency.

    The direct drive platform has been proven in applications with power requirements ranging from 5W to 100W, with higher-power variants planned for the near future.

    Reply
19. August 25, 2015 at 6:36 am

    Tomi Engdahl says:

    MRAM Hits Flash Arrays in M.2 Module
    http://www.eetimes.com/document.asp?doc_id=1327500&

    Everspin Technologies Inc. (Chandler, Ariz.) built its business as a magnetoresistive RAM (MRAM) company through industrial and automotive applications, but it’s always been looking at broader applications for both its MRAM and Spin-Torque MRAM (ST-MRAM), particularly for applications that require data persistence and integrity, low latency, and security.

    Now its MRAM has found its way into the M.2 form factor as part of Aupera Technologies’ (Vancouver, BC) All Flash Array. The AupM001 is an M.2 MRAM module designed with Everspin’s EMD3D064M ST-MRAM. Its initial capacity is 32 MB, with higher capacities becoming available soon, said Everspin president and CEO Phill LoPresti in a telephone interview with EE Times. “We feel this is right in the sweet spot we targeted the products for when we started development.”

    Aupera’s All Flash Array is equipped with Everspin’s, 64 Mb DDR3 ST-MRAM devices and a PCIe backhaul interface, he said, and this is the first time the M.2 form factor has been used to house MRAM.

    Reply
20. August 25, 2015 at 6:56 am

    Tomi Engdahl says:

    Qualcomm Beefs up its DSP
    Wide, fast Hexagon 680 serves many purposes
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1327507&

    The Hexagon 680 provides an expanded suite of digital signal processing capabilities Qualcomm will apply to multiple jobs in its Snapdragon 820 mobile SoC.

    Qualcomm has been the leader in building truly heterogeneous SoCs, which include a 64-bit CPU, a powerful GPU, dual ISPs, and a few DSPs, which Qualcomm brands as Hexagon. Other SoC builders have DSPs in their chip, but use them primarily for audio or modem functions. Qualcomm does that too, and also dedicates one to video and image processing.

    What’s new in the Snapdragon 820 is the extended Hexagon DSP, which Qualcomm has designated the 680.

    Reply
21. August 25, 2015 at 7:01 am

    Tomi Engdahl says:

    Cable Runs Affect MEMS Microphone Tests
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1327411&

    The explosion of smart devices has meant an explosion of small, low-powered audio components that bring their own special measurement and connectivity challenges.

    Virtually all smartphones, tablets, and wearables incorporate multiple MEMS (micro-electro-mechanical system) microphones both for capturing sound and implementing noise-cancellation features. These small, surface-mounted components are cost effective and provide remarkably good performance. While many MEMS microphones produce only analog signals, a new generation of digital microphones is rapidly overtaking the market. These tiny devices incorporate very simple, low-power analog-to-digital convertors (ADCs) that produce PDM (pulse density modulation) data streams.

    PDM is a 1-bit data technology that employs oversampling in order to match the performance of traditional PCM (pulse-code modulation) audio. By greatly oversampling the analog signal (most commonly by a factor of 64, but with a wide range of possible values) the bandwidth of the system is increased, and the inherent noise of a 1-bit system is pushed beyond audibility, where it is easily filtered.

    In order to match the performance of a PCM audio system with a 48kHz sample rate, digital MEMS microphones commonly employ a sample rate of 48 kHz x 64 = 3.072 MHz. This high-frequency behavior creates some issues for test and measurement.

    Because the microphones are generally mounted in close proximity to destination components in the finished product, signal loss due to capacitive effects are minimal, but the situation changes for the worse when testing MEMS microphones in a lab setting. Even bench cable runs of less than 3 ft (1 m) can present problems.

    Reply
22. August 25, 2015 at 7:02 am

    Tomi Engdahl says:

    Inside GlobalFoundries’ Fab 8
    Giant fab rides emerging NY tech corridor
    http://www.eetimes.com/document.asp?doc_id=1327435&

    GlobalFoundries’ Fab 8, one of the largest semiconductor fabs in the United States, sits on 233 acres of the Luther Forest tech campus in Malta, N.Y. A tour of the plant and an affiliated research center in nearby Albany provided a look inside an operation that now carries the DNA of chip giants such as AMD, IBM and Samsung.

    The Malta facility stands at the bleeding edge of the company’s nine fabs worldwide. It now produces 14nm chips while working on 10nm processes and beyond and leads the company’s manufacturing initiatives.

    Reply
23. August 25, 2015 at 7:53 am

    Tomi Engdahl says:

    China wants to take control of the programmable circuits

    China’s education system to produce as vast amounts of engineers and designers, that it ultimately is reflected in all areas of electronics. The composition and the manufacturing goes definitely planning more demanding circuits. Gowin Semiconductor is a good example.

    Gowin has launched the first field programmable matrix circuit. This is all the more interesting that the FPGA circuits is not new entrepreneurs very often. The market is beer bought by Americans Xilinx and Intel held a cross from Altera.

    Gowin, however, attempt to challenge the old gamblers. Its founders have a background Lattice Semiconductor, which is also known as the FPGA manufacturer. Gowin first tried to SRAM-based chips, but they have conquered the world.

    The new circuit family is more interesting, because it is based on non-volatile flash memory. A process is TSMC’s 55-nanometer process.

    Source: http://etn.fi/index.php?option=com_content&view=article&id=3220:kiina-haluaa-vallata-myos-ohjelmoitavat-piirit&catid=13&Itemid=101

    Reply
24. August 25, 2015 at 7:54 am

    Tomi Engdahl says:

    DRAM manufacturing is beginning to be fully Koreans held. DRAMExchangen recent statistics show that the combined market share of Samsung and Hynix already increased by 81.5 per cent in the second quarter. This was the first time in DRAMs history.

    Source: http://etn.fi/index.php?option=com_content&view=article&id=3219:dram-taysin-korealaisten-hallussa&catid=13&Itemid=101

    Reply
25. August 25, 2015 at 8:10 am

    Tomi Engdahl says:

    Two-pin EEPROM is parasitically powered
    http://www.edn.com/electronics-products/other/4440175/Two-pin-EEPROM-is-parasitically-powered?_mc=NL_EDN_EDT_EDN_productsandtools_20150824&cid=NL_EDN_EDT_EDN_productsandtools_20150824&elq=7360f93c3be04491b33c2e4b90dad867&elqCampaignId=24504&elqaid=27698&elqat=1&elqTrackId=516e1af6f3a2480e945c2855a5701e30

    Atmel has launched the AT21CS01/11, a single-wire serial EEPROM that needs only a data pin and a ground pin for operation. The self-powered device eliminates the need for a power source or VCC pin by using a parasitic power scheme over the data pin. Organized as 128×8 bits, the 1-kbit memory offers a security register with a 64-bit factory-programmed serial number and an extra 16 bytes of user programmable and permanently lockable storage.

    These features make the AT21CS01/11 well-suited for IoT, wearables, consumable, battery, and cable identification markets.

    Reply
26. August 25, 2015 at 11:02 am

    Tomi Engdahl says:

    Erin Griffith / Fortune:
    Profile of PCH CEO Liam Casey, the supply chain expert of hardware manufacturing in China

    Meet the tech industry’s China fixer
    http://fortune.com/2015/08/24/pch-ceo-liam-casey-china/

    Need a flashy new gadget designed, manufactured, and sold? Liam Casey doesn’t just know a guy—he is the guy.

    His name isn’t well-known in elite business circles, but in the tech hardware scene, Liam Casey is “the guy.” He’s the one you call for a factory connection, the guy you hire for your packaging design, and the one you ask about FedEx FDX -4.91% negotiations. All you have to do is find him. Casey, the 49-year-old founder and CEO of PCH International, splits his time between Shenzhen, China, and San Francisco; he lives out of hotels and carries three phones set to different time zones.

    Casey is the guy because since 1996 he’s been facilitating hardware manufacturing for companies large and small in China, the world’s largest manufacturer of (and market for) electronics. The simplest way to explain PCH (named for California’s Pacific Coast Highway) is that it offers “end-to-end” services: from design to engineering, manufacturing to packaging, fulfillment to retail distribution. If you gave PCH a sketch on a napkin, the company could turn it into a product on a shelf—as it actually did recently with Drop, a connected kitchen scale. “Some people expect a ‘China button,’ ” Casey says. “But they’re looking for an end-to-end button.”

    With nine offices and 2,600 employees, PCH moves as many as 10 million products through the 2,000-plus factories in its network each day. Last year the company’s revenue reached $1.1 billion.

    PCH’s clients don’t want to broadcast the fact that they’re outsourcing their secret sauce

    The idea of hiring a fixer like Casey and PCH is alluring for big companies and startups alike that see the Chinese manufacturing industry as a black box packed with potential complication. We know electronics are made in China. We rarely wonder how.

    That’s an especially pressing concern for startups that don’t know their way around a supply chain. In recent years hardware startups have proliferated in Silicon Valley—Casey calls it a prototyping renaissance—fueled by online crowdfunding platforms that make it easy to take money and preorders, but provide little else.

    Consider the case of Pebble, which raised $10.2 million on Kickstarter for its smartwatch before realizing it didn’t have the infrastructure to deliver 85,000 of them. It took the startup (which isn’t a PCH client) more than a year to fill those orders, prompting a brutal online backlash.

    Casey has gotten used to hearing from founders in distress. Sometimes it’s because they’ve found out they designed a product that wasn’t engineered for manufacturing. Other times it’s after they realize they’ve signed one-sided contracts with big-box retailers.

    The calls came in so frequently that in 2013 Casey set up an accelerator program in San Francisco, called Highway1, designed to help hardware startups. The four-month program offers access to a prototyping lab, consultation with product and business experts, and a visit to Shenzhen.

    “We wanted them to have something that basically protected them from themselves,”

    “Shark Tank takes this pivotal time for a startup and condenses it to five to 10 minutes,” Forrest says. “We want to take a step back and show how the product is actually made and how we got to this point.”

    “We learn how to make the things that the big companies are going to want in two years,” Forrest says.

    Casey believes that’s one reason Xiaomi, the Chinese smartphone maker, carries a $45 billion valuation and Western hardware success stories like Fitbit and GoPro haven’t topped $10 billion. “They ask, ‘What’s the difference?’ It’s mostly in the supply chain.”

    Reply
27. August 25, 2015 at 2:06 pm

    Tomi Engdahl says:

    Se Young Lee / Reuters:NEW
    SK Hynix to spend $26 billion for two new South Korea chip plants — SK Hynix Inc, the world’s No. 2 DRAM chip maker, on Tuesday said it plans to spend 31 trillion won ($25.94 billion) to build two new chip plants in South Korea, aiming to update its production technologies to boost

    SK Hynix to spend $26 billion for two new South Korea chip plants
    http://www.reuters.com/article/2015/08/25/us-sk-hynix-investment-idUSKCN0QU06E20150825

    The firm, which competes with rivals including Samsung Electronics Co Ltd, Micron Technology Inc and Toshiba Corp, said the plants would be completed by 2024 but did not comment on what they would make or when they would begin production.

    The memory chip industry has enjoyed robust profits in recent quarters, in part due to careful capacity management by major manufacturers like Samsung and SK Hynix. Investors are closely watching new capital investment, as aggressive spending could trigger oversupply or a price war.

    “The memory chip industry is already firmly controlled by a handful of companies, so there’s no reason for any parties involved to start a game of chicken,” said HMC Investment analyst Greg Roh, adding that SK Hynix’s investments were in line with rivals like Samsung.

    Reply
28. August 25, 2015 at 9:16 pm

    Tomi Engdahl says:

    Two New FPGA Families, Designed in China
    http://hackaday.com/2015/08/24/two-new-fpga-families-designed-in-china/

    The two largest manufacturers of FPGAs are, by far, Altera and Xilinx. They control over 80% of the market share, with Lattice and others picking up the tail end. The impact of this can be seen in EE labs and alibaba; nearly every FPGA dev board, every instructional, and every bit of coursework is based on Altera or Xilinx chips.

    There’s a new contender from the east. Gowin Semiconductor has released two lines of FPGAs (Google translate) in just under two years. That’s incredibly fast for a company that appears to be gearing up to take on the Altera and Xilinx monolith.

    The FPGA line released last week, the GW1N family, is comprised of two devices with 1,152 and 8,640 LUTs. These FPGAs are built on a 55nm process, and are meant to compete with the low end of Altera’s and Xilinx’ offerings.

    For comparison, Xilinx’ Spartan-6 LX family begins with devices featuring 3,840 LUTs and 216kb of block RAM, with larger devices featuring 147,443 LUTs and up to 268kb of block RAM. Altera’s Cyclone IV E devices are similarly equipped, with devices ranging from 6,272 to 114,480 LUTs. Between the two device families introduced by Gowin recently, nearly the entire market of low-end FPGAs is covered, and they’re improving on the current offerings: the GW1N chips feature random access on-chip Flash memory. Neither the low-end devices from Altera nor devices from Lattice provide random-access Flash.

    The toolchain for Gowin’s new FPGAs is based nearly entirely on Synopsys’ Synplify Pro, with dedicated tools from Gowin for transforming HDL into a bitstream for the chip. This deal was inked last year.

    The GW1N and GW2A families of FPGAs are fairly small when it comes to the world of FPGAs. This limitation is by capability though, and not number of units shipped. It’s nearly tautological that the largest market for FPGAs would be consumer goods, and Gowin is focusing on what will sell well before digging in to higher end designs.

    Reply
29. August 25, 2015 at 9:27 pm

    Tomi Engdahl says:

    Could Solid-State Batteries Last a Lifetime?
    http://hackaday.com/2015/08/25/could-solid-state-batteries-last-a-lifetime/

    Researchers from MIT and the Samsung Advanced Institute of Technology have been developing a new material that could potentially revolutionize the battery industry. A solid electrolyte that won’t wear out, lasting exponentially longer than current battery chemistry.

    It also has the possibility to increase battery life, storage, and the safety of batteries — as liquid electrolytes are the main reason batteries catch on fire.

    Sound too good to be true? The idea for solid-state batteries has been around for awhile, but it sounds like MIT and Samsung may have figured it out.

    Samsung, MIT say their solid-state batteries could last a lifetime
    http://www.computerworld.com/article/2973483/sustainable-it/samsung-mit-say-their-solid-state-batteries-could-last-a-lifetime.html

    By eliminating liquid electrolytes, the batteries eliminate fire risk

    esearchers have developed a new material for a basic battery component that they say will enable almost indefinite power storage.

    The new material — a solid electrolyte — could not only increase battery life, but also storage capacity and safety, as liquid electrolytes are the leading cause of battery fires.

    Today’s common lithium-ion batteries use a liquid electrolyte — an organic solvent that has been responsible for overheating and fires in cars, commercial airliners and cell phones.

    With a solid electrolyte, there’s no safety problem.

    “You could throw it against the wall, drive a nail through it — there’s nothing there to burn,”

    Additionally, with a solid-state electrolyte, there’s virtually no degradation, meaning such batteries could last through “hundreds of thousands of cycles,” Ceder added.

    Reply
30. August 26, 2015 at 7:49 am

    Tomi Engdahl says:

    One of Silicon Valley’s great contributions to the world has been the demonstration of how the application of entrepreneurship and venture capital to electronics and semiconductor hardware can create wealth with developments in semiconductors, displays, design automation, MEMS and across the breadth of hardware developments. But in recent years concerns have been raised that traditional venture capital has turned its back on hardware-related startups in favor of software and Internet applications and services.

    Source: http://www.eetimes.com/radio.asp?webinar_id=12

    Reply
31. August 26, 2015 at 10:51 am

    Tomi Engdahl says:

    iPhone6 Powered by Hydrogen
    Fuel cell has week-long battery life
    http://www.eetimes.com/document.asp?doc_id=1327517&

    The world has been “waiting for an ‘unforeseen leap’ in battery technology. That leap may not be far off, but it isn’t the battery that will revolutionize power in consumer electronics,” said Intelligent Energy in a recent blog titled Always in the Red: The Life and Death of the Smartphone Battery. “We, at Intelligent Energy, believe that the development of embedded fuel cells in smartphones…could be refueled with hydrogen gas from a recyclable canister and power the phone on its own.”

    “Advances in fuel cell technology have allowed it to be scaled for usage at the consumer, automobile and infrastructure levels,”

    “What we have proven with our recent prototypes of embedded fuel cell technology, in both phones and laptops, is that just as smartphones, tablets, etc. have challenged the way we communicate, fuel cells are the challenger technology to existing power sources, and that’s what makes this so exciting. The consumer applications for a portable power source are endless,” Hughes told us.

    “Hydrogen fuel-cell technologies are not confined by grids, battery life and range anxiety,” Hughes said. “And they can be integrated into many different technologies. Hydrogen fuel-cell power systems are field proven in the aerospace, automotive, consumer electronics and distributed power & generation markets.”

    Intelligent Energy has accelerated a 2,000 strong patent portfolio over the last few years as it perfected the functioning and made the fuel cell affordable for use alone, or in combination with lithium-ion batteries to make sure they always stay charged. The company has already penetrated several market segments and is planning to supply fuel-cell solutions at every scale over the next few years.

    Reply
32. August 26, 2015 at 10:53 am

    Tomi Engdahl says:

    CEO Interview: Ambiq Sees Broader Options for Low Voltage
    http://www.eetimes.com/document.asp?doc_id=1327525&

    Mike Noonen, recently appointed interim CEO at microcontroller startup Ambiq Micro, discusses the focus and opportunities for this pioneering company designing circuits that can operate below the threshold voltage of the constituent transistors.

    In January 2015 Ambiq Micro Inc. (Austin, Texas) introduced the Apollo family of Cortex-M4F-based microcontrollers. These MCUs can operate at voltages below 0.5V and the company claims that this can provide a 10-fold improvement in MCU power consumption compared with competitors’ MCUs. This is mainly based on the fact that power consumption scales with the square of voltage, although the achievable clock frequency for digital circuits also reduces with the voltage.

    However, Ambiq’s sub-threshold technology is not limited to MCUs. MCUs are almost always mixed-signal circuits and Ambiq already sells a range of real-time clock (RTC) circuits based on its technology. Noonen’s ambitions for the company are broad.

    EE Times Europe started by asking if the move by leading foundry Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) to introduce ultra-low power versions of its manufacturing processes at 55, 40, 28 and 16nm nodes was a welcome development and something that Ambiq could use.

    TSMC is offering ULP processes that operate below 1V at 55, 40 and 28nm while the 16FFC FinFET process operates at voltages down to 0.55V. These processes have all been described as offering near-threshold voltage operation. As a fabless pioneer of sub-threshold circuit operation spun out of the University of Michigan in 2010, Ambiq has had to perform its own process characterization for its low voltage use of foundry processes.

    “What TSMC has done is moving things in the right direction although, near-threshold is quite a way above the [voltage] world where Ambiq lives. But it is a good thing for Ambiq. The platforms make our lower voltage development work easier,” said Noonen.

    Emphasizing the advantage that Ambiq’s SPOT (Sub-threshold Power Optimized Technology) brings Noonen added that the Apollo series is currently based on 90nm CMOS process from TSMC. “What we have at 90nm is better than what other companies have at 55nm,” he states.

    And despite the technical claims for SPOT and the Apollo microcontroller range, MCU buying decisions are often based on the maturity of development environments and relationships with major vendors. Some of the leaders in microcontroller sales include: NXP, Freescale, Texas Instruments, STMicroelectronics, Microchip and Atmel. Has this been a problem for Ambiq?

    Noonen responded: “Our first major customer will launch in the fourth quarter. As to competition, what you say may be true in the traditional embedded space where there can be long development cycles.”

    Reply
33. August 26, 2015 at 11:02 am

    Tomi Engdahl says:

    Are you using the cloud as your time capsule?
    http://www.edn.com/electronics-blogs/power-points/4440207/Are-you-using-the-cloud-as-your-time-capsule–?_mc=NL_EDN_EDT_EDN_today_20150825&cid=NL_EDN_EDT_EDN_today_20150825&elq=ad8531cbe6f444cf8cf1a5098f9843ee&elqCampaignId=24508&elqaid=27702&elqat=1&elqTrackId=20a6250d8f4843b7a527faff710e5e3a

    The electronics industry is not immune to marketing hype or optimism, of course. Right now, our three hot buttons are “IoT,” the “cloud,” and “big data.” When you are not sure what to say, just work one or more of these three phrases into your pitch or response and you should be all set, at least for a while.

    While I understand the potential market and even end-application benefits of IoT – although not to the “it will be bigger than everything and solve every problem known” level of hype that IoT-related opportunities are made out to be – I am much more ambivalent about the cloud and, to a lesser degree, big data. I am not really sure why an application which is touted as cloud-based (such as CAD, CAE, CAM FAE, or Spice design/modeling tools) is inherently superior to one which is not, especially if the non-cloud application supports connectivity and file sharing.

    Reply
34. August 27, 2015 at 11:31 am

    Tomi Engdahl says:

    Deep Learning Pioneer On the Next Generation of Hardware For Neural Networks
    http://developers.slashdot.org/story/15/08/27/012235/deep-learning-pioneer-on-the-next-generation-of-hardware-for-neural-networks?utm_source=feedburner&utm_medium=feed&utm_campaign=Feed%3A+Slashdot%2Fslashdot%2Fto+%28%28Title%29Slashdot+%28rdf%29%29

    While many recognize Yann LeCun as the father of convolutional neural networks, the momentum of which has ignited artificial intelligence at companies like Google, Facebook and beyond, LeCun has not been strictly rooted in algorithms. Like others who have developed completely new approaches to computing, he has an extensive background in hardware, specifically chip design and this recognition of specialization of hardware, movement of data around complex problems, and ultimately core performance, has proven handy. He talks in depth this week about why FPGAs are coming onto the scene as companies like Google and Facebook seek a move away from “proprietary hardware” and look to “programmable devices” to do things like, oh, say, pick out a single face of one’s choosing from an 800,000 strong population in under five seconds..

    A Glimpse into the Future of Deep Learning Hardware
    http://www.theplatform.net/2015/08/25/a-glimpse-into-the-future-of-deep-learning-hardware/

    Convolutional neural network
    https://en.wikipedia.org/wiki/Convolutional_neural_network

    Reply
35. August 27, 2015 at 11:41 am

    Tomi Engdahl says:

    Continuing Education: It’s No Surprise that Engineers Like Homework
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1327430&

    Design News contributing writer and webcast lecturer Warren Miller learned that engineers who attend his online classes want to get very hands-on with learning.

    I just finished lecturing my most recent online course for Design News’ Continuing Education Center, “Designing with SoC FPGAs.” During the course, presented by Digi-Key, I asked students a variety of questions, via online chat, and often the answers told me what aspects of the topic the typical engineer (since that’s the typical student for my courses) was most interested in.

    In this last class, I decided to focus even more on the engineers’ desire for an immediate return on their time investment, structuring “System on Chip (SoC) FPGAs” similarly to a hands-on laboratory course. Students were able to use the free development software offered by the SoC vendor, which for this course, I selected Xilinx, to try out some hands-on exercises that allowed them to get familiar with the SoC devices, the tool flow, and design methodology. I also referenced several other hands-on examples Xilinx provides, as “homework.” Students had the option to try out additional example designs and dig deeper into advanced features and design techniques, if they desired.

    I even offered optional class projects that featured the use of a development board for the Xilinx Zynq SoC FPGA that Digilent provides (the board is available from Dig-Key). Students were able to take example designs and run them through the tools, targeting the board with the generated program files.

    Toward the end of the class, I asked students if they enjoyed the “hands-on” nature of the course and if they preferred it to some of the less-detailed courses I have done (many of the students have taken multiple Design News CEC courses that I have lectured). Perhaps not surprising, a vast majority of the students said they preferred a more hands-on course and even having homework assignments.

    I asked if they were planning on doing the homework right away, and many said they did, but a large number also said they would put the homework “on the shelf” until they had the time or until their projects got to the point where they were ready to get into the details.

    Reply
36. August 27, 2015 at 11:44 am

    Tomi Engdahl says:

    Albany Research Hub Drives Collaboration
    http://www.eetimes.com/document.asp?doc_id=1327489&

    The College of Nanoscience and Engineering (CNSE) has grown from a physics department at the State University of New York’s Albany Polytechnic campus to the hub of research and development for New York state. In a set of intricate public-private partnerships, CNSE is driving innovation across the chip industry while benefiting from consolidation.

    “We react to challenges that the industry has identified,”

    The R&D hub is designed to be vertically integrated, with competitors sharing expensive work on emerging technologies like lithography, which they can implement in processes down the line or license as IP. CNSE also hosts several architectural firms, which implement ongoing research such as in-building photovoltaics.

    “What we’re good at is integrating: the technology, workforce training, economic development strategies across the state,”

    Reply
37. August 27, 2015 at 11:46 am

    Tomi Engdahl says:

    Fabless RF Filters Cut Size, Share Same Die
    Could free space in smartphones
    http://www.eetimes.com/document.asp?doc_id=1327528&

    All the radio frequency (RF) bands that modern worldwide-coverage smartphones have to accommodate requires upwards of 60 RF filters. That number may come down soon. Superconducting RF filter specialists already with 10 percent of the basestation market, Resonant Inc. (Santa Barbara, Calif.) have decided to refocus on the handset market, making room temperature RF filters that are 25 percent smaller in area and 50 percent thinner plus they can handle two- or even three-bands per die.

    “Resonant is the world’s first fabless RF filter maker,” Bob Hammond, chief technical officer (CTO) of Resonant told EE Times. “Manufactured by leading RF foundries, our filters are not only smaller, thinner, and pack more filters per die, but will also reduce the parts count and the bill of materials [BOM].”

    Most RF filters are still manufactured by their designers, using proven technologies that date back to the 1920s and address only one frequency per die. Resonant, through its experience making superconducting filters for basestations from which it has accumulated a 70-strong patent portfolio, claims to have developed multi-band techniques that allow two or three filters to share the same die, as well as creating tunable models that can change their frequency to suit the locale in which the smartphone is being used.

    Reply
38. August 28, 2015 at 9:59 am

    Tomi Engdahl says:

    Getting the heat out of PCBs demands intelligent simulation
    http://www.edn.com/design/pc-board/4440112/Getting-the-heat-out-of-PCBs-demands-intelligent-simulation?_mc=NL_EDN_EDT_EDN_weekly_20150827&cid=NL_EDN_EDT_EDN_weekly_20150827&elq=c91010aff89c4117988b1394c6e54d09&elqCampaignId=24547&elqaid=27772&elqat=1&elqTrackId=aebdb3aa539043fba5b1940b83164a3e

    The drive for miniaturization means that more heat is being generated in very restricted spaces inside electronic and electrical equipment. Accurate thermal simulation of system behaviour can accelerate the design of products that perform better, are smaller, and prove to be more reliable.

    Until recently, thermal simulation of PCB assemblies was relatively crude, using approximations of questionable accuracy to predict real-world thermal performance. That’s beginning to change. Here, we examine the key issues around the thermal design of PCBs, and how some of the latest simulation tools are making good thermal design easy to achieve.

    Like any aspect of design, creating the optimal printed circuit board (PCB) involves trade-offs.

    Reply
39. August 28, 2015 at 10:00 am

    Tomi Engdahl says:

    7 Steps to a Successful Analog ASIC
    http://www.edn.com/design/analog/4440174/7-Steps-to-a-Successful-Analog-ASIC?_mc=NL_EDN_EDT_EDN_weekly_20150827&cid=NL_EDN_EDT_EDN_weekly_20150827&elq=c91010aff89c4117988b1394c6e54d09&elqCampaignId=24547&elqaid=27772&elqat=1&elqTrackId=58104a3c3eee41aea7d576d2c600e2c4

    Reply
40. August 28, 2015 at 10:00 am

    Tomi Engdahl says:

    Opening an FPGA-Based MIPS CPU Core to Universities
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1327535&

    Imagination’s MIPSfpga program is designed to bring a new CPU architecture education paradigm to universities around the world.

    “Education, education, education” — a simple slogan, but one that worked, and one that has contemporary implications for the electronics industry owing to the on-going shortage of newly-qualified electronics engineers, along with the concern that those new graduates are often not fully-equipped with the necessary skills to be useful to the companies that employ them.

    In the area of CPU design, however, engineering students are getting a significant boost. One company has just made the unusual decision to give something to colleges and universities around the globe that will help students gain a better understanding of the fundamentals of programmable electronics.

    In April this year, Imagination Technologies — most famous for its flagship products: PowerVR and MIPS — made a revolutionary announcement: as part of its university program, the company would start offering free and open access to a fully-validated, current-generation MIPS CPU in a complete teaching package.

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41. August 28, 2015 at 10:15 am

    Tomi Engdahl says:

    Microchip’s New PIC16F18877s: Peripheral’s Are Central
    http://www.eetimes.com/author.asp?section_id=182&doc_id=1327546&

    Microchip’s new PIC16F18877 MCUs offer a lot of interesting peripherals. The ADC is singularly powerful and complete.

    Ever-innovative Microchip has a couple of new families of 8-bit microcontrollers. The CPUs remain about the same as in the rest of the PIC16 family, but the peripherals offer some pretty interesting capabilities.

    I find the company’s part numbers baffling and can no longer correlate feature sets to numeric designations without a cheat sheet. The latest PIC16F18877 family comprises quite a few variants with different memory sizes.

    Microchip’s new family has, as is typical with modern MCUs, an ADC on board.

    Reply
42. August 28, 2015 at 10:16 am

    Tomi Engdahl says:

    Game Card Rides DRAM Stack
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1327544&

    A veteran graphics analyst takes AMD’s first graphics card with stacked memory out for a test drive.

    AMD made a breakthrough with their Graphics core Next (GCN) architecture when they brought it out in late 2013. It proved to a viable, scalable, and enduring design which has served them well. This will be the last of that generation, the last of the Fuji chips, and remarkably the test platform for their stacked 3D memory they call High-Bandwidth Memory (HBM).

    With 30 percent more performance and 30 percent lower power than the previous generation Radeon R9 290X AIB, the 175W Radeon R9 Nano becomes the world’s most power efficient Mini ITX enthusiast graphics card available—period. This sets a new bar on size and performance. Its price is going to challenge a few users, but in graphics you really do get what you pay for, so we think this is a good deal if you can afford it.

    The R9 Nano is the first GPU to deliver AMD’s new 3D stacked 4 GB of AMD’s new high-bandwidth memory on the main die itself. They run it at 500 MHz (1.0 GHz effective) and that gives the GPU 512 GB/s bandwidth—a scorcher.

    We first saw the AIB at E3 in June, and we’ve been waiting for it ever since. The R9 Nano is a marvel of technology improvements, operating at 175 watts and requiring only one 8-pin power plug, this killer board is targeted at 4K gaming and virtual reality. This is an enthusiast AIB, and is priced according. Selling at $649 it will be available by the second week of September.

    This will be the last GPU AMD offers based on the 28nm HPX process, and they’ve squeezed every ounce of performance out of the Fiji while reducing power. The Radeon R9 Nano features 64 compute units (CU) which have 64 stream processors per CU, which works out to a total of 4096 stream processors, the same as the flagship R9 Fury X.

    The AIB’s GPU has 256 texture mapping units and 64 raster operation units. Compared to the Radeon R9 Fury X with 8.6 TFlops and a 1050 MHz GPU clock, the Radeon R9 Nano hits 8.19 TFlops with a 1000 MHz engine clock. It accomplishes that partially by employing greater memory bandwidth over GDDR5 via a 4096-bit memory interface. Normally a wide bus width will cost you in power consumption, but AMD came up with some clever low power switches which they are not talking about.

    Reply
43. August 28, 2015 at 10:20 am

    Tomi Engdahl says:

    Well-Backed MEMS Startup Closed?
    http://www.eetimes.com/document.asp?doc_id=1327538&

    Sand 9 Inc. (Cambridge, Mass.), a startup founded in 2007 to develop piezoelectric MEMS resonator timing circuits as an alternative to quartz crystal devices, appears to have closed its doors.

    The company’s website is inactive and its previously given phone number is no longer in service. Other negative indicators are that a number of executives, including its last known CEO, state on their LinkedIn pages that their time with Sand 9 ended in May 2015.

    An alternative explanation is that the company has been bought as a going concern

    Over its eight years existence Sand 9 is thought to have raised about $66 million in venture capital and includes several high profile backers.

    Reply
44. August 31, 2015 at 8:15 am

    Tomi Engdahl says:

    Intel Investment Spotlights Drones’ Opportunity for Chipmakers
    http://www.eetimes.com/document.asp?doc_id=1327549&

    Intel Corp. said Thursday (Aug. 27) it has invested more than $60 million in Chinese drone maker Yuneec Holding Ltd., the clearest indication yet of the opportunity that Intel and fellow chip makers see in the nascent commercial drone space.

    “We’ve got drones on our roadmap that are going to truly change the world and revolutionize the drone industry,” said Brian Krzanich, Intel’s CEO, in a video announcing the deal.

    In a very short period of time, drones have gone from being viewed as pricey hobbyist toys to an enticing technology with serious commercial applications, including agriculture, construction, product delivery and others.

    According to a report published in January by ABI Research Inc., the small unmanned aerial vehicle market will be worth more than $8.4 billion by 2018. The report predicts that commercial drone revenue will grow at a compound annual growth rate of 51% from 2014 through 2019. By 2019, the commercial drone market will be worth roughly five times as much as the hobbyist drone market and more than twice as much as the market for military and civil service drones, according to the report.

    Chipmakers, including both Intel and Qualcomm, have taken notice, investing in companies that supply drones and drone technology.

    Reply
45. August 31, 2015 at 8:30 am

    Tomi Engdahl says:

    Analog Is More Important Than Digital: Scientific Proof
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1327551&

    At least some of those functions survive, either as standalone parts or (sigh) as microcontroller functional blocks. And the real world, thankfully, remains stubbornly analog, which means that most of the truly interesting “digital” problems are really analog problems — grounding, crosstalk, race conditions, noise, EMC, etc.

    We humans are products of the real world, too. Are we analog or digital?

    The information that makes up a unique human being is mostly to be found in two places, in our genes and in our brains. The information in genes can be considered digital, coded in the four-level alphabet of DNA. Although the human brain is often referred to as an analog computer, and is often modeled by analog integrated circuits, the reality is more nuanced.

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46. August 31, 2015 at 8:32 am

    Tomi Engdahl says:

    Nanotech Hub Targets 7nm, Beyond
    http://www.eetimes.com/document.asp?doc_id=1327492&

    Costs of developing advanced chip technology continue to rise amid rapid consolidation in the chip industry and an expanding Internet of Things that is extremely price and performance sensitive. Responding to the challenges, researchers here are collaborating to drive Moore’s Law forward.

    “As it becomes more and more expensive [to manufacture], it makes sense to integrate more process steps and [it] makes economic sense for one company to acquire another…Fewer companies can stay at the bleeding edge,”

    “Everybody’s looking for open innovation and to do that you need an environment that encourages risk taking and that generally requires trust and confidentially,” Fancher said.

    “The real challenge is not only advancing this technology, but integrating it with the rest of the chip world,”

    Reply
47. August 31, 2015 at 8:34 am

    Tomi Engdahl says:

    Giga-Scale Challenges Plague Memory Design
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1327530&

    Advanced designs are more complex and larger than ever before and designers are balancing between accuracy and performance for large scale memory simulation and verification, fine-tuning options and settings for each circuit type

    Advanced memory designers always use cutting-edge fabrication technologies for larger integration density and faster operating speed, while conserving low-power consumption. After all, memory chips are critical components that determine system performance and power.

    Similarly, embedded memory IP is also the critical piece of the SoC puzzle, consuming more than 50% of the die area of a chip. No matter what type of memory IP or memory IC –– DRAM, SRAM or flash –– greater design complexity is creating massive, giga-scale challenges, which are the last thing circuit designers need or want.

    Advanced designs are more complex and larger than ever before. The number of transistors is into the mind-boggling million or billion range and the memory’s circuit sizes have increased as well. Designers are forced to factor in reduced supply voltage and growing process variations with smaller process geometries. Shrinking design margins mean less room for designers to play and increased risk for a failed tape out. Unfortunately, design and fabrication costs at advanced nodes are increasing dramatically.

    To meet the challenges, new requirements or even re-factoring are needed for design flows and associated electronic design automation (EDA) tools. In particular, verification tools need to be accurate to give correct simulation results and capture all of the small signals, such as leakage currents. Designers also need variation design tools to trade-off chip yield and performance.

    Reply
48. August 31, 2015 at 8:36 am

    Tomi Engdahl says:

    EUV Breaks Through to Angstrom
    http://www.eetimes.com/document.asp?doc_id=1327537&

    The wavelength of visible light — 400-to-700 nanometers — makes it impossible with today’s tools to take photographs of nanoscale objects with any sort of reasonable resolution. The answer has been to use scanning electron microscopy (SEM) and atomic force microscopy (ATM), which yield reasonable images. These tools, however, produce nothing close to the angstrom-level (tenth of a nanometer) resolution of a new type of microscope that uses femtosecond pulses of extreme ultraviolet light (EUV) — the same wavelength light to be used for sub-10 nanometer semiconductor lithography.

    “In general when you go to less than 10-nm features, it is a big problem to image them. The fact that the EUV microscope is a table-top device will be a big boon to the industry.”

    SEMs and ATMs are big, heavy, expensive devices that are built into their own dedicated table, but the EUV microscope can be set on a laboratory table-top and easily moved from location to location or even stored in a closet. Plus it allows measurements to be easily made from their ultra-high contrast images which rival those of the highest resolution visible wavelength camera, only with angstrom resolution.

    The secret sauce in their process is using coherent EUV light, unlike that used in lithography, which is an omnidirectional flash. By using femto-second pulses of EUV lasers the researchers hope to not only image tiny objects, but also to adapt the technology to memory devices and medical applications.

    A computer algorithm is required to reconstruct the image from the light scattered by the 10-femtosecond pulses from the EUV laser that scans over the object to be imaged

    “The EUV laser-like beams can be used for defect detection either standalone or as an inline tool during manufacturing,”

    Reply
49. August 31, 2015 at 8:36 am

    Tomi Engdahl says:

    Qorvo Takes Strategic Stake in MEMS Vendor Cavendish
    http://www.eetimes.com/document.asp?doc_id=1327550&

    RF MEMS switch vendor Cavendish Kinetics Ltd. (San Jose, Calif.) has raised $36 million in a Series-F round of financing that includes a $25 million stake taken by RF component company Qorvo Inc. through its subsidiary TriQuint Inc.

    Reply
50. September 1, 2015 at 9:07 am

    Tomi Engdahl says:

    Slideshow: Touch Taiwan 2015
    http://www.eetimes.com/document.asp?doc_id=1327557&

    The touch screen industry is looking for a lift as demand growth for smartphones and tablets hits a lull in 2015.

    Taiwan’s Industrial Technology Research Institute (ITRI), one of the world’s largest electronics R&D organizations, may have the answer. ITRI has unveiled several new technologies to lead development of low-cost wearable devices that can be folded and rolled up in a scroll.

    At the Touch Taiwan show ended on August 28, ITRI demonstrated flexible OLED touch panels based on the organization’s proprietary FlexUP (flexible universal panel) technology for OLED production on today’s TFT-LCD equipment. The manufacturing process is compatible with existing substrates, light-emitting layers and touch manufacturing processes.

    Reply