Electronics trends for 2015

Chip designs that enable everything from a 6 Gbit/s smartphone interface to the world’s smallest SRAM cell will be described at the International Solid State Circuits Conference (ISSCC) in February 2015. Intel will describe a Xeon processor packing 5.56 billion transistors, and AMD will disclose an integrated processor sporting a new x86 core, according to a just-released preview of the event. The annual ISSCC covers the waterfront of chip designs that enable faster speeds, longer battery life, more performance, more memory, and interesting new capabilities. There will be many presentations on first designs made in 16 and 14 nm FinFET processes at IBM, Samsung, and TSMC.

There is push to go to even smaller processes, and it seems that next generation of lithography equipment are started to being used. Earlier expectation was for chipmakers to use traditional immersion lithography for production of 10 nm chip, but it seems that extreme ultraviolet (EUV) scanners that allows allow scaling to 10 nm or even smaller is being used. TSMC to Use EUV for 7nm, Says ASML. Intel and TSMC have been injecting money in ASML to push process technology.

2015 promises to see initial FPGA product releases and (no doubt) a deluge of marketing claims and counter-claims. One thing is certain: 2015 will not be boring. There will be FPGA products that use processes beyond 20nm, for example Altera and  Xilinx have committed to use the TSMC 16nm FinFET technology. There is  publicized (and rumored) race to get to production at 14nm has seen time frames for initial samples move into 2015. However, with both FPGA companies reporting gross margins of close to 70 percent, it would be possible for either company to take an initial hit on margin to gain key socket wins.

It seems that the hardware becomes hot again as Wearables make hardware the new software. Apple invest its time when it released the Apple Watch last quarter, going up against the likes of Google’s Android Wear and others in the burgeoning wearables area of design. Once Apple’s bitten into a market, it’s somewhat a given that there’s good growth ahead and that the market is, indeed, stable enough. As we turn to 2015 and beyond  wearables becomes an explosive hardware design opportunity — one that is closely tied to both consumer and healthcare markets. It could pick up steam in the way software did during the smartphone app explosion.

There will be more start-up activity within hardware sector. For recent years, the software has been on the main focus on the start-ups, and the hardware sector activity has been lower. Hardware sector has seem some start-up activity with many easy to use open hardware platforms became available (make development of complex devices easier and reachable for smaller companies). The group financing (Kickstarter, Indiegogo, etc.) have made it possible to test of new hardware ideas are market-worthy and get finance to get them to production.

EEs embrace hackathons aand accelerators. Design 2.0 is bubbling up in the engineering community, injecting new energy into the profession. In many ways, it’s the new Moore’s Law. Easy to use open hardware development platforms have made it possible to design working hardware device prototypes within hackathons.

Silicon Startups Get Incubator article tells that there will be new IC start-up activity as semiconductor veterans announced plans for an incubator dedicated to helping chip startups design their first prototypes. Keysight, Synopsys, and TSMC have signed exclusive deals to provide tools and services to the incubator. Silicon Catalyst aims to select its first batch of about 10 chip startups before April.

1,206 Comments

1. October 5, 2015 at 7:20 am

   Tomi Engdahl says:

   NXP-Freescale: Merger of ‘Compatible’ Giants on Track
   http://www.eetimes.com/document.asp?doc_id=1327868&

   NXP’s pending acquisition of Freescale is “on track,” but awaiting regulatory approvals in both China and the United States, according to Steve Wainwright, general manager of EMEA (Europe, the Middle East and Africa), vice president, sales and marketing at Freescale Semiconductor.

   Last month, the European Commission approved NXP’s acquisition of Freescale, subject to the divestment of NXP’s radio frequency power business.

   Wainwright said NXP and Freescale expect to hear from the Ministry of Commerce People’s Republic of China (MOFCOM) and the Federal Trade Commission (FTC) of the United States soon — most likely “in November.”

   “We said, at the time of the [M&A] announcement, this will get done in the fourth quarter. That hasn’t changed. But of course, you know Rick Clemmer [NXP’s CEO]. I’m sure he would have liked to see it happen in September.”

   Freescale’s Wainwright has been appointed as NXP’s general manager responsible for EMEA, once the merger goes through.

   IoT and security
   Wainwright believes automotive and the Internet of Things (IoT) will bring significant opportunities to the merged entity. At Thursday’s “Designing with Freescale” event in Paris where more than 80 demos were presented, he cautioned, “What can derail IoT is security.”

   Referring to data in the United States, where 70 percent of connected devices have no password-protected connectivity, he said Freescale is positioned and well-prepared to help IoT startup companies with security. “We offer trusted architecture to end node, gateway and cloud” complete with cryptographic security protocols.

   Reply
2. October 5, 2015 at 7:28 am

   Tomi Engdahl says:

   TSMC Turns Logic FinFET into ReRAM
   http://www.eetimes.com/author.asp?section_id=36&doc_id=1327876&

   Researchers are set to report on a 1kbit memory array made using TSMC’s 16nm FinFET logic manufacturing process. FIND ReRAM is a promising embedded non-volatile memory for the FinFET era.

   One of the more interesting papers scheduled for presentation at this year’s International Electron Devices Meeting (IEDM) is about making a non-volatile memory device—together with its array select switch—from a leading-edge logic transistor.

   The paper is set to show that hafnium-dioxide high-k dielectric material, which is used in the high-k metal gate (HKMG) of a 16nm FinFET, can be used as a resistive memory device. The paper comes shortly after Intel and Micron announced a development in non-volatile memory technology dubbed 3D Xpoint

   At IEDM researchers from Taiwan’s Tsing-Hua University and foundry chipmaker Taiwan Semiconductor Manufacturing Co. Ltd. are set to report on a 1kbit memory array made using TSMC’s 16nm FinFET logic manufacturing process. It is dubbed a FinFET Dielectric memory or FIND.

   Paper 10.1 is: 1Kbit FinFET Dielectric (FIND) RRAM in Pure 16nm FinFET CMOS Logic Process.

   Reply
3. October 5, 2015 at 7:29 am

   Tomi Engdahl says:

   Mellanox Targets Telcos with EZchip Buy
   http://www.eetimes.com/document.asp?doc_id=1327871&

   Networking chip vendor Mellanox Technologies Ltd. said Wednesday (Sept. 30) it signed a definitive agreement to acquire fellow Israeli chip firm EZchip Semiconductor, a provider of network processing chips, for roughly $811 million in cash.

   Mellanox said the deal would enhance its ability to provide intelligent interconnect and processing chips to data centers and wide area networks. The deal will also increase the size of Mellanox’s total available market to $14 billion by 2017, the company said.

   Eli Fruchter, CEO of EZchip, said the deal is about diversification and synergy amid a whirlwind of consolidation in the semiconductor space. “We believe that in the semiconductor space, larger bigger companies will do better,” Fruchter said. “We see that the synergy with Mellanox makes a lot of sense.”

   The semiconductor industry is currently undergoing an unprecedented degree of consolidation as chip vendors maneuver to increase their scale, grow sales and expand their offerings into other markets. According to market research firm IC Insights Inc., the value of semiconductor industry M&A deals in the first six months of 2015 alone totaled about $72.6 billion, more than six times the annual average for M&A deals struck during the five previous years.

   While Mellanox provides technology for network layers 1, 2 and 3, EZchip offers products for layers 3 through 7, Fruchter said. And while Mellanox currently sells mainly to data centers, EZchip sells products mostly to carrier networks, he added.

   “If you combine the layers and customers and market segments, we will be able to sell products that range from layer 1 to 7 to customers in the carrier and data center space,” Fruchter said. “That makes a lot of sense from the synergy perspective.”

   Mellanox is also seeing a “sort of merger” where cloud and data center technologies are starting to make inroads into telco environments, Deierling said. “We are seeing new technologies where people are embracing cloud architectures, trying to achieve the same efficiencies and agility and ability to manage large scale infrastructure and deliver new services very quickly,” he said. “That’s something that we are very good at in working with our cloud vendors, and we are seeing the evolution of the telco market to embrace those sort of architectures. We think the combination of the two companies puts us in a really unique position to address that evolution of the telco towards more of a cloud data center model.”

   Reply
4. October 5, 2015 at 8:13 am

   Tomi Engdahl says:

   IBM Scientists Find New Way to Shrink Transistors
   http://www.nytimes.com/2015/10/02/science/ibm-scientists-find-new-way-to-shrink-transistors.html?_r=0

   In the semiconductor business, it is called the “red brick wall” — the limit of the industry’s ability to shrink transistors beyond a certain size.

   On Thursday, however, IBM scientists reported that they now believe they see a path around the wall. Writing in the journal Science, a team at the company’s Thomas J. Watson Research Center said it has found a new way to make transistors from parallel rows of carbon nanotubes.

   The advance is based on a new way to connect ultrathin metal wires to the nanotubes that will make it possible to continue shrinking the width of the wires without increasing electrical resistance.

   One of the principal challenges facing chip makers is that resistance and heat increase as wires become smaller, and that limits the speed of chips, which contain transistors.

   The advance would make it possible, probably sometime after the beginning of the next decade, to shrink the contact point between the two materials to just 40 atoms in width, the researchers said. Three years later, the number will shrink to just 28 atoms, they predicted.

   “With carbon nanotubes, you begin with dust and you have to find a way to assemble it into a statue,”

   http://www.sciencemag.org/lookup/doi/10.1126/science.aac8006

   Reply
5. October 5, 2015 at 8:39 am

   Tomi Engdahl says:

   IBM aims to replace silicon transistors with carbon nanotubes to keep up with Moore’s Law
   http://fortune.com/2015/10/01/ibm-carbon-nanotubes/?xid=soc_socialflow_twitter_FORTUNE

   Keeping the information economy humming isn’t easy.

   IBM has developed a way that could help the semiconductor industry continue to make ever more dense chips that are both faster and more power efficient. Strap on your science hats while I explain what IBM has accomplished, and why it matters, because this is a significant step in keeping the information technology industry humming along.

   IBM IBM 0.69% researchers have figured out how to move electrons on a carbon nanotube, a structure that is 10,000 times smaller than a human hair and an awesome conductor of electricity. IBM’s breakthrough on Thursday is that it has figured out a way to atomically bond a specific type of metal to a carbon nanotube to create an incredibly tiny contact point needed to move electrons through the carbon nanotube without affecting the performance of the chip. This is a crucial step that should one day let researchers replace silicon transistors with carbon nanotubes.

   Keeping the information economy humming isn’t easy.

   IBM has developed a way that could help the semiconductor industry continue to make ever more dense chips that are both faster and more power efficient. Strap on your science hats while I explain what IBM has accomplished, and why it matters, because this is a significant step in keeping the information technology industry humming along.

   IBM IBM 0.69% researchers have figured out how to move electrons on a carbon nanotube, a structure that is 10,000 times smaller than a human hair and an awesome conductor of electricity. IBM’s breakthrough on Thursday is that it has figured out a way to atomically bond a specific type of metal to a carbon nanotube to create an incredibly tiny contact point needed to move electrons through the carbon nanotube without affecting the performance of the chip. This is a crucial step that should one day let researchers replace silicon transistors with carbon nanotubes.

   The research means that chip manufacturers may be able to make chips where the transistors are as close together as 3 nanometers. Currently the most advanced chips are between 14 and 11 nanometers apart, but moving them closer is becoming tough to contemplate. Earlier this year IBM announced with much fanfare that it had made a chip where the transistors were only 7 nanometers apart.

   Reply
6. October 5, 2015 at 8:46 am

   Tomi Engdahl says:

   Slideshow
   11 Test Products Introduced in September 2015
   http://www.eetimes.com/document.asp?doc_id=1327838&

   Reply
7. October 6, 2015 at 3:20 am

   Tomi Engdahl says:

   Georgia Tech Pumps Water Through Silicon for Chip Cooling
   http://hackaday.com/2015/10/05/georgia-tech-pumps-water-through-silicon-for-chip-cooling/

   One of the things that stops electronic devices from going faster is heat. That’s why enthusiasts go as far as using liquid nitrogen to cool CPU chips to maximize their overclocking potential. Researchers at Georgia Tech have been working on cutting fluid channels directly into the back of commercial silicon die (an Altera FPGA, to be exact). The tiny channels measure about 100 micron and are resealed with another layer of silicon. Water is pumped into the channels to cool the device efficiently.

   Even though water cooling isn’t a new idea, classical water cooling uses cold plates on the outside of the package, so they aren’t as efficient as the Georgia Tech method. By putting the water right at the source of the heat, packaging can be made smaller and it may even be possible to stack multiple chips without causing thermal management problems.

   Decapsulating ICs isn’t that hard, although removing the back part of the leadframe could be a problem.

   Liquid Cooling Moves onto the Chip for Denser Electronics
   http://www.news.gatech.edu/2015/10/05/liquid-cooling-moves-chip-denser-electronics

   Using microfluidic passages cut directly into the backsides of production field-programmable gate array (FPGA) devices, Georgia Institute of Technology researchers are putting liquid cooling right where it’s needed the most – a few hundred microns away from where the transistors are operating.

   “We believe we have eliminated one of the major barriers to building high-performance systems that are more compact and energy efficient,” said Muhannad Bakir, an associate professor and ON Semiconductor Junior Professor in the Georgia Tech School of Electrical and Computer Engineering. “We have eliminated the heat sink atop the silicon die by moving liquid cooling just a few hundred microns away from the transistors. We believe that reliably integrating microfluidic cooling directly on the silicon will be a disruptive technology for a new generation of electronics.”

   To make their liquid cooling system, Bakir and graduate student Thomas Sarvey removed the heat sink and heat-spreading materials from the backs of stock Altera FPGA chips. They then etched cooling passages into the silicon, incorporating silicon cylinders approximately 100 microns in diameter to improve heat transmission into the liquid. A silicon layer was then placed over the flow passages, and ports were attached for the connection of water tubes.

   In multiple tests – including a demonstration for DARPA officials in Arlington, Virginia – a liquid-cooled FPGA was operated using a custom processor architecture provided by Altera. With a water inlet temperature of approximately 20 degrees Celsius and an inlet flow rate of 147 milliliters per minute, the liquid-cooled FPGA operated at a temperature of less than 24 degrees Celsius, compared to an air-cooled device that operated at 60 degrees Celsius.

   Altera’s principal investigator for the project, Arifur Rahman, said: “Future high-performance semiconductor electronics will be increasingly dominated by thermal budget and ability to remove heat. The embedded microfluidic channels provide an intriguing option to remove heat from future microelectronics systems.”

   Reply
8. October 6, 2015 at 1:55 pm

   Tomi Engdahl says:

   Strike up the bandwidth!
   http://www.edn.com/design/systems-design/4440483/Strike-up-the-bandwidth-?_mc=NL_EDN_EDT_EDN_today_20151005&cid=NL_EDN_EDT_EDN_today_20151005&elq=ac81411ab71d4479a793a0ef4d0fb512&elqCampaignId=25055&elqaid=28463&elqat=1&elqTrackId=26b6bd968182431987f3079c8332b535

   While everyone agrees that one of the most pressing needs in the technology space is “How do we get to next-generation high-speed data transfer rates?” there are differing opinions as to how to accomplish this. There are even differing opinions regarding where we currently are in this process. Some companies claim that they are struggling just to get to 28 Gbps products, others say they are comfortable with their 28 Gbps technology solutions, while still others claim they have left 28 Gbps in the dust and are (data) streaming along at 56Gbps. While there may not be an exact concurrence as to where we as a hardware industry stand relative to high-speed data transfer rates, there are some givens.

   The first given is that even if we are successfully achieving information transfer rates of 28 Gbps, as an industry we have to accept that even with the best materials available today we can just barely get to 56 Gbps, which is the next level on the data transfer rate ladder.

   For my own edification, I did insertion loss plots for a typical long-reach backplane with various materials

   PTFE is so cost-prohibitive that it is not a viable solution

   The reality is that we have come a long way from FR-4 laminates to where we are now with far more sophisticated materials such as Isola’s Tachyon 100G laminate. Materials such as Tachyon 100G have gotten us this far to 28 Gbps and will likely get us to 56 Gbps for short and mid-reach systems.

   The second given is that we cannot grow bandwidth without optics. Optical systems have nearly unlimited bandwidth, but the pure and simple matter is it is difficult, if not at times nearly impossible, to put the number of optical connections required on a printed circuit board to replace the aggregate bandwidth of which copper traces are capable. Embedded silicon photonics may be the answer for the future, but with silicon photonics everything matters—the materials, the way engineers design boards and the way in which these boards are fabricated.

   In about 20 years, I think we will have silicon photonics printed circuit boards in volume production, but probably not much sooner than that.

   The third given is that we need a bridge technology that will enable us to get from the PCB solutions of today to the silicon photonics products of the future. That bridge is actually pretty simple to build and uses technology already in place— copper cables. At Samtec, we have our own in-house cable manufacturing plant, and we are able to produce very, very small, thin and flexible twinax and micro coax cables. The bandwidth achievable with these cables is an order of magnitude in difference over what is possible with current PCB technology.

   The standard design requirement for enterprise-class equipment, such as that available from Cisco or Juniper, needs to be continuously upgradeable for 10-15 years and go through three generations of bandwidth increase. We can address this need with the PCB technology we have right now and may even be able to achieve the next generation after that. Long term, we will hit the wall, so we need to find an interim (bridge) solution.

   Of particular note, when we use copper cable on PCBs in lieu of traces, the design rules are easy. All we need to account for is the skew of the cable (as opposed to the skew resulting from the glass weave in PCBs).

   With the use of copper cables on boards, we don’t need complex, high-priced materials.
   With the use of the less pricey materials on PCBs with copper cables, we are able to show that we can go faster for less cost.

   Bottom line: we are currently at a crossroads in the industry. The PCB technology that is currently in use is 30 years old. Prior to PCBs, there was wire-wrap or multi-wire technology. The ability to create PCBs really happened about 40 years ago. It took 20 years for us to really be able to fully utilize PCB technology. Then, it took 20 years for us to reach the limits of PCB technology.

   Reply
9. October 7, 2015 at 12:22 pm

   Tomi Engdahl says:

   BBC:
   Samsung third quarter profit forecast up nearly 80%

   Samsung surprises with third-quarter profit forecast
   http://www.bbc.com/news/business-34461696

   South Korean tech giant Samsung Electronics expects its third-quarter operating profit to beat market forecasts on the back of strong semiconductor sales.

   It forecasts that operating profit jumped nearly 80% from a year ago to 7.3 trillion won ($6.29bn; £4.13bn).

   The guidance figures for the three months to September exceeded analysts’ expectations of about 6.8tn won.

   The amount would mark the firm’s first quarterly profit growth in two years.

   Samsung is also the world’s biggest maker of memory chips and its semiconductor unit is expected to be its top earner for the fifth consecutive quarter.

   Reply
10. October 7, 2015 at 2:18 pm

    Tomi Engdahl says:

    Why Is RAM Suddenly So Cheap? It Might Be Windows
    http://hardware.slashdot.org/story/15/10/06/2246206/why-is-ram-suddenly-so-cheap-it-might-be-windows

    The average price of a 4GB DDR3 memory DIMM at the moment $18.50 — a price that’s far lower than at this time last year. Why is it so cheap? The memory business tends to go in boom and bust cycles, but the free availability of Windows 10 means that fewer people are upgrading their PCs, reducing RAM demand.

    Memory is dirt cheap at a time when it should be expensive
    http://www.itworld.com/article/2989724/hardware/memory-is-dirt-cheap-at-a-time-when-it-should-be-expensive.html

    If you were looking to stock up on memory, now would be a good time.

    Years ago – decades, really – a friend told me “memory equals performance.” I’ve yet to see that maxim proven wrong. So if you want to upgrade your PCs or Macs with more memory, now would be a great time to do it.

    Normally memory prices shoot up around this time of year as system builders gobble it up for their Christmas inventory build-up. While we have new CPUs from both Intel and AMD, the expected pop in PC sales from a new version of Windows did not happen, and memory is at its lowest point in recent years.

    Microsoft worked diligently to make sure Windows 10 would run on the same hardware that ran Windows 7 and 8.1, and with that icon in the system tray telling you your free copy is ready for download, Microsoft killed a lot of incentive to upgrade. Then again, if your migration was anything like mine you might just want to buy a new system with Windows 10 installed.

    Reply
11. October 7, 2015 at 2:53 pm

    Tomi Engdahl says:

    Crucial hurdle overcome in quantum computing
    http://newsroom.unsw.edu.au/news/science-tech/crucial-hurdle-overcome-quantum-computing

    A team of Australian engineers has built a quantum logic gate in silicon for the first time, making calculations between two qubits of information possible – and thereby clearing the final hurdle to making silicon quantum computers a reality.

    A team of Australian engineers has built a quantum logic gate in silicon for the first time, making calculations between two qubits of information possible – and thereby clearing the final hurdle to making silicon quantum computers a reality.

    The significant advance, by a team at the University of New South Wales (UNSW) in Sydney appears today in the international journal Nature.

    “What we have is a game changer,” said team leader Andrew Dzurak, Scientia Professor and Director of the Australian National Fabrication Facility at UNSW.

    “We’ve demonstrated a two-qubit logic gate – the central building block of a quantum computer – and, significantly, done it in silicon. Because we use essentially the same device technology as existing computer chips, we believe it will be much easier to manufacture a full-scale processor chip than for any of the leading designs, which rely on more exotic technologies.

    In classical computers, data is rendered as binary bits, which are always in one of two states: 0 or 1. However, a quantum bit (or ‘qubit’) can exist in both of these states at once, a condition known as a superposition.

    “If quantum computers are to become a reality, the ability to conduct one- and two-qubit calculations are essential,”

    “Despite this enormous global interest and investment, quantum computing has – like Schrödinger’s cat – been simultaneously possible (in theory) but seemingly impossible (in physical reality),” said Professor Mark Hoffman, UNSW’s Dean of Engineering.

    He said that a key next step for the project is to identify the right industry partners to work with to manufacture the full-scale quantum processor chip.

    Such a full-scale quantum processor would have major applications in the finance, security and healthcare sectors

    Reply
12. October 8, 2015 at 1:24 pm

    Tomi Engdahl says:

    Mark Sullivan / VentureBeat:
    Andy Rubin’s Playground Global incubator closes $300M funding round, will invest in hardware startups — Andy Rubin’s Playground incubator has closed a $300 million funding round — Former Android chief Andy Rubin has a new incubator called Playground Global, and says the firm has now closed …

    Andy Rubin’s Playground incubator has closed a $300 million funding round
    http://venturebeat.com/2015/10/07/andy-rubins-playground-incubator-has-closed-its-funding-round-and-is-now-a-vc/

    Former Android chief Andy Rubin has a new incubator called Playground Global, and says the firm has now closed a $300 million funding round and will be investing in new hardware startups.

    Playground has said that it provides resources, mentorship and funding to startups that make hardware devices.

    Reply
13. October 8, 2015 at 1:30 pm

    Tomi Engdahl says:

    Demand for components on the rise

    European component of the trade has grown for a long time and now finally the growth seems to have entered the “base keeper”. Electronic components and measuring importers’ association Elkomitin the demand components grew in the first half of the 10 per cent.

    Elkomit suggests that industrial orders are also increasing. Electronic components are used more and more widely the electronics industry, but also in almost all machines and equipment.

    One of electronics drivers, internet of things, which is also one yesterday that Elkom Fair of the main themes. Elkomit sees that Finland has a strong IoT expertise and fast-growing markets offer opportunities for a wide range of definitions of small enterprises. Several industrial internet products are available immediately at birth products, with its market area throughout the world.

    Source: http://etn.fi/index.php?option=com_content&view=article&id=3406:komponenttien-kysynta-kasvussa&catid=13&Itemid=101

    Reply
14. October 9, 2015 at 10:57 am

    Tomi Engdahl says:

    The first 5-nanometer test circuit

    The Belgian microelectronics research center IMEC and the EDA-house Cadence declare that they have made ​​first 5-nanometer silicon process test circuit. The production of EUV lithography was used and that the immersiolitograply with 193-nanometer laser.

    Thus dense circuits, the exposure is very difficult.

    The project was intended to demonstrate that the manufacture can go on a 5 nm and denser processes.

    Source: http://etn.fi/index.php?option=com_content&view=article&id=3423:ensimmainen-5-nanometrin-testipiiri&catid=13:news&Itemid=101

    Reply
15. October 9, 2015 at 11:32 am

    Tomi Engdahl says:

    Water-powered computer built by Stanford scientists
    http://www.edn.com/electronics-blogs/tech-edge/4440421/Stanford-scientists-build-water-powered-computer?_mc=NL_EDN_EDT_EDN_review_20151002&cid=NL_EDN_EDT_EDN_review_20151002&elq=87a0841ce77a4254ad9299262908027b&elqCampaignId=25040&elqaid=28448&elqat=1&elqTrackId=a84ce454ddf84a74b842b7100a364388

    Though its processing speed is significantly slower than that of a conventional electronic computer, this computer, which works by moving water droplets, can theoretically perform the same operations. The work, according to Stanford University’s Bjorn Carey, combines “droplet fluid dynamics with a fundamental element of computer science — an operating clock.”

    The water computer is described in the article “Synchronous universal droplet logic and control,” which appears in the journal Nature Physics.

    Reply
16. October 9, 2015 at 11:35 am

    Tomi Engdahl says:

    Timing closure in multi-level partitioned SoCs
    http://www.edn.com/design/integrated-circuit-design/4440519/Timing-closure-in-multi-level-partitioned-SoCs?_mc=NL_EDN_EDT_EDN_today_20151008&cid=NL_EDN_EDT_EDN_today_20151008&elq=6a7bcb9354a7416d954435bd8197b9a7&elqCampaignId=25127&elqaid=28562&elqat=1&elqTrackId=c1e8435d2c274bd7a4c574103c0828ee

    With rising SoC design complexity, hierarchical backend design closure has become almost ubiquitous across the industry. Block and sub-block partitioning allow designers to exploit engineering and tool bandwidth more efficiently through optimized resource use. In addition, this approach is compatible with a bottom-to-top design approach.

    This is in keeping with design practice wherein mature IP partitions are taken into the backend cycle while work is going on to finish the rest of the chip. Benefits like design-cycle reduction have prompted designers to push for multi-level partitioning schemes. However, as the level of hierarchical partitions increases, so do the challenges involved in their closure and signoff.

    In this paper, we discuss the major timing and implementation challenges involved in multi-level hierarchical partitioning and modeling schemes.

    Reply
17. October 9, 2015 at 11:41 am

    Tomi Engdahl says:

    Prototyping is critical to US hardware development
    http://www.edn.com/electronics-blogs/now-hear-this/4440516/Prototyping-is-critical-to-US-hardware-development?_mc=NL_EDN_EDT_EDN_today_20151008&cid=NL_EDN_EDT_EDN_today_20151008&elq=6a7bcb9354a7416d954435bd8197b9a7&elqCampaignId=25127&elqaid=28562&elqat=1&elqTrackId=9eab74ae6ea8417cb588e3e55e94cdb6

    The way in which products are developed and manufactured is a key element of the global supply chain. In terms of PCBs, we have migrated to an environment where virtually all PCB manufacturing is going off shore. The main contributor to this migration is cost.

    The vast majority of product development companies have readily embraced the OEM mantra of “If it costs less money to manufacture PCBs off-shore, then this is the path that we should continue to pursue.” However, it must be kept in mind that there is a difference between price and cost or, to put it more precisely, the best price is not always the best cost.

    In terms of “costs” to the industry, the move to offshore manufacturing of PCBs has led to a very serious crisis. US prototyping suppliers are vanishing at an alarming rate. And this phenomenon impacts all parties that are involved in the product development process from board designers and material suppliers, to board fabricators, chip providers, and packaging companies.

    Further, turning instantly to offshore manufacturing may seem the best way to cut prices but it is not the best way to cut costs. For example, the cost of running an engineering development team is about $2-million per week. Getting a prototype built offshore almost never takes less than three weeks. By the time you get the prototype from an offshore manufacturer, you have incurred almost $4-million in extra non-reoccurring engineering (NRE) costs as opposed to building the same prototype at a U.S. fabricator in less than a week.

    In truth, with the advent of the plethora of electronic devices upon which we all rely on and use, consumers have been lulled into something of a passive state in terms of hardware design. It’s not sexy; it doesn’t let me do all the cool and wonderful things I want to do with my latest acquired smartphone or tablet

    In contrast to software design, hardware design is not all that forgiving. We can’t simply make some code changes and send our customers a patch to correct a design flaw. We have to replace the whole assembly to correct it or provide an upgraded product.

    Designing new hardware or revising existing hardware is not an easy task. Hardware is not nearly as malleable as software, it is not possible to upgrade hardware via a new software download, “tweaks” to one part of a hardware design can affect other parts of the design in an unforeseen manner, and changes to existing hardware designs are rarely, if ever, inexpensive.

    In some ways, the crisis surrounding prototyping efforts is due in part to the fact that we have become spoiled and somewhat unaware. Stated more directly, it’s our own engineering and manufacturing practices that have led us to the precipice. As amazing as it may seem, there are a vast number of hardware development companies that still consider two or three respins of a board to be acceptable from both the technological and business operations level.

    Prototyping Proves Critical in U.S. Hardware Development Process
    What does the prototyping crisis really mean to the industry?
    http://www.ebnonline.com/author.asp?section_id=3835&doc_id=278869&page_number=2

    Reply
18. October 12, 2015 at 9:02 am

    Tomi Engdahl says:

    SanDisk, HP take on Micron and Intel’s faster-than-flash XPoint
    Joining forces for Storage Class Memory deal
    http://www.theregister.co.uk/2015/10/12/sandisk_and_hp_partner_to_counter_xpoint/

    HP and SanDisk are joining forces to combat the Intel/Micron 3D XPoint memory threat, and developing their own Storage-Class Memory (SCM) technology.

    SCM is persistent memory that runs at DRAM or near-DRAM speed but is less costly, enabling in-memory computing without any overhead of writing to slower persistent data storage such as flash or disk through a CPU cycle-gobbling IO stack. It requires both hardware and software developments.

    Micron and Intel’s XPoint memory is claimed to be 1,000 times faster than flash with up to 1,000 times flash’s endurance. Oddly enough HP and SanDisk say their SCM technology is also “expected to be up to 1,000 times faster than flash storage and offer up to 1,000 times more endurance than flash storage.”

    It also is expected to offer significant cost, power, density and persistence improvements over DRAM technologies, enabling servers to have tens of terabytes of SCM for use with in-memory databases, real-time data analytics, transactional and high-performance computing.

    SanDisk’s EVP for memory technology, Siva Sivaram (appropriate last syllable there), said he was pleased at the deepening relationship with HP, to which SanDisk will bring “our complete portfolio of enterprise SAS, SATA and PCIe products, and leading-edge enterprise system solutions.” That sounds like an OEM or reselling type deal.

    Reply
19. October 12, 2015 at 10:16 am

    Tomi Engdahl says:

    SMIC to Report Tunnel-FET Extension to CMOS
    http://www.eetimes.com/document.asp?doc_id=1327958&

    Chinese foundry Semiconductor Manufacturing International Corp. has manufactured complementary Tunnel FETs (C-TFETs) that operate at 0.4V using a CMOS baseline technology.

    Because of the low voltage operation, SMIC (Shanghai, China) is declaring that the platform has potential for ultra low-power applications such as the Internet of Things (IoT).

    The details are due to be revealed at the upcoming International Electron Devices Meeting (IEDM) scheduled to take place at the Washington D.C. Hilton Hotel from December 7 to 9, 2015.

    Reply
20. October 12, 2015 at 10:19 am

    Tomi Engdahl says:

    Blog
    Why Out-of-Stock Inventory May Kill Electronic Businesses this Holiday Season
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1327948&

    The holiday season could mean a sales boon for OEMs, but they’ll only be able to cash in by delivering the right experience to customers.

    With the holiday season quickly approaching, electronics retailers couldn’t be in a better position to make record breaking sales, exceeding the $1 trillion earned in 2014. Electronics make ideal gifts, and electronic stores are one of the largest revenue generating distributors, accounting for 13.6% of all holiday sales.

    Electronics constitute one of the leading purchases made for dads, and accounted for 20% of Father’s Day sales this past June. With the rise of tablets, mobile phones and wearables, retailers can expect this category to grow.

    other electronics that are also predicted to be big for business. Koenig explained, “Consumer decisions to replace their TVs at home with Ultra HD 4K units should provide a much-needed boost to the TV industry, while new smartwatches and other high-tech wearables will also expand that growing category this year.”

    Why Out-of-Stock Inventory May Kill Electronic Businesses this Holiday Season
    http://www.ebnonline.com/author.asp?section_id=3830&doc_id=278856&

    Reply
21. October 13, 2015 at 6:50 am

    Tomi Engdahl says:

    ECAD & System-level design now “going steady”
    http://www.edn.com/electronics-blogs/all-aboard-/4440512/ECAD—System-level-design-now–going-steady-?_mc=NL_EDN_EDT_pcbdesigncenter_20151012&cid=NL_EDN_EDT_pcbdesigncenter_20151012&elq=c39fee3be11a4a8380cfcf173d785401&elqCampaignId=25164&elqaid=28604&elqat=1&elqTrackId=f03beb1f579c4d9ab96d3d69a5e2925f

    One is almost tempted to ask,”Is anyone still buying plain old CAD tools?” A least, that’s the impression I got attending sessions and browsing vendor offerings at PCB West a few weeks ago.

    Zuken is one of the companies offering what they term “Product-centric design”. This means you are able to combine multiple PCBs and their interconnects into one project, as well as maintaining physical models of components and interfacing with MCAD software, allowing the PCB designer to quickly confirm at any time that their design is going to physically fit. Since miniaturized products these days rely on “squeezing all the air out” of the enclosure (gotta love that turn of phrase), having that power in one designer’s hands is a good thing.

    One session attendee explained how they would make 3-D “prints” of their PCBs, components and all, to demonstrate fit within a similarly printed enclosure. This can be done with or without system-level tools, and is less necessary with them of course, but it’s a nice way to prove out the mechanics – assuming all the component models are correct.

    Reply
22. October 13, 2015 at 6:52 am

    Tomi Engdahl says:

    Low-cost Ultra High Isolation SPDT Switch
    http://www.eeweb.com/design-articles/low-cost-ultra-high-isolation-spdt-switch

    Wide-band test instrumentation often needs signal routing. This is accomplished with mechanical switches, which are expensive and slow. When isolation requirements are not high, it is also done with electronic switches. Some high isolation switches available in the market are very expensive. Mini-Circuits has developed a pair of low-cost, high isolation, fast switching, TTL-driven, connectorized – switches that have a typical isolation of 85 dB at 1 GHz and 60 dB at 5 GHz.

    Reply
23. October 13, 2015 at 6:56 am

    Tomi Engdahl says:

    Wafer Level Chip Size Package (WLCSP) Guidelines
    http://www.eeweb.com/company-blog/nxp/wafer-level-chip-size-package-wlcsp-guidelines/

    This application note presents the Wafer Level Chip Size Packages (WLCSP) guidelines. The method uses ball drop bumps with bump pitches of 500 µm and 400 µm and plated bumps with bump pitches of 400 µm and 350 µm.

    Wafer level chip scale packages offer the smallest package size possible. The package size is equal to the die size. The solder-bumps provide the interconnection to the outside world.

    Reply
24. October 13, 2015 at 6:57 am

    Tomi Engdahl says:

    Three-Phase Output to 10 A 440 VAC
    http://www.eeweb.com/company-news/onlinecomponentscom/three-phase-output-to-10-a-440-vac/

    Onlinecomponents.com, an authorized distributor of Teledyne Relays, features the S3P relay series. The series is made up of three separate relays controller by a common DC voltage control.

    Reply
25. October 13, 2015 at 7:58 am

    Tomi Engdahl says:

    Home> Tools & Learning> Products> Product Brief
    DC/DC converter performs coulomb counting
    http://www.edn.com/electronics-products/other/4440545/DC-DC-converter-performs-coulomb-counting?_mc=NL_EDN_EDT_EDN_today_20151012&cid=NL_EDN_EDT_EDN_today_20151012&elq=95e9d566d42b4b958caab4f0ef3bab83&elqCampaignId=25166&elqaid=28606&elqat=1&elqTrackId=8065e740d5f24908a9adbd600829cc95

    A synchronous buck-boost converter with an onboard coulomb counter, the LTC3335 from Linear Technology monitors accumulated battery-discharge in long-life primary cell applications that have extremely flat battery-discharge curves. With only 680 nA of quiescent current and programmable peak input current from 5 mA to 250 mA, the device is well-suited for a wide variety of low-power battery designs, including remote sensors and monitors.

    The LTC3335 accepts an input range of 1.8 V to 5.5 V and furnishes eight user-selectable outputs between 1.8 V and 5 V

    Reply
26. October 13, 2015 at 8:10 am

    Tomi Engdahl says:

    Chip Market Decline Gathered Pace in August, says ESIA
    http://www.eetimes.com/document.asp?doc_id=1327968&

    The three-month average of global chip sales for August declined by 3 percent in comparison with the same month a year ago, according to numbers from World Semiconductor Trade Statistics (WSTS) and reported by the European Semiconductor Industry Association (ESIA).

    In July the same statistic was down by 0.9 percent and the chip market decline is therefore accelerating.

    The year-to-August market for 2015 was still up on the same period in 2014, by 2 percent, a reduction from 2.7 percent growth in the year-to-July. The indicators are that 2015 could turn in to no-growth year for the global chip market, or even one of decline.

    Reply
27. October 13, 2015 at 8:24 am

    Tomi Engdahl says:

    Startup Describes New Core, SoC
    Shasta aims to rise above today’s processors
    http://www.eetimes.com/document.asp?doc_id=1327933&

    SAN JOSE, Calif. – A year after its debut, microprocessor startup Soft Machines described in rough terms the first two products it will deliver in mid-2016, a licensable processor core and an SoC using it. The dual-core 16nm Shasta will run at up to 2 GHz and outperform existing chips with superior performance/watt, but the startup will not say which two instruction sets it will support through emulation.

    Microprocessor startups have become a rarity given the industry is consolidating around a handful of large ecosystems, mainly centered on Intel’s x86 and ARM cores. Investors have pumped a whopping $175 million into Soft Machines to date in hopes it has a rare break-out technology.

    The startup essentially turns virtualization on its head, creating a few virtual cores that are backed up by multiple physical ones. A software layer and hardware block spread the work of a single processor thread across the multiple physical cores. The approach avoids problems traditional CPUs face scaling power and frequency and requiring complex multicore programming tools, the startup said.

    Reply
28. October 13, 2015 at 8:26 am

    Tomi Engdahl says:

    Q’comm Unveils Server Bid
    Xilinx partnership rivals Intel/Altera combo
    http://www.eetimes.com/document.asp?doc_id=1327954&

    Making a long anticipated leap from its mobile roots to the cloud, Qualcomm officially entered the server market, announcing it is sampling to top-tier server makers a development platform based on a new SoC.

    The news was hailed as the strongest validation to date of ARM’s move into servers which has so far been relatively slow and bumpy. Qualcomm forged partnerships with Xilinx and Mellanox which could be important given its big data center customers are exploring FPGAs as co-processors and carriers are adopting new comms architectures such as network function virtualization (NFV).

    Qualcomm has “a long history of developing custom IP for high performance microarchitectures and we think we can leverage that expertise into world leading data centers,” Qualcomm President Derek Aberle said at a press event. “Given our position in mobile, we are consistently at the leading node…which is very important to have in a competitive solution in data center.”

    Cloud computing will account for 40% of the server market by 2018, a 110% increase from 2013, to become a $15 billion opportunity by 2020, Qualcomm said. While the U.S. leads in server demand, China is fast approaching to feed its “under penetrated” market.

    Reply
29. October 13, 2015 at 8:37 am

    Tomi Engdahl says:

    Ion-based data allows atom-sized storage cells that simulate brain structure
    https://thestack.com/world/2015/10/12/ion-based-data-allows-atom-sized-storage-cells-that-simulate-brain-structure/

    Researchers have found a new method of storing information that uses ions to save data and electrons to read data, heralding a possible move from charge-based storage to a model based on resistance – and with it a potentially game-changing miniaturisation of current data storage models.

    The work has been carried out by scientists from Kiel University and the Ruhr Universitat Bochum and amongst its findings yields the notion of reducing a storage cell in size to almost the dimensions of an atom.

    Conventional memory technologies involve the displacement of electrons by applying voltage, but this configuration of is almost at its limits in terms of future development,

    The Kiel and Ruhr researchers have looked to a storage type that’s based on electrical resistance, and have developed a component that runs along these lines. The component comprises two metallic electrodes that are separated by a “so-called solid ion conductor”. On application of voltage, the resistance of the storage cell changes -the end game (and gain) of this is that the cells built in this fashion are not only easy to produce but can be reduced to practically the size of an atom.

    Reply
30. October 13, 2015 at 10:58 am

    Tomi Engdahl says:

    Melexis Preps Sony Sensor Deal
    http://www.eetimes.com/document.asp?doc_id=1327993&

    Mixed-signal and magnetic sensor chip company Melexis NV (Ieper, Belgium) will make a deal with Sony Corp. to expand an existing agreement to deploy time-of-flight sensor technology in automotive safety and infotainment markets.

    The original deal was made with SoftKinetic SA (Brussels, Belgium), which is set to be acquired by Sony

    Melexis has been licensed to use SoftKinetic’s DepthSense technology for a number of years in such products as the MLX75023 quarter-VGA automotive ranging sensor.

    Melexis said it will enter into a license agreement with Sony for the DepthSense sensor technology upon Sony’s acquisition of SoftKinetic

    Reply
31. October 14, 2015 at 7:10 am

    Tomi Engdahl says:

    Quentin Hardy / New York Times:
    Intel Q3: beats expectations with $14.5B revenue, $3.1B net income, despite weak PC market, with data center group revenue up 12% YoY to $4.1B

    Intel’s Results Reflect Move to Cloud Computing
    http://www.nytimes.com/2015/10/14/technology/intels-results-reflect-move-to-cloud-computing.html?_r=0

    SAN FRANCISCO — The Intel Corporation is changing with the times.

    Intel became the world’s biggest producer of semiconductors thanks mostly to personal computers, which eventually led to chips for server computers.

    Now, the new hot trend of cloud computing — data centers filled with tightly connected servers — is remaking Intel.

    PC sales are in a long decline, as customers increasingly use online services connected to mobile devices. While Microsoft and others to try to revive the market with new designs and tabletlike models, in the most recent quarter worldwide PC shipments fell 10.8 percent from the year before, according to IDC.

    Making PC chips is still a big business, but not the way it once was. The data center group also has much higher profit margins: Operating profit from PC chips was $2.1 billion, down 20 percent from a year ago, while data center chips had an operating profit of $2.1 billion, up 9 percent.

    “If you zoom out, we’re not a PC company anymore,” Stacy J. Smith, Intel’s chief financial officer, said in an interview. “We still work with PC companies, but we’re deeply involved in automotive, wearables, all kinds of new devices.”

    Last month, Intel even sponsored Fashion Week in New York, stressing the convergence of clothing and computing.

    Intel’s net income for the third quarter was 64 cents a share, above the projections of Wall Street analysts.

    Reply
32. October 14, 2015 at 7:32 am

    Tomi Engdahl says:

    ARM Brings SoC ASIC Design to Embedded IoT Mainstream
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1327994&

    The free SoC tools on ARM’s DesignStart portal have been retargeted from a purely academic and educational focus to offering embedded IoT developers low-cost ASIC design services.

    ARM Ltd. this week introduced an ARM Cortex-M0-based system-on-chip design capability that the company expects to change the economics of embedded and IoT application specific IC development. The new tool suite is now available on ARM’s existing DesignStart portal, a free SoC design resource introduced several years ago by ARM for use by academic institutions for educational purposes.

    The free development package includes a Cortex-M0 processor and system design kit (SDK), featuring system IP, peripherals, test bench and software, and a free 90-day license for the full suite of ARM Keil MDK software development tools. York said the package will enable the design, simulation and testing of new SoCs using a pre-configured Cortex-M0 processor without incurring the capital costs typically associated with up-front licensing.

    Despite its limitations, the academic offering has been used by over 50 universities worldwide since its launch several years ago. York said the company will continue to offer such limited SoC design capabilities free to institutions that express an interest.

    DesignStart
    http://www.arm.com/products/designstart/index.php

    Reply
33. October 14, 2015 at 7:39 am

    Tomi Engdahl says:

    Leading-Edge Driving Pure-Play Foundry Growth
    http://www.eetimes.com/document.asp?doc_id=1328004&

    The total pure-play foundry market is forecast to grow 6.1 percent to $44.9 billion in 2015, according to IC Insights.

    However, all the growth will be accounted for by growth in sales at geometries below 40nm.

    The <40nm pure-play foundry market is expected to increase 24 percent to $16.1 billion in 2015 compared to $13.0 billion in 2014. In contrast, pure-play foundry sales of ≥40nm devices are forecast to decline 2 percent to $28.8 billion.

    The figure shows sales of ≤45nm devices from the top four pure-play foundries on a quarterly basis for 2014 and 2015.

    Reply
34. October 14, 2015 at 7:40 am

    Tomi Engdahl says:

    Freescale Multi-Mode MCU Pushes IoT Envelope
    Shades of gray in ‘multi-protocol’ MCUs
    http://www.eetimes.com/document.asp?doc_id=1327995&amp;

    The multi-mode radio is the Holy Grail of IoT, since any given connected IoT devices will likely operate not in a single but multiple wireless networks.

    The Internet of Things (IoT) community has gotten a little closer to that dream with Freescale’s announcement Tuesday (Oct. 13) of a much-anticipated multi-mode wireless MCU supporting both Bluetooth Low Energy v 4.2 and IEEE 802.15.4 networks.

    Freescale’s new multi-mode radio MCU, KW41Z, comes loaded with memory – as much as 512K flash and 128K RAM. The extended memory allows multiple network stacks—Bluetooth, Thread and ZigBee—to run on a single device, enabling developers to design true multi-protocol IoT devices, according to the company.

    Further, the new MCU offers a time-slicing solution which—in the eyes of a user—makes the device look like it’s living on both networks (Bluetooth Low Energy and 802.15.4). But in fact, the device is time-slicing and switching very quickly between the two networks.

    Freescale explained that the company is offering radios “working concurrently, but not simultaneously.” Emmanuel Sambuis, executive director, MCU and connectivity products at Freescale, told EE Times, “KW41 can switch without any loss communication between Bluetooth Low Energy and 802.15.4,” enabling a dual Personal Area Network solution.

    Potential use-case scenario
    Consider the example of a smart door lock, said Freescale’s Sambuis. The wireless MCU—designed into the lock—runs both BLE and 802.15.4.

    While the host MCU runs Thread protocol in the background, the same MCU operates in BLE, enabling a user to control the lock locally from a Bluetooth-enabled smartphone or tablet. Alternatively, a user can control the lock remotely using the cloud-connected Thread mesh network, Sambuis explained.

    Without a multi-mode radio MCU like KW41Z, IoT system designers would need to add to the network a separate BLE chip to communicate with a Thread or ZigBee device.

    Reply
35. October 14, 2015 at 7:43 am

    Tomi Engdahl says:

    Researchers Demonstrate Single-Ended Die-to-Die Transceiver
    http://www.eetimes.com/document.asp?doc_id=1327985&amp;

    Researchers at the University of Toronto’s Integrated Systems Laboratory have have created a 20 Gb/s single-ended die-to-die transceiver to address some of the challenges presented by the technology likely to replace double data rate (DDR) memory.

    “It’s clear the end of DDR is in sight, especially for high performance computing,” said Anthony Chan Carusone, a professor of electrical and computer engineering at U of T. The best alternatives on the horizon – memory stacked on top of a processor or stacked memory next to the processor – both present a series of challenges when balancing density, low latency and heat dissipation. If a memory cube is placed next to the processor, the heat dissipation issues are addressed, he said, but there needs to be an interface. “That’s really where the research comes in.”

    Chan Carusone and PhD student Behzad Dehlaghi proposed a link architecture, a transceiver circuit design and a package solution to create this new die-to-die link.

    A 20 Gb/s 0.3 pJ/b Single-Ended Die-to-Die Transceiver in 28 nm-SOI CMOS. The interface connects a CMOS memory controller die at bottom of DRAM stack and the processor and achieves high density at a high data rate per pin,” said Chan Carusone.

    Ultimately, the researchers were able to demonstrate that he proposed transceiver can be used on both organic substrates and silicon interposers and consume 6.1 mW power at 20 Gb/s over a 2.5 mm interconnect with 10.7 dB loss at Nyquist frequency and 4.8 dB loss at DC. The energy efficiency of the proposed transceiver is mainly due to the use of CMOS building blocks, minimizing current in the transmitter to receiver signal path, and lowering the signal swings on the channel.

    Reply
36. October 14, 2015 at 1:02 pm

    Tomi Engdahl says:

    Intel thanks growth in IoT for positive Q3 financials
    Customer enthusiasm for the 6th-gen Intel Core processor also helped
    http://www.theinquirer.net/inquirer/news/2430382/intel-thanks-growth-in-iot-for-positive-q3-financials

    INTEL HAS BEATEN INDUSTRY EXPECTATIONS in its third quarter this year, seeing growth in the data centre, Internet of Things (IoT) and non-volatile memory businesses.

    Intel said that quarterly revenue of $14.5bn, which was flat year over year, was “above the midpoint of outlook”. The firm attributed this to a focus on the IoT of which its dedicated group showed the most promise this quarter, logging revenue of $581m, up 10 percent year over year.

    Reply
37. October 15, 2015 at 6:34 am

    Tomi Engdahl says:

    Why Is It Always ‘Someone Else’s Problem’?
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1328001&amp;

    Anyone who’s worked in chip industry will have listened to the hardware guys blaming a software problem, only to cross the room and find that the software guys are convinced that “the problem’s in the hardware.”

    We’re always hearing that innovation is a team sport. Nowhere is this more the case than in today’s semiconductor industry. Different teams and skill sets are required to architect the system, generate the RTL, perform place and route, implement the physical design, verify and debug both the logical and physical design and generate the software that runs on a typical core-based SoC.

    You might think that in this environment, people would be used to taking collective responsibility for taping out a chip on time and to budget…

    … so why is it that one of the most commonly heard mantras in our industry is “It’s not our problem”? This is particularly true when it comes to the hardware/software teams: anyone who’s worked in our industry for any length of time will have listened to the hardware guys blaming a software problem, only to cross the room and find that the software guys are convinced that “the problem’s in the hardware”. But even within the “community” of hardware designers, there’s a tendency to blame another team.

    Part of the reason for this is inertia. People get used to working in silos and doing things in a certain way. But “the most dangerous phrase in the language is – we’ve always done it this way”

    Today, more than ever, we need to embrace a holistic approach to chip development. Technologically, an important part of this is to design into every chip structures that help us understand exactly how the final device operates: including the complex interactions between hardware blocks, often sourced from different third parties, and the relationship between hardware and software.

    The existing tools for this are inadequate – we often rely on JTAG, a technology that is 30 years old. But because we have the excuses that “it’s somebody else’s problem” and “we’ve always done it this way,” the impetus to adopt a better approach is not there.

    Reply
38. October 15, 2015 at 6:39 am

    Tomi Engdahl says:

    Xilinx Revenues Driven By Data
    CEO expects to play in x86, non-Intel server markets
    http://www.eetimes.com/document.asp?doc_id=1328017&amp;

    Programmable device company Xilinx today (Oct. 14) announced second quarter fiscal 2016 sales of $528 million, down 4% from the prior quarter and down 13% year-over-year. Second quarter net income was $127 million, with the Asia Pacific region accounting for 40% of revenue.

    “The quarter was characterized by solid profitability and strong new product growth. Sales performed as expected with increases from wired and wireless communications offsetting expected declines from defense,” said Moshe Gavrielov, Xilinx President and CEO, said in a release.

    Following the announcement of a server partnership with Qualcomm, Xilinx put emphasis on its data center future. The company’s data center and communications business grew 5% sequentially to account for 41% of Xilinx’s revenue in Q2.

    Gavrielov sees data centers as an emerging market and networking, storage, and acceleration as the three main areas of focus. Xilinx is in a good position with the first two, but is in the middle of a competitive acceleration market split among several architectures.

    “Clearly Intel has the highest market share, but it is expected to have more than one set of solutions driven by the customers who are large, independent companies,” Gavrielov said, adding that Xilinx’s partnership with Qualcomm is not exclusive. “I believe, over time, that [data centers] will provide an interesting growth opportunity for us. We have a strategy that allows us to participate in different levels of integration.”

    The server acceleration market could be hundreds of millions or a billion dollar industry, though Gavrielov cautioned “it’s premature to count on it” and that it would be several years before Xilinx would see results.

    Reply
39. October 15, 2015 at 6:56 am

    Tomi Engdahl says:

    Ag3.0: A Field of Opportunities for Tech
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1328015&amp;

    CEVA sees the challenges fo raising population and climate change to agriculture as a good thing for the semiconductor industry.

    For thousands of years, farmers have been looking up to the clouds to try to decipher what’s in store for their crops this season. Today, a new cloud is on the horizon. More and more farmers are turning to big data and precision farming, in order to maximize the potential of their land and resources as well as the quality of their produce, while minimizing the impact on the environment.

    Why on earth?
    As the human population grows and resources become more and more scarce, specifically water and arable land, innovative solutions are required in order to meet the increasing demand. According to the United Nations’ World Population Prospects report, by the year 2050 the earth’s population will grow to almost ten billion people. In addition to the swelling population, there is very little arable land left on the planet to grow more crops.

    Ag3.0: A field of opportunities for semiconductors
    http://www.embedded.com/electronics-blogs/say-what-/4440583/Ag3-0–A-field-of-opportunities-for-semiconductors

    Enter Precision Agriculture

    In an article from 2012, Dr. Jim Budzynzki describes the evolution of farming in the 20th century. Ag1.0, according to this description, was labor intensive, low productivity, traditional farming.

    Ag2.0 was the dramatic shift in the industry that mostly took place in the second half of the twentieth century. This shift included the introduction of synthetic fertilizers and pesticides, significantly driving up efficiency and reducing differentiation, effectively cutting costs.

    Ag3.0, he suggests, is the new paradigm which will bring with it a huge surge in the use of technology to accurately manage farms, while shifting focus from efficiency to profitability. A phrase he suggests will be in use is “No molecule wasted”.

    It seems that’s a pretty good description of where the agriculture industry is headed. In today’s technologically pioneering farms, autonomous combines are already harvesting crops using extremely precise Global Positioning Systems (GPS), accurate down to the centimeter, while using special sensors on the ground to perform grid sampling of the fields. Drones fly overhead, mapping the field and collecting millions of different data points, and sending them to the cloud to be processed. Meanwhile, the farmer looks at his tablet, immediately identifying areas that require special attention. The collected information is then fed back into the tractors and choppers which automatically make corrections for amounts of pest control substance. This scenario is still quite rare, but more and more farmers are adapting to this revolution in agriculture brought on by information technology.

    In every piece of technology in this futuristic scenario there are many components that require digital signal processing. All the different monitoring functions require sensors that can collect the relevant data, as well as communication processors that can send the data using various wireless communication standards to the cloud. From extremely low-power sensor networks, through proprietary communication for drones, all the way to high-speed LTE networks for tractors and concentrators, communication processors for Ag3.0 must remain flexible. The autonomous farming vehicles, tractors, combines, choppers and drones, all need vision capabilities as well as intensive processing power to derive intelligence from the visual data. They also require extremely accurate GPS capability, so that they can both navigate properly and report information on each and every plant that might need fine tuning in water, nutrient or pesticide application. The farmer, who is in charge of this whole operation, requires a handheld device with LTE and Wi-Fi connectivity and processing capabilities, in order to display the processed information, and make decisions in cases that require intervention.

    While Ag3.0 shows a lot of promise, it is clear that a significant capital investment is required to adopt these cutting-edge solutions.

    Reply
40. October 15, 2015 at 7:08 am

    Tomi Engdahl says:

    Semiconductor sales slump in 2015 due to weak PC demand
    But blue skies are round the corner with a 2017 recovery
    http://www.theinquirer.net/inquirer/news/2430476/semiconductor-sales-slump-in-2015-due-to-weak-pc-demand

    SALES OF SEMICONDUCTORS have remained sluggish during 2015 and look set to drop still further in 2016, according to new research from Gartner.

    Last quarter, 2.5 percent growth was expected for 2015, but this has been revised down to a one percent drop in the market. 2016 remains predicted to see a 3.3 percent drop.

    “We are continuing to see weakness in end-user electronics demand in response to an uncertain economic environment, which is putting a dampener on 2015 spending,” said Takashi Ogawa, research vice president at Gartner. “Next year we are anticipating DRAM manufacturers to respond to oversupply with dramatic reductions in their investment plans.”

    Reply
41. October 15, 2015 at 8:16 am

    Tomi Engdahl says:

    Graphene Grown on Semiconductors Big Step Toward Manufacturability
    http://hackaday.com/2015/10/14/graphene-grown-on-semiconductors-big-step-toward-manufacturability/

    No modern technology has been met with more hype than graphene. These single-layer sheets of carbon promise everything from incredibly efficient power grids to more advanced electronics to literal elevators to space. Until now, though, researchers have yet to produce graphene sheets or ribbons in a reliable way. Researchers at the University of Wisconsin at Madison and the US Department of Energy Argonne National Laboratory have done just that, growing graphene nanoribbons on the surface of a germanium crystal.

    Direct oriented growth of armchair graphene nanoribbons on germanium
    http://www.nature.com/ncomms/2015/150810/ncomms9006/full/ncomms9006.html

    Reply
42. October 16, 2015 at 6:57 am

    Tomi Engdahl says:

    News & Analysis
    TSMC Slashes 2015 Capex by over 25% to $8 Billion
    http://www.eetimes.com/document.asp?doc_id=1328022&amp;

    Taiwan Semiconductor Manufacturing Co. (TSMC), which for the first time this year led the world’s chipmakers with the largest announced capital expenditure, will cut the 2015 budget by more than a quarter to $8 billion after demand slumped.

    The world’s largest chip foundry earlier this year set its planned capex within a range of $10.5 billion and $11 billion.

    A slowdown in global demand and inventory reduction that will probably continue during the fourth quarter this year have had a negative impact on business, TSMC Co-CEO Mark Liu said at a meeting to announce the company’s third-quarter 2015 results. Unit growth for smartphones, the largest business driver for TSMC, is slowing, Liu added.

    For the first time, TSMC recognized 16nm FinFET products as part of its quarterly revenue. Together, 16nm and 20nm products accounted for 21 percent of TSMC’s third-quarter sales of NT$212.5 billion ($6.6 billion), the company said.

    The company’s most advanced technology node will continue to ramp strongly in the fourth quarter, TSMC said.

    TSMC reiterated its expectation that 16nm will be a “long node” similar to its cash cow 28nm process that went unchallenged in the marketplace for nearly five years.

    TSMC uses its 16nm FinFET process to make the A9, compared with Samsung, using its 14nm FinFET process.

    TSMC said its work on upcoming 10nm and 7nm technology nodes is proceeding well. The company will begin technology qualification for 10 nm during the fourth quarter this year, and customer tapeouts will start early in 2016, according to Co-CEO Mark Wei.

    “The migration from 10nm to 7nm provides substantial improvement in performance, power and density,”

    Reply
43. October 16, 2015 at 6:58 am

    Tomi Engdahl says:

    Report: Analog Devices, Maxim in Merger Talks
    http://www.eetimes.com/document.asp?doc_id=1328023&amp;

    The share prices of both Analog Devices and Maxim Integrated Products spiked late on Wednesday Oct. 14 after reports that the two companies are in talks about a potential merger.

    The potential deal is the latest in a wave of consolidation taking place across the semiconductor industry.

    Fairchild Reportedly in Sale Talks with Infineon, On Semi
    http://www.eetimes.com/document.asp?doc_id=1328026&amp;

    Fairchild Semiconductor International Inc. (San Jose, Calif.)—a name synonymous with Silicon Valley since the original company’s formation in 1957—has hired Goldman Sachs to help it find a buyer for the company, according to a Bloomberg report.

    Infineon has been growing its business by acquisition since it got rid of its wired and wireless communications businesses. Infineon acquired International Rectifier for about $3 billion in a deal that closed at the beginning of 2015.

    Reply
44. October 16, 2015 at 11:48 am

    Tomi Engdahl says:

    Industrial-Strength Processor Has a Core For That
    http://www.eetimes.com/document.asp?doc_id=1327964&amp;

    Addressing themes of high performance, real-time control, multimedia, and connectivity requirements in industrial applications, Texas Instruments (TI) has released a heterogeneous processor architecture with devices having as many as ten separate cores to handle these diverse tasks. The Sitara AM57x processor family, taglined with “there’s a core for that,” combines computational, real-time control, and hardware accelerator cores for a variety of functions into a single, integrated device targeting industrial, robotics, imaging, and other demanding applications. A unified processor SDK and pin compatibility across the family provide developers with design scaleability over a range of performance needs.

    “There are three dimensions of scaleability to the AM57x series,” said Carlos Betancourt, a marketing director at TI, in an interview with EE Times,”speed, the number of cores, and multimedia empowerment.” Family members provide various combinations in all three areas, he added, filling in the performance range between the existing AM335x Sitara and C66x DSPs.

    Reply
45. October 16, 2015 at 11:54 am

    Tomi Engdahl says:

    Active voltage positioning reduces output capacitors
    http://www.edn.com/design/power-management/4440546/Active-voltage-positioning-reduces-output-capacitors-?_mc=NL_EDN_EDT_EDN_weekly_20151015&cid=NL_EDN_EDT_EDN_weekly_20151015&elq=a824dfd02c384a40b1e6091ee0010a29&elqCampaignId=25242&elqaid=28712&elqat=1&elqTrackId=3d3cbed976f147b5b2c9be90db8674be

    Power supply performance, especially transient response, is key to meeting today’s demands for low voltage, high current microprocessor power. In an effort to minimize the voltage deviation during a load step, a technique that has recently been named “active voltage positioning” is generating substantial interest and gaining popularity in the portable computer market. The benefits include lower peak-to-peak output voltage deviation for a given load step, without having to increase the output filter capacitance. Alternatively, the output filter capacitance can be reduced while maintaining the same peak-to-peak transient response.

    The term “active voltage positioning” (AVP) refers to setting the power supply output voltage at a point that is dependent on the load current. At minimum load, the output voltage is set to a slightly higher than nominal level. At full load, the output voltage is set to a slightly lower than nominal level. Effectively, the DC load regulation is degraded, but the load transient voltage deviation will be significantly improved. This is not a new idea, and it has been observed and described in many articles. What is new is the application of this principle to solve the problem of transient response for microprocessor power.

    In order to implement voltage positioning, a method for sensing the load current is required. This information must then be used to move the output voltage in the correct direction.

    Reply
46. October 16, 2015 at 1:55 pm

    Tomi Engdahl says:

    China to consume nearly 30% of the world’s flash, 21% of DRAM
    http://www.computerworld.com/article/2993841/data-storage-solutions/china-to-consume-nearly-30-of-the-worlds-flash-21-of-dram.html

    15nm and 16nm process flash have become the industry’s mainstream technologies

    Chinese domestic DRAM and NAND flash consumption is dramatically increasing with the rise in popularity of Chinese PCs and smartphones, according to a new report from TrendForce.

    China this year will purchase $12 billion worth of DRAM and $6.67 billion worth of NAND flash, representing 21.6% and 29.1% of the global revenues for those markets, respectively.

    “Increasing shipments of Chinese-branded PCs and smartphones in recent years have contributed to the overall DRAM demand,” said Avril Wu, assistant vice president at DRAMeXchange. “China’s top PC maker Lenovo and the global PC market leader HP are neck on neck on shipments, and this is an indication that the Chinese brand vendors’ purchasing power in the DRAM market is getting stronger every year.”

    According to TrendForce’s smartphone shipment report for the third quarter of this year, seven of the world’s top 10 smartphone vendors hail from China.

    Additionally, server growth in China has been spurred by the popularity of the Internet of Things in recent years. The country has already consumed nearly 20% of the world’s server DRAM supply this year.

    “Clearly, China’s economic growth is closely tied to the DRAM industry,” TrendForce stated in a news release.

    Solid-state drives (SSDs) currently lead the market in NAND flash demand, and the uptake of SSDs in notebooks is also climbing rapidly. Another demand driver comes from smartphone eMMCs (Embedded MultiMediaCard technology), which have seen a sharp increase in their densities as well.

    Reply
47. October 19, 2015 at 9:02 am

    Tomi Engdahl says:

    ‘Digital skin’ activates brain cells
    http://www.bbc.com/news/science-environment-34539056

    Engineers have built a flexible sensor that detects touch and, just like skin, produces electrical pulses that get faster when the pressure increases.

    They have also used those pulses to drive neuronal activity in a slice of mouse brain.

    They say the system is a more faithful replica of touch sensation than many other designs for artificial skin, making it a promising option for the development of responsive prosthetics.

    The work appears in Science magazine.

    The main advantage, according to senior author Zhenan Bao, is that the bendy, plastic-based sensor directly produces a pattern of pulses that makes sense to the nervous system.

    A skin-inspired organic digital mechanoreceptor
    http://www.sciencemag.org/content/350/6258/313

    Reply
48. October 19, 2015 at 2:26 pm

    Tomi Engdahl says:

    Are you reliable?
    http://www.edn.com/electronics-blogs/benchtalk/4440606/Are-you-reliable-?_mc=NL_EDN_EDT_EDN_today_20151019&cid=NL_EDN_EDT_EDN_today_20151019&elq=9ed1adfa1e944a5a86cf602e6ed60347&elqCampaignId=25283&elqaid=28749&elqat=1&elqTrackId=fe89b2fd1b424c08828d377b44daabf6

    How reliable are the products you design or work on? Do you give the matter much thought?

    We all get upset when something we’ve bought breaks or dies before its time. Whether it’s a car, a camera, a dishwasher, or a cellphone, we want our purchases to last forever (except when we’re looking for an excuse to upgrade).

    Manufacturers sometimes have different priorities. Not only do they want to minimize their BOM cost, but they generally don’t mind if your widget dies (after the warranty has expired, of course), and you have to buy a new one. It’s a fine line. Make your product too unreliable, and you’re not likely to get repeat business.

    There are manufacturers and industries that stress reliability however, such as aerospace and medical, and even some makers of industrial gear like oscilloscopes. Cost becomes secondary to quality and reliability. But in my experience, that’s rare in the consumer arena, even with so-called luxury goods.

    OK, let’s say you want your next design to be as reliable as possible, within reasonable limits of course. Where do you start?

    My own best advice is to get to know your components. Understand what their specs really mean

    even though a capacitor may be rated for 105° operation, it will last only a few months at that temperature. Drop to 45°, and the lifetime goes way up – perhaps to 10 years.

    In fact, virtually all components, from ICs to electrolytic caps, are governed by the Arrhenius equation, which can be simplified and summarized as follows: Lifetime doubles with every 10K (Kelvin) reduction in temperature.

    Derating (using a component below its maximums) also improves reliability

    The bible of component reliability is the famous MIL-HDBK-217.

    Reply
49. October 20, 2015 at 6:45 am

    Tomi Engdahl says:

    Microsemi Offers to Buy PMC-Sierra in $2.4 Billion Deal
    http://www.nytimes.com/2015/10/20/business/dealbook/microsemi-offers-to-buy-pmc-sierra-in-2-4-billion-deal.html?_r=0

    The California chip maker Microsemi Corporation said on Monday that it had offered to acquire its fellow chip maker PMC-Sierra in a cash-and-stock deal valued at about $2.4 billion.

    The offer, in the form of a letter to PMC-Sierra’s board of directors on Monday, came as Microsemi sought to derail a competing proposal from Skyworks Solutions, a rival chip maker and supplier to Apple.

    Skyworks, based in Woburn, Mass., offered to buy PMC-Sierra for $2 billion in cash this month.

    The deal would be subject to regulatory and shareholder approval.

    Reply
50. October 20, 2015 at 12:56 pm

    Tomi Engdahl says:

    The First 5nm Chip
    http://hackaday.com/2015/10/20/the-first-5nm-chip/

    For almost forty years, integrated circuits have become smaller and smaller. These chips started out with massive transistors in the early 1970s. They shrank to less than 1μm by 1990, and shrank yet again to less than 100nm by the turn of the last century. Now, Imec and Cadence are experimenting with 5nm technology – the smallest technology available for any mass-produced integrated circuit.

    The history of microelectronic fabrication over the last decade is a story of failure. Something happened in 2005, and although chips could be designed at ever-smaller technologies, the transition to these smaller manufacturing processes didn’t go as smoothly as in the 70s, 80s, and 90s.

    Imec and Cadence Complete Tapeout of First 5nm Test Chip
    Cadence Innovus Implementation System Enables Optimal PPA for Advanced Designs
    http://www.cadence.com/cadence/newsroom/press_releases/pages/pr.aspx?xml=100715_imec5nm

    Nano-electronics research center imec and Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that the companies completed the first tapeout of a 5nm test chip using extreme ultraviolet (EUV) as well as 193 immersion (193i) lithography. To produce this test chip, imec and Cadence optimized design rules, libraries and place-and-route technology to obtain optimal power, performance and area (PPA) scaling via Cadence® Innovus™ Implementation System. Using a processor design, imec and Cadence successfully taped out a set of designs using EUV lithography as well as Self-Aligned Quadruple Patterning (SAQP) for 193i lithography, where metal pitches were scaled from the nominal 32nm pitch down to 24nm to push the limit of patterning.

    “Our collaboration with Cadence plays an important part in the development of the world’s most advanced geometries including 5nm and below,” said An Steegen, senior vice president of Process Technology at imec.

    Reply