Electronics trends for 2015

Chip designs that enable everything from a 6 Gbit/s smartphone interface to the world’s smallest SRAM cell will be described at the International Solid State Circuits Conference (ISSCC) in February 2015. Intel will describe a Xeon processor packing 5.56 billion transistors, and AMD will disclose an integrated processor sporting a new x86 core, according to a just-released preview of the event. The annual ISSCC covers the waterfront of chip designs that enable faster speeds, longer battery life, more performance, more memory, and interesting new capabilities. There will be many presentations on first designs made in 16 and 14 nm FinFET processes at IBM, Samsung, and TSMC.

There is push to go to even smaller processes, and it seems that next generation of lithography equipment are started to being used. Earlier expectation was for chipmakers to use traditional immersion lithography for production of 10 nm chip, but it seems that extreme ultraviolet (EUV) scanners that allows allow scaling to 10 nm or even smaller is being used. TSMC to Use EUV for 7nm, Says ASML. Intel and TSMC have been injecting money in ASML to push process technology.

2015 promises to see initial FPGA product releases and (no doubt) a deluge of marketing claims and counter-claims. One thing is certain: 2015 will not be boring. There will be FPGA products that use processes beyond 20nm, for example Altera and  Xilinx have committed to use the TSMC 16nm FinFET technology. There is  publicized (and rumored) race to get to production at 14nm has seen time frames for initial samples move into 2015. However, with both FPGA companies reporting gross margins of close to 70 percent, it would be possible for either company to take an initial hit on margin to gain key socket wins.

It seems that the hardware becomes hot again as Wearables make hardware the new software. Apple invest its time when it released the Apple Watch last quarter, going up against the likes of Google’s Android Wear and others in the burgeoning wearables area of design. Once Apple’s bitten into a market, it’s somewhat a given that there’s good growth ahead and that the market is, indeed, stable enough. As we turn to 2015 and beyond  wearables becomes an explosive hardware design opportunity — one that is closely tied to both consumer and healthcare markets. It could pick up steam in the way software did during the smartphone app explosion.

There will be more start-up activity within hardware sector. For recent years, the software has been on the main focus on the start-ups, and the hardware sector activity has been lower. Hardware sector has seem some start-up activity with many easy to use open hardware platforms became available (make development of complex devices easier and reachable for smaller companies). The group financing (Kickstarter, Indiegogo, etc.) have made it possible to test of new hardware ideas are market-worthy and get finance to get them to production.

EEs embrace hackathons aand accelerators. Design 2.0 is bubbling up in the engineering community, injecting new energy into the profession. In many ways, it’s the new Moore’s Law. Easy to use open hardware development platforms have made it possible to design working hardware device prototypes within hackathons.

Silicon Startups Get Incubator article tells that there will be new IC start-up activity as semiconductor veterans announced plans for an incubator dedicated to helping chip startups design their first prototypes. Keysight, Synopsys, and TSMC have signed exclusive deals to provide tools and services to the incubator. Silicon Catalyst aims to select its first batch of about 10 chip startups before April.

1,206 Comments

1. March 12, 2015 at 2:06 pm

   Tomi Engdahl says:

   Linduino Power System Management (PSM)
   http://www.edn.com/electronics-blogs/power-system-management-design/4438852/Linduino-Power-System-Management–PSM-?_mc=NL_EDN_EDT_EDN_systemsdesign_20150311&cid=NL_EDN_EDT_EDN_systemsdesign_20150311&elq=6b81474370884005814916324a847564&elqCampaignId=22035&elqaid=24740&elqat=1&elqTrackId=310a9f9fea6d48f39f07bca8aab57477

   While many engineers use a dongle and tools to configure Power System Management devices via PMBus, a growing number of designs are adding Board Management Controllers, or connecting their PMBus to an existing microcontroller or application processer. At LTC, the dongle/tool option is comprised of a DC1613 and LTpowerPlay, and firmware development is supported with Linduino for Power System Management, aka “Linduino PSM.”

   Reply
2. March 12, 2015 at 2:08 pm

   Tomi Engdahl says:

   AVSBus: What is it? Guest blog 1
   http://www.edn.com/electronics-blogs/power-system-management-design/4427515/AVSBus–What-is-it–Guest-blog-1

   This blog is the first in a 3-part series giving more details on the new AVSBus standard which is being incorporated into PMBus 1.3.

   The purpose of AVS is different than that of PMBus. AVSBus complements PMBus by providing a direct point-to-point link between a Point of Load (POL) voltage controller and its load. With AVS, the load can make adjustments to its power as often as needed much faster than could be done with PMBus. The load can also use AVSBus to read back current, temperature and some status information, which in the 3-wire implementation results in there being a closed feedback loop between the load and the POL controller.

   Reply
3. March 12, 2015 at 2:53 pm

   Tomi Engdahl says:

   Intel Lowers Q1 Revenue Forecast By $900M To $12.8B Amid PC Sales Slump
   http://techcrunch.com/2015/03/12/intel-lowers-q1-revenue-forecast-by-900m-to-12-8b-amid-pc-sales-slump/

   The shift away from desktop PCs to smartphones and other smaller computing devices is having a big impact on a major player in the PC market. Chipmaker Intel today lowered its revenue expectations by $900 million for its Q1 earnings that will come out on April 14. It now says Q1 sales will be $12.8 billion, “plus or minus $300 million,” versus earlier guidance of $13.7 billion, “plus or minus $500 million.” It says the change was made because of weak demand for desktop PCs and economic conditions in specific markets like Europe.

   “The change in revenue outlook is a result of weaker than expected demand for business desktop PCs and lower than expected inventory levels across the PC supply chain,” the company writes. “The company believes the changes to demand and inventory patterns are caused by lower than expected Windows XP refresh in small and medium business and increasingly challenging macroeconomic and currency conditions, particularly in Europe.”

   Reply
4. March 13, 2015 at 8:20 am

   Tomi Engdahl says:

   Miniaturization and the integration of a growing number of functions in portable electronic devices require an extremely high packaging density for the active and passive components. There are many ways to increase the packaging density and a few examples would be to stack them with Package on Package (PoP), fine pitch CSP’s, 01005 and last but not least reduced component to component spacing for active and passive components (…)

   This paper will discuss different layouts, assembly and material selections to reduce component to component spacing down to 100-125um (4-5mil) from today’s mainstream of 150-200um (6-8mil) component to component spacing.

   Miniaturization with Help of Reduced Component to Component Spacing
   http://www.smtnet.com/library/index.cfm?fuseaction=view_article&article_id=2038

   Reply
5. March 13, 2015 at 9:24 am

   Tomi Engdahl says:

   The MAX31865 RTD-to-digital converter can handle 2, 3, or 4 wires, and from 100 to 1000 ohms. Yes, resistance temperature detection can be complex

   http://www.maximintegrated.com/en/products/all-products/campaigns/focus-products-q315/never-settle.html?utm_source=EEWeb%20MAX31865%20Epostcard&utm_medium=3rdparty%20eblast&utm_content=MAX31865%20Get%20EV%20Kit&utm_campaign=Focus%20Products%20Q3-15

   Reply
6. March 13, 2015 at 9:30 am

   Tomi Engdahl says:

   PCB design tool links Altium & SolidWorks
   http://www.edn.com/electronics-products/other/4438812/PCB-design-tool-links-Altium—SolidWorks?_mc=NL_EDN_EDT_EDN_weekly_20150312&cid=NL_EDN_EDT_EDN_weekly_20150312&elq=5b5eb02440004ebab250246a634c6844&elqCampaignId=22050&elqaid=24755&elqat=1&elqTrackId=8153fbb21b8847098a38cf46ceebe553

   PCBWorks is a PCB design tool created by Altium to enhance workflow collaboration between electrical and mechanical designers. Created in direct response to the divide between electrical and mechanical workflows, PCBWorks provides a powerful set of collaboration tools to integrate design data with the SolidWorks (Dassault Systèmes) mechanical design software.

   Altium says that PCBWorks “dramatically” shifts the landscape of how electronic and mechanical engineers work together, making the design process virtually seamless between ECAD and MCAD teams.

   At the core of PCBWorks is a set of schematic capture and PCB layout tools along with an interface that works in tandem with existing mechanical workflows in SolidWorks. Design data between components and mechanical enclosures are linked seamlessly between electrical and mechanical workflows, with the first managed Engineering Change Orders (ECO) process delivering changes in design data from SolidWorks to PCBWorks using native SolidWorks fil

   Reply
7. March 13, 2015 at 9:34 am

   Tomi Engdahl says:

   The fully Digital radio transmitter: Is it real or more hype?
   http://www.edn.com/design/analog/4438807/The-fully-Digital-radio-transmitter–Is-it-real-or-more-hype-?_mc=NL_EDN_EDT_EDN_weekly_20150312&cid=NL_EDN_EDT_EDN_weekly_20150312&elq=5b5eb02440004ebab250246a634c6844&elqCampaignId=22050&elqaid=24755&elqat=1&elqTrackId=123eb66584cd4f9182685321aff467b3

   Cambridge Consultants are claiming the world’s first fully digital radio transmitter built only from computing power. There are no analog components like a high-speed D to A converter with amplifier, although I would think they would need a Power Amplifier (PA) to broadcast a great distance. This is a Digital Radio transmitter and not part of a Software Defined Radio (SDR) architecture which requires analog components.

   They are demonstrating the transmitter at the Mobile World Congress (MWC)

   Reply
8. March 13, 2015 at 10:13 am

   Tomi Engdahl says:

   Xilinx Targets Embedded Software Developers with SDSoC
   http://www.eetimes.com/document.asp?doc_id=1325992&

   FGPA company Xilinx may have discovered the “Holy Grail”of embedded systems development — the ability to create a high-level representation of the system and to then quickly and easily decide which portions are to be implemented in software and which are to be realized in hardware. Furthermore, to have this solution presented in such a way that software developers can use it without having to call in their hardware counterparts.

   There are several reasons why such a solution is important, not the least that software developers outnumber hardware design engineers; also that the number of software developers coming out of university far outweighs the numbers of hardware designers.

   There are, of course, many different types of software. In the case of higher-level applications, there could be 1,000 to 10,000 software developers for every hardware designer. In embedded systems, this ratio is probably more like 10-to-1, but that’s not insignificant, especially if Xilinx can now make their programmable logic technology easily accessible and usable by the “10″ in addition to the “1.”

   Reply
9. March 13, 2015 at 10:16 am

   Tomi Engdahl says:

   One-stop Shop From IC Design to Silicon Tape Out
   http://www.eetimes.com/document.asp?doc_id=1326009&

   CEA-Leti has launched the Silicon Impulse IC design competence centre, offering IC design, advanced intellectual property, emulator and test services along with industrial multi-project wafer (MPW) shuttles.

   Established to increase the competitiveness of Leti’s industrial partners, Silicon Impulse provides immediate access to Leti’s and CEA-List’s advanced IC technologies and systems expertise.

   The IC competence center combines Leti’s large portfolio of leading-edge technologies and novel low-power design solutions with a unique service for speeding integration of Fully Depleted Silicon-on-Insulator (FD-SOI) and many other more advanced technologies (ReRAM, MEMS, 3DVLSI, Silicon Photonics), enabling heterogeneous low-power co-integration. These services are targeted to enable the rapidly emerging third-generation information-acquisition and processing devices that are key to the Internet of Things.

   Reply
10. March 13, 2015 at 10:27 am

    Tomi Engdahl says:

    Marvell CEO: The Tinkerer at The Top
    http://www.eetimes.com/document.asp?doc_id=1326017&

    How many CEOs in the semiconductor industry today are so possessed with their inner technology questions that they actually spend weekends looking for answers?

    Given their engineering backgrounds, many CEOs at chip companies can probably be found in the basement tinkering on weekends. Rarely, however, do we encounter an executive who not only discusses his personal obsession with technologies, but also reveals a solution he’s found after countless sessions of quiet experimentation — all alone at home.

    Meet Sehat Sutardja, CEO of the Marvell Technology Group.

    In a recent interview in Barcelona during the Mobile World Congress, Sutardja said, “For the last 30 to 40 years, the computer system architecture has remained the same. The advancements of computers have always depended on the bigger and faster CPU and more memory.”

    “We are going to fix it for once and all,” In a recent interview in Barcelona during the Mobile World Congress, Sutardja said, “For the last 30 to 40 years, the computer system architecture has remained the same. The advancements of computers have always depended on the bigger and faster CPU and more memory.”

    “We are going to fix it for once and all,” he said, with Marvell’s newly proposed system architecture which uses only a fraction of DRAM and puts DRAM in deep sleep. Marvell plans to launch prototype chips — based on the MoChi interconnect and FLC memories — at the end of this year.

    Sutardja, however, made it clear in the interview: “No, developing this [new system architecture] is not my job. My day job is running the company. This was my hobby.”

    But he acknowledged, “I’ve been thinking about this for decades: why a computer system has to be designed this way.”

    Obsessing about unresolved technical problems has been a lifelong habit. “I’ve been that way since I was 12 years old.” He started his career as an analog circuit engineer, so, he said, “I still think about how to build a better A-to-D converter. I work on my new ideas at night, sometimes call a professor, and discuss the issue.”

    Typically, Sutardja prefers working on his crazier ideas alone.

    Although he isn’t against teamwork, keeping harmony within a big group gets more problematic when the idea of changing system architecture is as radical as this. He said, “You don’t want to offend anyone” who might have a vested interest in keeping a certain structure the way it is. He said he’s also wary of compromising the solution for the sake of keeping everyone happy.

    Thus, the Marvell CEO kept working on his idea on his own during weekends. It wasn’t until two years ago when Sutardja finally introduced it to the Marvell team. At that time, he said he knew he had a solution, but “I couldn’t explain it properly.”

    How the world is reacting
    The initial reaction from the engineering staff was as deeply skeptical as Sutardja expected. Nobody in the team was willing to believe it without hard data. At Marvell, “We built a simulator,” he said, and 100 Marvell engineers now have the technologies running in simulation. “I think we simulated all of the ‘gotcha’ last year,” he said. “It’s unlikely anything would trip us up when we implement this on a chip. We see implementation quite simple.”

    The Marvell CEO said, “They all asked why nobody came up with this before, because it’s such a simple idea. And their own inevitable answer was they must have tried this before, but this never came to see the day of light because it never worked.”

    “SSD’s have a wear out mechanism while DRAMs do not. The scheme is similar to multi-level caching used in servers “

    Reply
11. March 13, 2015 at 12:57 pm

    Tomi Engdahl says:

    Industry is undergoing a revolution

    The factory halls is ongoing revolution, called the Industry 4.0. It requires more efficient and better performing and more severe packaged automation. Control logic is bound to collapse.

    Production is running the correct revolution, which is often referred to as the Industry 4.0.

    For manufacturers, this means a huge opportunity. Environment and process variations in the number of sensors is growing all the time. This will accelerate the transition to a distributed control architecture, the mill management to try to get rid of bottlenecks and to shorten the control loops by moving the control logic (PLC, programmable logic controllers) closer to the controlled processes. In the end, improved operational efficiency and productivity, leading to the mill operations in the largest reform since the discovery of the logic control.

    For PLC developers to set this big challenge: In order to succeed in this market for system designers to keep to pack more I / O connections, and more features ever smaller dealers in boxes. . Many analog and discrete components, which have worked very well in the previous design, are simply too large to micro-PLC and embedded controllers. 4.0 Industry’s promise can only be realized by increasing the integration of the entire PLC system, all the components.

    According to a recent market survey, most designers still believe that digital technology will bring the most opportunities for space savings. And yet, the digital circuits occupy only 15-20 per cent of the PLC module circuit board. The real problem is analog and discrete space occupied by the circuit board. These components consume up to 85 per cent use the cards in the PLC modules. Solving this problem requires a new approach to analog design.

    Control logic have been in the industry change unifying factor always Modicon 084′s after the presentation in 1969. Thanks to the digital revolution, they have become more efficient at an accelerating pace over the years. Now they are able to handle more income, longer words and more complex instruction sets.

    Today, innovations in analog and sensor technologies to facilitate manufacturers to take full advantage of the massive use of computing resources, as well as the factory lines and in the cloud. Industry 4.0 shows what is possible when you combine this intelligence everywhere to stick his perception, shared governance and sustainable, seamless connectivity.

    I / O’s are an essential link in the control logic and a plethora of sensors and actuators between that industry requires 4.0. When manufacturers add sensors around the factory, the machine designers need to increase the channel density, even if the PLC under the guidance of the available space is shrinking all the time.

    I / O isolation architecture offers the opportunity to save significant space in use. Traditionally, it is used as optocouplers per channel, wherein each opto-isolator is connected to the output of the microcontroller on a digital input. Today, the multi-channel circuits, such as MAX31911 can reverse, correct, and serialized 24-Volt digital sensor and switch the outputs of micro-controllers required by the 5-volt CMOS compatible levels. This approach may be needed to shrink the number of channels isolated to just three.

    The higher I / O density and smaller housing sizes increase their design challenges in the second fundamental way, as a result of the inevitable heat output. The system must be more energy efficient than ever before, so that the control logic does not overheat. This is especially true for applications where cooling fans and air vents are not allowed.

    In today’s signal processing, processing and communication circuits require very different power inputs, which often vary only a few volts or even within volts. This compounding the already complex electrical environment. With the addition of increasingly sophisticated energy-saving methods for a variety of power control means, sub-PSU-system price and complexity will increase.

    Protect your new security threats

    When the plant networks were closed systems, IT security generally related to roistomaisiin employees and internal data theft. These “good old days” are behind us, and they will not return. Today was connected to the control logic needs to be protected from a number of threats, including hackers, malware, and viruses.

    The system-level software will bring a basic level of protection, but in many cases it is not enough. Hardware-level security is needed for protection against them

    Industry 4.0 is fundamentally changing the rules of the game, according to which the market PLC overcome. Smaller cases, a higher I / O density and advanced features – success requires new strategies in order to manage the competing demands to cram more and more functionality into a smaller space.

    Source: http://www.etn.fi/index.php?option=com_content&view=article&id=2550:teollisuudessa-on-kaynnissa-vallankumous&catid=26&Itemid=140

    Reply
12. March 13, 2015 at 1:20 pm

    Tomi Engdahl says:

    Design Compilation in Hardware Emulators
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1326008&

    Design capacity in hardware emulators, also the compilation flow, is heavily dependent on the type of technology used in the verification engine.

    At this time, each of the three hardware emulation vendors has embraced its own architecture:

    Cadence: Processor-based architecture
    Mentor: Custom-FPGA-based or emulator-on-chip architecture
    Synopsys: Commercial FPGA-based architecture

    The first two are based on custom chips; the third is built using arrays of commercial FPGAs. The compilation process is different, and unique to each architecture.

    A simulator is essentially a software algorithm running on a computer. The algorithm processes data representing a design model described in a design language at one of multiple hierarchical level

    The compiler converts the design model into that data structure, following the guidelines of a software compiler, with some differences.

    When the output of a compiler targets computer hardware at a very low level, for example, an FPGA or a structured ASIC, it is a hardware compiler because the source code produced effectively controls the final configuration of the hardware and its operations. The output of the compiler is not a sequence of instructions. Rather, it is an interconnection of transistors or lookup tables. A quintessential example is the compiler of a hardware emulator.

    Compiler in processor-based emulators
    The operation of a processor-based emulator vaguely resembles that of a software simulator. In both engines, the design-under-test (DUT) model is converted in a data structure stored in memory.

    Reply
13. March 13, 2015 at 3:14 pm

    Tomi Engdahl says:

    Jeremy C. Owens / Mercury News:
    Cypress Semiconductor and Spansion complete $5B merger, company plans to lay off 1,600 workers worldwide within three weeks

    Exclusive: Hundreds being laid off as Cypress and Spansion merge in $5B deal, internal memo shows
    http://www.mercurynews.com/60-second-business-break/ci_27700616/exclusive-hundreds-being-laid-off-cypress-and-spansion

    Today: The merger of Silicon Valley chip companies Cypress Semiconductor and Spansion will result in layoffs that shave 20 percent of their combined workforces, a memo obtained by the Mercury News shows.

    A Cypress spokesman confirmed the memo was an internal Cypress document, but declined further comment.

    Rodgers suggests in the memo that the total layoffs will be about 20 percent of the companies’ combined workforces

    “This is a very creative financial deal that’s good for both sides,” Spansion CEO John Kispert said in a video distributed by Cypress on Thursday.

    The merger closed Thursday after shareholders of the two firms separately voted to approve the transaction.

    Reply
14. March 16, 2015 at 8:26 am

    Tomi Engdahl says:

    Design Compilation in Hardware Emulators
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1326008&

    Design capacity in hardware emulators, also the compilation flow, is heavily dependent on the type of technology used in the verification engine.

    At this time, each of the three hardware emulation vendors has embraced its own architecture:

    Cadence: Processor-based architecture
    Mentor: Custom-FPGA-based or emulator-on-chip architecture
    Synopsys: Commercial FPGA-based architecture

    The first two are based on custom chips; the third is built using arrays of commercial FPGAs. The compilation process is different, and unique to each architecture.

    Reply
15. March 16, 2015 at 8:28 am

    Tomi Engdahl says:

    Tri-Core Sensor Hub Ups Ante: Sensors Included
    InvenSense tri-core hub includes sensors
    http://www.eetimes.com/document.asp?doc_id=1326024&

    Motion-tracking sensor company InvenSense believes it also has the world’s first programmable tri-core sensor hub that also includes a 3-axis accelerometer and a 3-axis gyroscope. Announced in early January, the ICM-30630 sensor hub — named FireFly — also has a I2C port to connected magnetometers, barometric pressure sensors, humidity sensors, or any other specialized sensor for a particular application.

    InvenSense is pitching the hub as a sensor system-on-chip (SoC), in its press release.

    InvenSense® Ushers in the Era of Sensor System-On-Chip With the World’s First Integrated Motion Sensor and Multi-Core Processing
    http://ir.invensense.com/phoenix.zhtml?c=237953&p=irol-newsArticle_print&ID=2003597

    Jan. 6, 2015– InvenSense, Inc. (NYSE:INVN), the leading provider of intelligent sensor solutions, announced the world’s first Sensor System on Chip (SoC) integrating a 6-axis MEMS sensor, tri-core sensor hub, embedded Flash and SRAM, and software framework. The ICM-30630 disrupts the traditional discrete sensor subsystem in many applications by providing a true turn-key and open solution in the same footprint as competitive sensor only devices (3 mm x 3 mm x 1mm LGA package).

    The ICM-30630 consists of three distinct processors; an ARM Cortex-M0 microcontroller and InvenSense’s next generation Digital Motion Processors; DMP3 and DMP4.

    Reply
16. March 16, 2015 at 8:30 am

    Tomi Engdahl says:

    PC Drop & iPhone Rumors Color Intel Forecast
    http://www.eetimes.com/document.asp?doc_id=1326025&

    The news about the weakening PC market is getting old. And yet, when Intel cut nearly $1 billion from its first-quarter revenue forecast on Thursday (March 12), the well-told narrative of declining demand for PCs reared its ugly head again.

    The warnings from Intel also raise the issue of Intel’s ability to diversify its business — fast enough to make up for the declining PC revenue. A recent report that Intel’s LTE modems “could get into iPhones” in 2016 stirred some noise, but it’s still a rumor at this point.

    Chicago-based rating agency Fitch Ratings also reported Thursday, “Intel’s negative pre-announcement this morning suggests the end of support for Windows XP was a more significant factor than previously estimated in last year’s perceived stabilizing personal computer (PC) demand.”

    The rating agency concluded: “Consequently, extended PC refresh cycles may result in a resumption of negative PC sales growth.”

    Indeed, Intel’s newly issued forecast is a shock to some who were led to believe in recent months that the PC business was growing after two years of weakness.

    Reply
17. March 16, 2015 at 9:21 am

    Tomi Engdahl says:

    Fujitsu’s thin heat pipe could let smartphone chips run cooler
    http://www.computerworld.com.au/article/570335/fujitsu-thin-heat-pipe-could-let-smartphone-chips-run-cooler/

    While it won’t eliminate heat, this heat pipe could spread it out better and reduce extremes of temperature on the surface of smartphones

    Reply
18. March 16, 2015 at 11:41 am

    Tomi Engdahl says:

    Dyson throws $15m at solid-state battery firm Satki3
    Firm looks to give smartphones and electric cars a boost in the battery department
    http://www.theinquirer.net/inquirer/news/2399727/dyson-throws-usd15m-at-solid-state-battery-firm-satki3

    VACUUM CLEANER MAKER Dyson has thrown $15m at solid-state battery maker Sakti3, which it claims will help it in its quest to improve smartphone battery life.

    The investment means that Dyson will commercialise Sakti3′s next-generation battery technology, which can store twice as much energy as traditional lithium batteries.

    That’s because Satki3′s solid-state technology switches out reactive liquid compounds for solid lithium electrodes, storing 1,000 watt hours per cubic litre – compared to the 620 cubic litres stored by lithium-ion batteries.

    What’s more, Sakti3′s batteries are expected to be affordable to mass produce and safer than sometimes-combustible liquid-based batteries, with flammable liquid electrolyte removed.

    Dyson invests $15m in technology that may double smartphone battery life
    http://www.theguardian.com/technology/2015/mar/16/dyson-invests-15m-in-technology-that-may-double-smartphone-battery-life

    Pioneering solid-state batteries could hold twice as much electricity as current batteries for longer-lasting smartphones, tablets and electric cars

    The British vacuum company was alerted to the University of Michigan spin-off called Sakti3, which has developed next generation solid-state technology that can store twice as much energy as traditional rechargeable batteries.

    “Sakti3 has achieved leaps in performance, which current battery technology simply can’t,” said company founder James Dyson. “It’s these fundamental technologies – batteries, motors – that allow machines to work properly.”

    The lithium-ion technologies used in today’s best batteries have barely progressed since their introduction in 1991 by Sony. There has been improvement in longevity and charging times, but not a great deal in terms of the amount of energy that batteries store.

    Mobile electronics have been forced to choose: either be heavier and thicker, or else suffer from poor battery life, which is one of the reasons products like the iPhone rarely last longer than a day on a single charge.

    Reply
19. March 17, 2015 at 9:42 am

    Tomi Engdahl says:

    World’s Most Powerful Laser Diode Arrays Deployed
    http://news.slashdot.org/story/15/03/17/0220214/worlds-most-powerful-laser-diode-arrays-deployed

    The High-Repetition-Rate Advanced Petawatt Laser System (HAPLS) under construction in the Czech Republic is designed to generate a peak power of more than 1 petawatt. The key component to this instrument – the laser “pump” – will be a set of solid-state laser diode arrays recently constructed by Lawrence Livermore National Laboratory.

    Lawrence Livermore deploys world’s highest peak-power laser diode arrays
    https://www.llnl.gov/news/lawrence-livermore-deploys-world%E2%80%99s-highest-peak-power-laser-diode-arrays

    Lawrence Livermore National Laboratory (LLNL) has installed and commissioned the highest peak power laser diode arrays in the world, representing total peak power of 3.2 megawatts (MW).

    The diode arrays are a key component of the High-Repetition-Rate Advanced Petawatt Laser System (HAPLS), which is currently under construction at LLNL. When completed, the HAPLS laser system will be installed in the European Union’s Extreme Light Infrastructure (ELI) Beamlines facility, under construction in the Czech Republic.

    HAPLS is designed to be capable of generating peak powers greater than one petawatt (1 quadrillion watts, or 1015) at a repetition rate of 10 Hertz, with each pulse lasting 30 femtoseconds (30 quadrillionths of a second).

    “The Extreme Light Infrastructure in Europe is building international scientific user facilities equipped with cutting-edge laser technology to explore fundamental science and applications,”

    Reply
20. March 17, 2015 at 2:30 pm

    Tomi Engdahl says:

    SoC Spec Hits Version 1.0
    AMD-led HSA spec awaits adopters
    http://www.eetimes.com/document.asp?doc_id=1326040&

    The Heterogeneous Systems Architecture Foundation has finished its 1.0 spec, turning attention to what SoCs will support it. So far, of the group’s seven board members only Advanced Micro Devices has announced chips using HSA’s specs.

    The HSA specs are geared to let graphics cores share coherent memory as equal citizens with CPU cores, enabling performance gains across a wide range of applications. The approach also lets developers program SoCs using it in familiar high-level languages such as C++ and Python. AMD which led the formation of the group said its latest x86 SoC, Carrizo, will get certified as compliant with the spec when tests are ready later this year.

    Other leading HSA board members include Imagination Technologies, LG, Mediatek, Qualcomm and Samsung. They have not yet commented on product plans but their work on the spec suggests they have them, said Phil Rogers, president of HSA and a corporate fellow at AMD.

    Application that use parallel operations on graphics cores could gain 2-6x performance benefits using chips enabled with HSA. Without it or similar mechanisms, they cannot access more than half an SoC’s main memory because it would be partitioned into separate coherent banks, Rogers said.

    Reply
21. March 17, 2015 at 2:51 pm

    Tomi Engdahl says:

    arge system chips to get ready so that they can be exported to a production line, takes more and more time. EDA-house Cadence Design Systems has introduced a completely new tool for the environment, which speeds up the designs for obtaining silicon up to 10-fold.

    Innovus Implemention System is a suite of tools that is the most important years Cadecen release. It brings speed circuits in addition to a 10-20 percent improvement in power consumption, performance and silicon area use.

    Innovus is based on the utilization of parallel computing. The circuit code can be processed by standard 8-16 processor power workstations.

    Innovus supports the latest 16, 14 and future 10 nm FinFET processes.

    Source: http://www.etn.fi/index.php?option=com_content&view=article&id=2559:piirit-valmiiksi-10-kertaa-nopeammin&catid=13&Itemid=101

    Cadence Innovus Implementation System
    http://www.cadence.com/products/di/innovus_implementation_system/pages/default.aspx?CMP=031015_Innovus_bb

    Reply
22. March 17, 2015 at 2:56 pm

    Tomi Engdahl says:

    Matlab can now simulate from the antenna to bits

    Swedish Mathworks has introduced this year, the first update of Matlab and Simulink your tools. Now they are successful wireless system testing from the antenna to a digital bit far.

    New features help designers to develop wireless devices that use usieta antennas, smart antenna and advanced reception algorithms.

    In addition, Matlab and Simulink support 2015a versions of the software-based, ie SDR radios. It allows for LTE and other waveforms OTA testing of air of testing.

    Matlab and Simulink new versions in addition to Mathworks brought four new tools for developers. Antenna Toolbox can be used to design, analyze and visualize the antenna elements.

    Source: http://www.etn.fi/index.php?option=com_content&view=article&id=2553:matlab-osaa-nyt-simuloida-antennista-bittiin&catid=13&Itemid=101

    Matlab home page
    http://se.mathworks.com/

    Reply
23. March 17, 2015 at 2:57 pm

    Tomi Engdahl says:

    Industrial PLC market actually collapsed in 2012, when economic uncertainty coagulated investments in production facilities. Now the market has returned to a growth path. The logic of the modules, however, need to develop smaller and more efficient investment in order to justify itself.

    Frost & Sullivan research institute predicts that in 2018 PLC is sold for 14.6 billion dollars. This covers the services, software and hardware solutions that, in particular the so-called. micro size range of modules is increasing.

    Frost & Sullivan to bring security one of the key features of the new logic control system. Mills networks are no longer separate from the Internet, so they must be protected with the same seriousness and care as other business networks.

    Source: http://www.etn.fi/index.php?option=com_content&view=article&id=2552:ohjauslogiikoiden-on-pakko-kutistua&catid=13&Itemid=101

    Reply
24. March 17, 2015 at 3:03 pm

    Tomi Engdahl says:

    Intel for the jackpot: the circuit to a new iPhone

    Intel has done for many years-billion dollar losses with it’s mobile chips (acquired Infineon’s mobile phone circuit functions in 2010).

    According to the latest market rumours, the company’s fortune would finally turning. Apple has said to have chosen Intel’s LTE modem chip in the next iPhone-phone radio solution. According to Venture Beat the site, according to Intel’s LTE modem should be a new iPhone in some markets in Asia and Latin America. Intel 7360 modem chip supports 3GPP Release 9 and 10 assays.

    This would be a revolutionary design to Intel profit. At the same time, it would be a significant loss of Qualcomm.

    Source: http://www.etn.fi/index.php?option=com_content&view=article&id=2549:intelille-jattipotti-piiri-uuteen-iphoneen&catid=13&Itemid=101

    Reply
25. March 18, 2015 at 7:05 am

    Tomi Engdahl says:

    Counterfeiters will produce $1.7 trillion in fake products worldwide this year…
    Check before you buy!
    http://www.thecounterfeitreport.com/

    Reply
26. March 18, 2015 at 7:11 am

    Tomi Engdahl says:

    Marvell Touts MoChi, FLC in Shanghai
    http://www.eetimes.com/document.asp?doc_id=1326063&

    Weili Dai, president and co-founder at Marvell Technology Group (Santa Clara, Calif.), was in Shanghai Wednesday, March 18 to pitch Marvell’s recently disclosed less memory-intensive computing system architecture – scalable from wearable to data centers – in a keynote speech at the Global CEO Summit.

    Dai painted in broad strokes Marvell’s Final-Level Cache (FLC) memories and a new interconnect technology called MoChi (modular chip). She described them as basic building blocks for the company’s scalable SoCs.

    Marvell’s CEO Sehat Sutardja first presented the idea on FLC and MoChi at the international Solid-State Circuits Conference (ISSCC) last month. The approach, he said, can substantially reduce the amount of DRAM main memory needed in a system.

    Now, taking that revolutionary concept developed by her husband Sutardja, Dai is running with it in China.

    She said in her keynote that FLC is “redefining the main memory hierarchy,” while MoChi is designed to “build chips in Lego-like format.”

    She explained that the FLC-MoChi approach will significantly reduce the “cost, power and size” of electronics systems – whether PC, server, smartphone, or wearable.

    Marvell plans to launch prototype chips — based on the MoChi interconnect and FLC memories — at the end of this year.

    Breakthrough needed for longer battery life
    In a speech entitled “’Smart Me’ for Smart Life, Smart Lifestyle,” Dai touched on the growing trend of always-on, context-aware smartphones and wearable devices. “The information between me and my smartphone is now going bidirectional,” said the Marvell president. “My smartphone, which used to pick up only spotty data, is now capable of collecting all the data about me — where I am and what I am doing – through always-on sensors.”

    But for such fully bidirectional wearable devices to proliferate, “We need a breakthrough. On the dilemma of battery life, “we are still up against the wall,” Dai said. Citing the recently launched Apple Watch, Dai observed, “Apple did a good job on the smartwatch. But only 18 hours of battery life? That’s a real bottleneck.”

    “Smartwatches should last at least “weeks,” she added.

    Further, today’s smartwatch is generally designed as a sidekick for a smartphone. By leveraging the MoChi-FLC approach, she believes it’s possible to develop a wearable device that can stand on its own.

    Marvell believes the key to low power is the use of a fraction of DRAM in the main memory of a computing system, while putting DRAM in deep sleep.

    MoChi extends the ARM AXI SoC interconnect to off-chip interconnect, paving the way to more high performance 2 1/2 D designs.

    As Kevin Krewell, principal analyst at Tirias Research, explained, “Many logic chip designs want to stop at 28nm, and many analog designs don’t get the scaling benefits of smaller geometries. Being able to mix multiple process generations into a system in package (SIP) can be a cost effective alternative to SoC where the process is not optimized for all the chip functions.”

    The beauty of using MoChi in SoC is that chip designers can customize product features by selecting different flavors of MoChi’s, according to Dai. “MoChi makes the SoC highly scalable.”

    Reply
27. March 18, 2015 at 7:38 am

    Tomi Engdahl says:

    Stick a PUF to Your Board
    A foil hat for your PCB?
    http://www.eetimes.com/document.asp?doc_id=1325947&

    The Fraunhofer Institute for Applied and Integrated Security (AISEC) is developing a very versatile and flexible form of Physically Unclonable Function (PUF), one that can wrap an entire circuit board to secure it from physical attacks.

    The foil-based solution consists of patterned metal electrodes embedded into a polymer film with a self-adhesive backing. The electrodes are connected to the board to be protected and special read-out software IP running on the board’s controller can extract the PUF from the film as is has been wrapped around or stuck to the board.

    Try to remove the PUF sticker, pinch it to probe through it, scratch it or unseal it and the PUF will be altered. By detecting that change, the circuit board will be able to take any counter-measure it will have been programmed for, for example sending an alert message and disabling itself at run-time, or wiping out all of its embedded software.

    “The advantage over silicon-based PUFs is that one foil could protect an entire board or system, it is also much cheaper and simpler to implement”, he added, saying such a PUF sticker may be commercialized within the next two to three years.

    Reply
28. March 18, 2015 at 7:46 am

    Tomi Engdahl says:

    Bioinspired Imaging Technologies and Techniques
    http://www.eetimes.com/author.asp?section_id=216&doc_id=1326055&

    The October 2014 Proceedings of the IEEE, Volume 102, Number 10, was a special issue on bioinspired imaging techniques and technologies that may revolutionize embedded systems of the future.

    Bioinspired Imaging Techniques and Technologies
    http://www.embedded.com/electronics-blogs/max-unleashed-and-unfettered/4438938/Bioinspired-Imaging-Techniques-and-Technologies

    Reply
29. March 18, 2015 at 11:54 am

    Tomi Engdahl says:

    Programmable mixed-signal circuits in the fourth generation

    Silicon Valley’s Silego Technology has introduced the fourth generation of programmable mixed-signal circle. GPAK4 family brings new features to the chips and more accuracy. Target applications include consumer and industrial electronics equipment.

    The fourth generation of GPAK4-circuits the first member is SLG46620V.
    GPAK4 circuits are available 2 x 3 x 0.55 mm 20 pin STQFN enclosure

    Source: http://www.etn.fi/index.php?option=com_content&view=article&id=2569:ohjelmoitavia-sekasignaalipiireja-neljannessa-polvessa&catid=13&Itemid=101

    Reply
30. March 18, 2015 at 2:15 pm

    Tomi Engdahl says:

    Fine-pitch connectors fit smart phones, IoT devices
    http://www.edn.com/electronics-products/other/4438954/Fine-pitch-connectors-fit-smart-phones–IoT-devices?_mc=NL_EDN_EDT_EDN_today_20150318&cid=NL_EDN_EDT_EDN_today_20150318&elq=82c4f92d26024e7ba45a62bc9a2f4cb1&elqCampaignId=22122&elqaid=24850&elqat=1&elqTrackId=c5767b94b151470481e45a86cede58cc

    TE Connectivity has expanded its line of board-to-board connectors with three devices, including a 0.4-mm fine-pitch EMI-shielded board-to-FPC (flexible printed circuit) connector, a 0.4-mm pitch board-to-board connector, and a 0.35-mm pitch board-to-board connector with a locking peg design. These devices are designed to address manufacturers’ requirements for a super-slim, low-profile board-to-board connector for use in smart phones, Internet of Things devices, wearables, and other mobile devices.

    Reply
31. March 18, 2015 at 2:16 pm

    Tomi Engdahl says:

    High-speed comparator cuts delays to 2.9 ns
    http://www.edn.com/electronics-products/other/4438952/High-speed-comparator-cuts-delays-to-2-9-ns?_mc=NL_EDN_EDT_EDN_today_20150318&cid=NL_EDN_EDT_EDN_today_20150318&elq=82c4f92d26024e7ba45a62bc9a2f4cb1&elqCampaignId=22122&elqaid=24850&elqat=1&elqTrackId=9b2f3155d06a48b5a9ebdfa428ed6f00

    Intended to drive logic levels of 3.3 V down to 1.8 V, the LTC6752 comparator from Linear Technology achieves fast rise and fall times of 1.2 ns and a toggle frequency of 280 MHz, making it one of the fastest CMOS-output comparators on the market. The device exhibits a propagation delay of only 2.9 ns and overdrive dispersion of just 1.8 ns. Jitter is 4.5 ps for a 100-mV pk-pk, 100-MHz sinusoidal input, and the outputs swing to within 200-mV of the rails with up to 8 mA of load current.

    Reply
32. March 18, 2015 at 2:34 pm

    Tomi Engdahl says:

    A day may come when flash memory is USELESS. But today is not that day
    However sometime in the 2020s it will be. What then?
    http://www.theregister.co.uk/2015/03/18/the_future_of_solid_state_storage/

    The era of flash memory is anticipated to run out of road in the 2020s and newer technologies involving resistance and electron spin are poised to take over, delivering higher capacities, greater speed and DRAM-style addressability.

    Some people ask if one of these new technologies could actually unify dynamic memory (RAM) and non-volatile memories in a single universal memory tech.

    That seems far-fetched at the moment; just finding a working successor to NAND looks like achievement enough.

    Of the IT systems companies only IBM and HP are involved in fundamental research areas that have produced breakthroughs in the post-NAND area. The flash foundry operators, such as Samsung, Toshiba and Micron, are more interested in extending the life of NAND and their investment in NAND product processes than in replacing it with something else.

    They can’t ignore it, however. Micron has developed Phase-change memory (PCM) and has been manufacturing product until recently. Toshiba has looked into STT-RAM and Samsung has dabbled with STT-RAM as well.

    NAND flash memory is odd technology. It is non-volatile, of course, like tape and disk, but it is not byte-addressable. Unlike disk or tape it has to be written in blocks of bytes at a time, with each byte going into a cell.

    As NAND semi-conductor technology reaches the end of its process shrink road, with cells becoming progressively more error-prone and short-lived below 10nm in size, alternative post-NAND technologies are being examined to see if they can deliver the increased density (capacity) that is needed without carrying NAND’s disadvantages.

    Users will always want more capacity and more speed, and post-NAND technologies will be needed. Two or three years ago it was thought that the post-NAND future was going to arrive quickly but TLC (three-layer cell) and 3D NAND technology is pushing back the end of the NAND era to the 2020s.

    There are three main post-NAND development thrusts: phase-change memory (PCM), resistive RAM (RRAM) and spin transfer torque RAM (STT-RAM).

    At the moment it is apparent that no major flash foundry has yet put its weight behind a single post-NAND technology. That, in El Reg’s opinion, is because of two things.

    Firstly, no clear front-running technology has emerged, with PCM, RRAM and STT-RAM enjoying roughly equal status.

    They are concentrating on pushing NAND density higher through the 3D and TLC initiatives, while lowering latency by moving to NVMe, and possibly flashDIMM interfaces. They see no pressing need to develop anything else until closer to the 2020s.

    A respected consultant in this area, Jim Handy of Objective Analysis, says: “I see 2023 as the year that RRAM or some competing technology will displace flash or DRAM. Entrenched technologies will be with us for some time.

    “Until then, all the other technologies vying to replace DRAM and flash will be relegated to niches.”

    Niches but no riches for post-NAND tech startups, then, at least for the next eight years or so.

    Reply
33. March 19, 2015 at 8:30 am

    Tomi Engdahl says:

    New Part Day: SPI RAM and a Video Controller
    http://hackaday.com/2015/03/18/new-part-day-spi-ram-and-a-video-controller/

    Generating video signals with a microcontroller or old CPU is hard if you haven’t noticed. If you’re driving even a simple NTSC or PAL display at one bit per pixel, you’re looking at a minimum of around 64kB of RAM being used as a frame buffer. Most microcontrollers don’t have this much RAM on the chip, and the AVR video builds we’ve seen either have terrible color or relatively low resolution.

    Here’s something interesting that solves the memory problem and also generates analog video signals. Yes, such a chip exists, and apparently this has been in the works for a very long time. It’s the VLSI VS23s010C-L, and it has 131,072 bytes of SRAM and a video display controller that supports NTSC and PAL output.

    There are two chips in the family, one being an LQFP48 package, the other a tiny SMD 8-pin package.
    The larger LQFP package is where the action is

    Reply
34. March 19, 2015 at 8:40 am

    Tomi Engdahl says:

    Industrial equipment and systems sold in circles at an accelerating pace.

    IHS research institute in the region is the annual growth of 9.7 per cent. Growth is based on the recovery of the economies of different countries, which leads to, for example, investments in factory automation.

    Last year, industrial components sold about $ 40 billion.

    In 2018, the size of the market is expected to be $ 55.2 billion.

    Of all the industrial components of American companies bought last year by 30.5 percent. China is the second largest market in the world: there were sold 14 per cent of industrial components.

    Source: http://www.etn.fi/index.php?option=com_content&view=article&id=2572:teollisuuspiireissa-hyvaa-kasvua&catid=13&Itemid=101

    Reply
35. March 19, 2015 at 11:34 am

    Tomi Engdahl says:

    Serial flash devices boast fast erase time
    http://www.edn.com/electronics-products/other/4438911/Serial-flash-devices-boast-fast-erase-time?_mc=NL_EDN_EDT_EDN_systemsdesign_20150318&cid=NL_EDN_EDT_EDN_systemsdesign_20150318&elq=e98b167a64944ea58dd219e59e5cb716&elqCampaignId=22127&elqaid=24855&elqat=1&elqTrackId=d5ac09f1d30d4184b93d5ed50cafcf64

    According to Microchip Technology, the SST26VF series of 3-V Serial Quad I/O (SQI) CMOS SuperFlash memory devices provides the fastest erase times in the industry, minimizing the time required for testing and performing firmware updates. Sector and block erase commands are completed in just 18 ms, and a full chip-erase operation is completed in 35 ms. Competing devices require 10 to 20 seconds to complete a full chip erase, making the SST26VF approximately 400 times faster.

    Reply
36. March 19, 2015 at 1:32 pm

    Tomi Engdahl says:

    Full-Duplex Radio Integrated Circuit Could Double Radio Frequency Data Capacity
    http://tech.slashdot.org/story/15/03/18/1733245/full-duplex-radio-integrated-circuit-could-double-radio-frequency-data-capacity

    Full-duplex radio communication usually involves transmitters and receivers operating at different frequencies. Simultaneous transmission and reception on the same frequency is the Holy Grail for researchers, but has proved difficult to achieve.

    Full-duplex radio integrated circuit could double radio frequency data capacity
    http://www.gizmag.com/full-duplex-wireless-radio-integrated-circuit/36580/

    Simultaneous transmission and reception on the same frequency is the Holy Grail for researchers, but has proved difficult to achieve. Those that have been built have proven complex and bulky, but to be commercially useful in the ever-shrinking world of communications technology, miniaturization is key. To this end, engineers at Columbia University (CU) claim to have created a world-first, full-duplex radio transceiver, all on one miniature integrated circuit.

    Implemented at the nanoscale on a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit (IC), the new device from the CU team enables simultaneous wireless radio transmission and reception at the same frequency. Dubbed CoSMIC – for Columbia high-Speed and Mm-wave IC – the team believes that its transceiver could help revolutionize mobile communications technology.

    “This is a game-changer,” said Associate Professor Harish Krishnaswamy of CU’s Fu Foundation school of Engineering and Applied Science. “By leveraging our new technology, networks can effectively double the frequency spectrum resources available for devices like smartphones and tablets.”

    To achieve this reported full-duplex capability, the team needed first to cancel out the transmitter’s echo on the frequency so that the minute “whisper” of the received signal could be heard.

    “Transmitter echo or ‘self-interference’ cancellation has been a fundamental challenge, especially when performed in a tiny nanoscale IC, and we have found a way to solve that challenge.”

    The researchers are not actually the first to produce a full-duplex radio system, nor are they the first to use the analogy of the whisperer/shouter. Stanford University produced a system using ostensibly similar techniques, and explained its system using exactly the same premise as the Columbia team.

    However, what Columbia is first at is the miniaturization of the full-duplex transceiver onto an integrated circuit.

    “Our work is the first to demonstrate an IC that can receive and transmit simultaneously,”

    New Technology May Double Radio Frequency Data Capacity
    http://www.engineering.columbia.edu/new-technology-may-double-radio-frequency-data-capacity-0

    So the ability to have a transmitter and receiver re-use the same frequency has the potential to immediately double the data capacity of today’s networks. Krishnaswamy notes that other research groups and startup companies have demonstrated the theoretical feasibility of simultaneous transmission and reception at the same frequency, but no one has yet been able to build tiny nanoscale ICs with this capability.

    “Our work is the first to demonstrate an IC that can receive and transmit simultaneously,” he says. “Doing this in an IC is critical if we are to have widespread impact and bring this functionality to handheld devices such as cellular handsets, mobile devices such as tablets for WiFi, and in cellular and WiFi base stations to support full duplex communications.”

    The biggest challenge the team faced with full duplex was canceling the transmitter’s echo. Imagine that you are trying to listen to someone whisper from far away while at the same time someone else is yelling while standing next to you. If you can cancel the echo of the person yelling, you can hear the other person whispering.

    This work was funded by the DARPA RF-FPGA program.

    Comments from http://tech.slashdot.org/story/15/03/18/1733245/full-duplex-radio-integrated-circuit-could-double-radio-frequency-data-capacity

    The article is misleading. Transmission and reception on the same “frequency” is done today. However, there’s some other “discriminator” in the signal. Either modulation method, phase, shift, orientation, or “something” is different so that the receive and transmit don’t collide.

    This article — despite its misleading introduction — talks about a limited application whereby RX and TX can occur using the same frequency *BAND* (they say “spread spectrum”) and allow full-duplex communication. The advance is that this is all on one chip.

    What would be truly revolutionary, like the example of two people talking to each other at the same time, is the ability to transmit and receive using the *same* exact method by both transceivers. THAT would be the holy grail.

    Not there yet.

    The issue is that a strong transmission in the same band as a receiver can desense the receiver. This can also be done with a cavity duplexer if you need input and output in the same band on adjacent frequencies, but you pay for it with geometric space (since cavity duplexer dimensions are a fraction of the wavelength in free space multiplied by the materials velocity factor). This can be problematic on HF and VHF bands, but UHF and microwave can get away with duplexers the size of a brick. Unfortunately, that’s still too much for mobile phones since it’s too big to fit in someone’s pocket.

    Hi all, I was perusing through all the comments, and as one of the authors of the work, I thought I would clarify some of the points that were raised to aid the discussion:
    1. The chip targets same-channel full duplex, meaning the transmitter and the receiver work in the same frequency channel at the same time, and are not separated by polarization, modulation format etc. Therefore, since transmitted signals are around +20dBm and receiver sensitivity levels are around -90dBm, nearly 110dB of suppression through isolation (across a pair of antennas or a circulator) and echo (aka self-interference or SI) cancellation must be achieved (as one of the people above has correctly pointed out). Such a high degree of SI cancellation requires that SI cancellers be implemented in all domains (RF, analog and digital, each yielding a part of the total SI suppression).
    2. As one of the people above has pointed out, even if the signals were separated in modulation format for instance, the transmitter SI would be so powerful that it would saturate the receiver front end before modulation-format-based separation can be achieved in the digital domain. So echo cancellation at the receiver front end is required.
    3. As someone points out, circulators and echo cancellers have existed for quite a while and have been implemented in many ways. The innovation here is that we perform echo or SI cancellation at RF in a single chip, which has not been done before.
    4. Moreover, the SI cancellation approach can tackle echos that experience significant delay (as high as 20ns) while still fitting with an IC form factor through the use of on-chip reconfigurable high-Q filters, enabling cancellation of wideband signals (>20MHz enabling use for WiFi).
    5. Finally, indeed the varying environment is a challenge and the RF and digital SI cancellers need to be reconfigured periodically (milli-seconds).
    Hope this helps.

    Some more clarifications:
    6. The chip has been fully tested, and is able to provide the required SI cancellation so that the desired signal can be received without distortion in the presence of the powerful transmitter echo. What remains to be tested are rate gains when several of these chips are networked. This is not that straightforward because today’s networks are designed for half-duplex nodes, not full-duplex. So new scheduling concepts etc. need to be developed, which is a topic of research.
    7. Echo cancellation is certainly not old technology. While echo cancellation techniques exist, they use techniques that cannot be integrated into an IC (e.g. cm-long transmission lines to replicate 10s of nanoseconds of delay spread, photonic techniques etc.). The innovation here is a technique that can replicate the delay spreads of the echo at RF frequencies on an IC.

    Reply
37. March 23, 2015 at 9:54 am

    Tomi Engdahl says:

    FinFET impact on dynamic power
    http://www.edn.com/electronics-blogs/eda-power-up/4438874/FinFET-impact-on-dynamic-power?_mc=NL_EDN_EDT_EDN_today_20150319&cid=NL_EDN_EDT_EDN_today_20150319&elq=24d90c098d1e4244abe788aa1421edaf&elqCampaignId=22166&elqaid=24900&elqat=1&elqTrackId=03a02472037845c1b24d8c53fdca5d60

    FinFET transistors are now in production at the major foundries, having gone from drawing board to products on the shelf in record time. FinFET adoption has been growing steadily because they deliver better power, performance, and area compared to their planar counterparts. This makes them very compelling for smartphones, tablets, and other products that require long battery life and snappy performance.

    When Intel first used FinFETs at the 22nm node, they claimed 37% better performance (at the same total power) or 50% power reduction (at the same speed) than bulk, PDSOI, or FDSOI. These numbers are compelling, and continue to improve even down to 14nm, and presumably, beyond.

    In terms of power usage, controlling power leakage has been a huge challenge for planar devices, especially at smaller nodes. By raising the channel and wrapping the gate around it, finFETs create a fully depleted channel to overcome the leakage problems of planar transistors. The better channel control of FinFETs leads to lower threshold and supply voltages.

    While leakage is under control in FinFETs, dynamic power consumption accounts for a significant chunk of the total power. FinFETs have higher pin capacitances compared to planar transistors, which results in higher dynamic power numbers. According to Cavium networks “FinFETs bring a 66 percent increase in gate capacitance per micron compared to 28 nm process, and at the same level of the 130-nm planar node.” Figure 2 charts the gate capacitances of planar and FinFET devices.

    Reply
38. March 23, 2015 at 10:56 am

    Tomi Engdahl says:

    Optical Color Shifter Computes Cognitively
    http://www.eetimes.com/document.asp?doc_id=1326093&

    A new era of all-optical computers that use the neural network paradigm and have fast, cheap memory could result from switching optical materials to chalcogenides, which darken in color as light passes threw them.

    Research on Chalcogenides is underway in a collaboration between professor Dan Hewak from the Optoelectronics Research Centre (ORC) at the University of Southampton, U.K. and professor Cesare Sci at the Centre for Disruptive Photonic Technologies (CDPT) at the Nanyang Technological University (NTU) in Singapore. Hewak told EE Times:

    Chalcogenides are highly light sensitive materials which respond to light in many different ways. In our neural network experiments, we exploit the photodarkening process, in which chalcogenides become absorbers of photons when exposed to light. The glasses ‘remember’ how much light they are been exposed to, and depending on the wavelength of the light, this memory can be temporary or permanent. Also, they can respond equally to weak light, exposed for a long time, or intense light for a short time.

    Reply
39. March 23, 2015 at 11:00 am

    Tomi Engdahl says:

    Industrial IoT Drives Microsemi-Vitesse Merger
    MIPS vs. ARM conflict on horizon
    http://www.eetimes.com/document.asp?doc_id=1326074

    In a sign that the rash of M&As among chip vendors has yet to subside, Microsemi Corp. announced Wednesday (March 18) its acquisition of Vitesse Semiconductor Corp. for $389 million.

    The merger’s focus is “communications semiconductors,” with plans to direct the combined company at “carrier, enterprise and industrial Internet of Things markets,” according to Microsemi’s statements.

    While the two insisted that they play in complementary fields, technically speaking, a MIPS vs. ARM conflict is on the horizon. It’s unclear how the new company will handle its separate processor cores – Vitesse’ product family is based on Imagination Technologies’ MIPS core and Microsemi’s product line is based on ARM’s Cortex M microcontroller core.

    Microsemi (Aliso Viejo, Calif.) is known as a chip supplier for military and commercial satellites and aircraft, wireless and wired LAN systems, oilfield equipment, and airport security systems. Microsemi CEO James Peterson explained what drove the deal was Microsemi’s “continuing commitment to grow as a communications semiconductor company.”

    Vitesse, a self-styled “Ethernet Everywhere” company, designs, develops, and markets chips for carrier and enterprise networking applications worldwide. In particular, Vitesse offers carrier Ethernet switch engines, including mobile access equipment, such as base stations, small cells, fiber and microwave wireless backhaul products.

    Reply
40. March 23, 2015 at 12:30 pm

    Tomi Engdahl says:

    LED penetration 10-20 percent

    LED power slowly, but surely, the lighting market. Yole Developpement Research Institute, the LEDs lighting the proportion varies in different countries, usually 10 to 20 percent.

    LED penetration has depended largely on decisions of the authorities. For example, in Japan the LEDs light bulbs are accounted for 30 per cent, because the state has supported the LED lamps significantly.

    LED lighting market will grow this year, according to forecasts of more than USD 25 billion. The lighting of the total size of the market will grow to more than 81 billion US dollars, so the LEDs accounted for about one-third.

    Sold in China this year, a fifth of all LED lamps.

    Source: http://www.etn.fi/index.php?option=com_content&view=article&id=2578:ledipenetraatio-10-20-prosenttia&catid=13&Itemid=101

    Reply
41. March 23, 2015 at 1:00 pm

    Tomi Engdahl says:

    A true op-amp made from inverters
    http://www.edn.com/design/analog/4424461/A-true-op-amp-made-from-inverters?_mc=NL_EDN_EDT_EDN_analog_20150319&cid=NL_EDN_EDT_EDN_analog_20150319&elq=2d30312fc3324662b36d223bcf9313e7&elqCampaignId=22151&elqaid=24881&elqat=1&elqTrackId=14cb02e9e36748968cd5858a3011125e

    Ever-increasing demand for smaller, more efficient CPUs has driven CMOS fabrication deep into the nanometer scale. The supply scaling and device leakage of these fine processes adversely affects precision analog circuits, leading researchers to find highly-digital alternative architectures for traditionally analog-intensive functions [1, 2]. This “digitization” of the analog domain will eventually trickle down to the home hobbyist, who will face increasing difficulty finding simple analog components.

    Figure 1 shows the complete implementation of a two-stage op-amp using only four CD4049UBE [4] hex inverters, a resistor, and a capacitor.

    The inverters in U1 behave as a gm-doubled differential pair. Since the first stage only has between 25dB & 30dB of gain, a second stage is added

    This design should work equally well with CD4069UB as well as 74HCU04 devices,

    Reply
42. March 24, 2015 at 8:06 am

    Tomi Engdahl says:

    Bringing Sub-Threshold Voltage to Any MCU
    Applying subthreshold voltage technology to real-time clocks changes the MCU power equation
    http://www.eetimes.com/document.asp?doc_id=1326107&

    A basic hardware building block in any embedded developer’s repertoire of low power design aids is the lowly real-time clock (RTC). In its simplest form, the function of an RTC is to keep track of the current time. But the RTC has taken on a pivotal role as the means by which to monitor and manage sparse power resources in almost any untethered embedded or Internet of Things design.

    So it should come as no surprise that almost every maker of microprocessors and microcontrollers also provides at least one RTC circuit in its catalog of products, including most of the major makers of ARM-based processors and SoCs, including NXP Semiconductor, Silicon Labs, and ST Microelectronics. The reason is simple: developers still have to deal with the power requirements of the rest of the components in a design.

    Ambiq Micro has addressed this challenge by using the Subthreshold Power Optimized Technology (SPOT) used in its Apollo family of ARM Cortex-M4F MCUs to also fabricate its AM08XX/18XX real time clock family (Figure 1), now in volume production.

    “The RTCs we have built allow the design of systems that are roughly seven times lower in power than the NXP PCS 2123 RTC, and at least 10 times lower than similar devices from Integrated Device Technology, Maxim, and STMicroelectronics,”

    And because they are processor agnostic, Ambiq’s RTCs can reduce the power consumption of any embedded system design based on any processor, including high end ARM, MIPS, and Intel Atom-based 32- or 64-bit CPUs as well as any 8- or 16-bit microcontroller.

    If these claims are proven in working designs, the near-term impact of Ambiq’s RTC family is more far-reaching than the use of its subthreshold voltage technology in 32-bit processor designs.

    The shift to threshold voltage-based RTCs will make any 32-bit MCU more viable in power constrained IoT designs. But at the same time, it will make already low power 8- and 16-bit MCUs even more so, considerably extending their operational life, especially in applications that require unattended operation over months or years using only batteries or energy harvesting. The AM08XX/18XX devices achieve this power savings in a number of ways, Salas said.

    “Despite the fact that they play a key role in managing MCU design power resources, traditional RTCs are incredibly power-hungry,”

    The most common use of an Ambiq RTC is to manage the VCC power switch that completely turns off the MCU and/or other system elements. But to provide the MCU system designer additional flexibility, Ambiq’s RTCs can also be reset- or interrupt-driven.

    “In energy harvesting designs, which often use a rechargeable battery or a super-capacitor to store energy for later use, our RTCs’ trickle charge feature would allow collection of energy at much lower voltage and current levels, as well as manage the storage of such resources, and when to use them.”

    Reply
43. March 24, 2015 at 8:06 am

    Tomi Engdahl says:

    Apple A9 Orders Pivot to TSMC
    Samsung’s yield issues may have caused the shift
    http://www.eetimes.com/document.asp?doc_id=1326110&

    AIPEI — Taiwan Semiconductor Manufacturing Co. (TSMC), the world’s largest chip foundry, will snatch more orders for Apple’s A9 processor at the expense of Samsung, which is having yield problems with its most advanced technology node, according to sources interviewed by EE Times.

    Apple is ramping production of the A9 this year for the iPhone 6S, according to the sources. Apple, the world’s biggest company by market capitalization, originally handed Samsung about 80% of the A9 orders and the rest to TSMC, the sources say. Now the tables appear to have turned.

    “We believe TSMC will get 40% of the next iPhone processors, in addition to all the next iPad processors,” said Mark Li, senior analyst with Bernstein, in a March 20 report. TSMC will get about 70% of Apple’s overall business starting in the third quarter of 2015, the report stated.

    Reply
44. March 24, 2015 at 8:07 am

    Tomi Engdahl says:

    The EE Times 2014 Salary and Opinion Study
    http://www.eetimes.com/document.asp?doc_id=1326104&

    Reply
45. March 24, 2015 at 11:10 am

    Tomi Engdahl says:

    Secure Microprocessors the Andes Way
    https://www.semiwiki.com/forum/content/4108-secure-microprocessors-andes-way.html

    Microprocessor vendors such as Andes have been saying for some time that security requires extensive hardware support. In particular, embedded processors in intelligent sensors inside IoT chips are now popular targets for hackers, who find it easy to change the program code and system parameters to alter the operation of the sensor or to use the system for their own purposes. Every time a major breach occurs, like the recent infiltration of Sony, the message that security cannot be left in software only becomes stronger.

    There are different levels of hardware support for security. At the lowest level, the encryption keys need to be kept in hardware and the access carefully controlled. But there are a lot of other more subtle ways to attack a microprocessor-based system.

    One point of vulnerability to hackers in an embedded system is the JTAG interface. An attacker able to put the system into debug mode has complete control of the system with complete access to the CPU’s registers, program memory and another memory in the system. To provide protection of embedded software and program data while keeping the debugging capability, Andes secure debugging feature requires pass code validation.

    Anyone attempting to access the JTAG interface must provide the stored code.

    Another point of vulnerability in an embedded system is the memory interface brought out to the pins on the packaged part to access external memory. By probing the interface pins with a logic analyzer, attackers can capture all the traffic passing between external memory and the embedded CPU. To secure the memory interface, the Andes secure MPU scrambles the data and/or address thus displaying random information to a logic analyzer probe and making it impossible to copy the memory contents without the encryption key.

    A third technique used to hack into embedded designs is differential power analysis. This is a technique developed by Cryptography Research and works by looking at the power consumption of the system cycle-by-cycle and by looking at small differences in repetitive operations (such as DES encryption) to try and deduce, for example, the key. It is especially important to protect against in smart cards

    Of course security is a sort of war in which the attacks never get weaker.

    Reply
46. March 24, 2015 at 11:12 am

    Tomi Engdahl says:

    High-speed comparator cuts delays to 2.9 ns
    http://www.edn.com/electronics-products/other/4438952/High-speed-comparator-cuts-delays-to-2-9-ns?_mc=NL_EDN_EDT_EDN_productsandtools_20150323&cid=NL_EDN_EDT_EDN_productsandtools_20150323&elq=dd54b1ef616a4560a2bdd826e4363a0a&elqCampaignId=22209&elqaid=24946&elqat=1&elqTrackId=12befe8857ed4522884a981ce0fe0ad4

    Intended to drive logic levels of 3.3 V down to 1.8 V, the LTC6752 comparator from Linear Technology achieves fast rise and fall times of 1.2 ns and a toggle frequency of 280 MHz, making it one of the fastest CMOS-output comparators on the market.

    The device exhibits a propagation delay of only 2.9 ns and overdrive dispersion of just 1.8 ns. Jitter is 4.5 ps for a 100-mV pk-pk, 100-MHz sinusoidal input, and the outputs swing to within 200-mV of the rails with up to 8 mA of load current.

    Reply
47. March 24, 2015 at 11:42 am

    Tomi Engdahl says:

    Philips has always been the pride of the Netherlands, a bit like the Nokia once Finland. Now the company will divest the business, which it eventually founded 124 years ago. Philips Lumileds lighting company are exported to the stock exchange.

    Gerard Philips founded the company in 1891 to produce new wonderful lighting fixtures or light bulbs.

    The company grew a hundred years, a giant conglomerate, which in 2006 released the NXP semiconductors your company.

    Since 2008, Philips has been divided into health boards will (Philips Heathtcare), consumer electronics and lighting solutions (Philips Lighting).

    Philips’ long-term goal is to give up the lighting business altogether. At the initial stage it will maintain the share of Lumileds shares.

    Source: http://www.etn.fi/index.php?option=com_content&view=article&id=2588:philips-luopuu-alkuperaisesta-toiminnastaan&catid=13&Itemid=101

    Reply
48. March 24, 2015 at 11:43 am

    Tomi Engdahl says:

    District, housing and a card with the same tools

    EDA house Mentor Graphics has introduced a design environment where the same tools can be designed as a circuit, enclosure as circuit boards. Xpedition Package intergrator takes the design optimization of a magnitude beyond.

    Source: http://www.etn.fi/index.php?option=com_content&view=article&id=2591:piiri-kotelo-ja-kortti-samoilla-tyokaluilla&catid=13&Itemid=101

    Reply
49. March 24, 2015 at 11:46 am

    Tomi Engdahl says:

    Linear Technology has introduced a new family of regulators of compressed micro-assembly, where for the first time in the micro size inductor is planted inside the module.
    LTM8055- and LTM8056-regulators inductor is inside the module promise to make design easy.
    The modules facilitate the design of the power supply voltages up to 60 volts and up to about 70 watts.

    LTM8055 – 36VIN, 8.5A Buck-Boost μModule Regulator
    Complete Buck-Boost Switch Mode Power Supply
    VOUT Equal, Greater, Less Than VIN
    Wide Input Voltage Range: 5V to 36V
    12V/3A Output from 6VIN
    12V/6A Output from 12VIN
    12V/8.5A Output from 24VIN
    Up to 97.5% Efficient
    Adjustable Input and Output Average Current Limits

    Sources:
    http://www.etn.fi/index.php?option=com_content&view=article&id=2592:linear-istutti-induktorin-mikroregulaattoriin&catid=60&Itemid=101
    http://www.linear.com/product/LTM8055

    Reply
50. March 24, 2015 at 11:49 am

    Tomi Engdahl says:

    Murata include Analog Devices, Infineon and Honeuwellin join us with a mems business moving at about US $ 200 million range. It has a long way to the market leader in sales of Bosch, which last year exceeded $ 1.2 billion mark.

    At present, the success of the MEMS market is divided into three camps depending on the application areas of the company plays. Inkjet printer head sales are shrinking steadily. Car Electronics sales remain quite at the same level. The fastest growth will enjoy a variety of motion sensors for smartphones and other mobile devices to develop. For example, the Bosch for sales growth last year, largely based on the design of Apple’s new iPhone to victory in 6 models.

    Source: http://www.etn.fi/index.php?option=com_content&view=article&id=2593:entinen-vti-pitaa-paikkansa&catid=13&Itemid=101

    Reply