Electronics trends for 2015

Chip designs that enable everything from a 6 Gbit/s smartphone interface to the world’s smallest SRAM cell will be described at the International Solid State Circuits Conference (ISSCC) in February 2015. Intel will describe a Xeon processor packing 5.56 billion transistors, and AMD will disclose an integrated processor sporting a new x86 core, according to a just-released preview of the event. The annual ISSCC covers the waterfront of chip designs that enable faster speeds, longer battery life, more performance, more memory, and interesting new capabilities. There will be many presentations on first designs made in 16 and 14 nm FinFET processes at IBM, Samsung, and TSMC.

There is push to go to even smaller processes, and it seems that next generation of lithography equipment are started to being used. Earlier expectation was for chipmakers to use traditional immersion lithography for production of 10 nm chip, but it seems that extreme ultraviolet (EUV) scanners that allows allow scaling to 10 nm or even smaller is being used. TSMC to Use EUV for 7nm, Says ASML. Intel and TSMC have been injecting money in ASML to push process technology.

2015 promises to see initial FPGA product releases and (no doubt) a deluge of marketing claims and counter-claims. One thing is certain: 2015 will not be boring. There will be FPGA products that use processes beyond 20nm, for example Altera and  Xilinx have committed to use the TSMC 16nm FinFET technology. There is  publicized (and rumored) race to get to production at 14nm has seen time frames for initial samples move into 2015. However, with both FPGA companies reporting gross margins of close to 70 percent, it would be possible for either company to take an initial hit on margin to gain key socket wins.

It seems that the hardware becomes hot again as Wearables make hardware the new software. Apple invest its time when it released the Apple Watch last quarter, going up against the likes of Google’s Android Wear and others in the burgeoning wearables area of design. Once Apple’s bitten into a market, it’s somewhat a given that there’s good growth ahead and that the market is, indeed, stable enough. As we turn to 2015 and beyond  wearables becomes an explosive hardware design opportunity — one that is closely tied to both consumer and healthcare markets. It could pick up steam in the way software did during the smartphone app explosion.

There will be more start-up activity within hardware sector. For recent years, the software has been on the main focus on the start-ups, and the hardware sector activity has been lower. Hardware sector has seem some start-up activity with many easy to use open hardware platforms became available (make development of complex devices easier and reachable for smaller companies). The group financing (Kickstarter, Indiegogo, etc.) have made it possible to test of new hardware ideas are market-worthy and get finance to get them to production.

EEs embrace hackathons aand accelerators. Design 2.0 is bubbling up in the engineering community, injecting new energy into the profession. In many ways, it’s the new Moore’s Law. Easy to use open hardware development platforms have made it possible to design working hardware device prototypes within hackathons.

Silicon Startups Get Incubator article tells that there will be new IC start-up activity as semiconductor veterans announced plans for an incubator dedicated to helping chip startups design their first prototypes. Keysight, Synopsys, and TSMC have signed exclusive deals to provide tools and services to the incubator. Silicon Catalyst aims to select its first batch of about 10 chip startups before April.

1,206 Comments

1. March 25, 2015 at 10:43 am

   Tomi Engdahl says:

   Popov makes early radio transmission, March 24, 1896
   http://www.edn.com/electronics-blogs/edn-moments/4429598/Popov-makes-early-radio-transmission–March-24–1896?_mc=NL_EDN_EDT_EDN_today_20150324&cid=NL_EDN_EDT_EDN_today_20150324&elq=8cb72af89e1f4f41ba1a4f5f7ed00bc4&elqCampaignId=22218&elqaid=24955&elqat=1&elqTrackId=72af1df67c174ab5ace8f617b86f4806

   Alexander Popov’s place in radio history is often overlooked.

   Popov set out to achieve that goal, and on March 24, 1896, he claimed to transmit the words “Heinrich Hertz” between buildings on the St Petersburg University campus. However, reports of his achievement weren’t published until years later as he was working for the Navy and his research was not intended for public knowledge.

   The Russians tested his radio system communicating with a ship that had run aground in 1900 and began adopting it for naval use.

   Guglielmo Marconi is often credited with the invention of the radio, which he patented in 1896, and Tesla demonstrated the fundamentals of radio in 1893, but the Soviet government made May 7 “Radio Day” and named Popov a national hero for his contributions to the field.

   Reply
2. March 25, 2015 at 10:48 am

   Tomi Engdahl says:

   Multicore comes to IoT connectivity and audio applications
   http://www.edn.com/electronics-products/other/4439003/Multicore-comes-to-IoT-connectivity-and-audio-applications?_mc=NL_EDN_EDT_EDN_today_20150324&cid=NL_EDN_EDT_EDN_today_20150324&elq=8cb72af89e1f4f41ba1a4f5f7ed00bc4&elqCampaignId=22218&elqaid=24955&elqat=1&elqTrackId=e3e7b74cad0f4beca9c396cb1c07c41e

   XMOS has released next-generation products based on its xCore multiprocessor architecture that the company says have twice the performance and up to four times the memory of earlier generations. The xCore-200 family targets connectivity for the Internet of Things (IoT) while the xCore-Audio family targets professional and high-end consumer applications. Both promise low cost.

   The xCore-200 family will provide 8- to 32-core configurations in a dual-issue pipeline architecture that supports a high degree of parallelism in code execution. The initial device in the family offers 16 32-bit cores, 512kBytes of SRAM, and up to 2Mbytes of Flash along with a flexible 10/100/1000 Gigabit Ethernet interface, including programmable MAC and RGMII PHY. A programmable 480 Mbps USB 2.0 interface with PHY is also included. Other peripherals can be implemented using configurable port logic, with protocols implemented in software.

   Reply
3. March 25, 2015 at 1:31 pm

   Tomi Engdahl says:

   Breakthrough chip research brings faster and cheaper semiconductors
   Stanford University researchers find new way to reduce gallium arsenide manufacturing costs
   http://www.theinquirer.net/inquirer/news/2401351/breakthrough-chip-research-brings-faster-and-cheaper-semiconductors

   RESEARCHERS HAVE UNCOVERED a way to make faster and more efficient chips while saving on manufacturing costs.

   The new semiconductor technology was developed by Stanford University, and uses gallium arsenide as opposed to silicon.

   It can handle data at higher speeds, or high-frequency radio signals, because the material allows electrons to move through it up to six times faster.

   Silicon has traditionally been used as a semiconductor material, despite the technical advantages of gallium arsenide, as it’s around 1,000 times cheaper to produce.

   Silicon and gallium arsenide are developed from raw crystal and are used in electronic devices in the same way, each material being fashioned into what electronics manufacturers call ‘wafers’.

   It can cost about $5,000 to make an 8in gallium arsenide wafer, compared with just $5 for a same-sized silicon wafer.

   To make the wafer reusable the Stanford process adds several steps to the manufacturing process.

   Aneesh Nainani, who teaches semiconductor manufacturing at Stanford, said that this reuse could create gallium arsenide devices that would be 50 to 100 times more expensive than silicon circuits. That’s still a big difference compared with the super-cheap silicon process, but it’s much less than the current difference.

   “Silicon is inexpensive today because, over time, the electronics industry has focused all its ingenuity on making silicon cheaper”

   “And with each advance, more uses will open up, especially in solar energy generation where gallium arsenide has clear efficiency advantages.”

   Reply
4. March 26, 2015 at 9:24 am

   Tomi Engdahl says:

   Tektronix Returns to the High-speed Oscilloscope Game
   http://www.eetimes.com/document.asp?doc_id=1326117&

   With the introduction of the DPO70000SX series at OFC 2015, Tektronix has jumped back into the game at the top end of real-time oscilloscopes, taking over second place.

   At 70 GHz, the DPO70000SX surpasses Keysight’s 63 GHz 96204Q Infiniium Oscilloscope and Teledyne LeCroy’s 65 GHz Wavemaster 10 Zi. Teledyne LeCroy’s 100 GHz Wavemaster 10-100Zi oscilloscope still holds the lead.

   Reply
5. March 26, 2015 at 9:26 am

   Tomi Engdahl says:

   EUV Makes Headway At Last
   http://www.eetimes.com/author.asp?section_id=36&doc_id=1326103&

   Research on extreme ultraviolet (EUV) lithography is making real progress, encouraging semiconductor makers to reconsider their road maps.

   What struck me at the SPIE Advanced Lithography conference in February was the progress in EUV lithography, which left me more optimistic than last year. After some years of very slow progress with the throughput and source power of the EUV scanners, we are seeing a sudden breakthrough that changed the outlook of many attendants.

   TSMC was the source of the optimism. It’s engineers reported they exposed 1,000 wafers in 24 hours on an ASML NXE:3300B equipped with an 80W light source. This is a watershed advance compared to last year, when even reaching a 10W power level seemed challenging.

   TSMC has set up a pre-production experiment. Clearly, they have positioned themselves as a pioneer in EUV, with an ambition to insert EUV in N7 high-volume production, and retrofit it into N10 production. Seeing the advances with the power, that seems possible. However, the EUV scanners still need to improve their average uptime.

   Reply
6. March 26, 2015 at 9:28 am

   Tomi Engdahl says:

   Manufacturing Industry Short on Tech Talent
   http://www.eetimes.com/author.asp?section_id=36&doc_id=1326120&

   Manufacturing in the US is trying to rebound, but a shortage of technical talent may impede progress.

   America’s aging manufacturing base may finally be on the rebound, but it still faces an unexpected dilemma — lack of trained technical people to carry out the work.

   The problem is so acute that many OEMs openly recruit trained technical workers from suppliers, in some cases paying penalties for doing so.

   Reply
7. March 26, 2015 at 9:31 am

   Tomi Engdahl says:

   News & Analysis
   MCU Vendors Engaging in Low-Power Leapfrog
   http://www.eetimes.com/document.asp?doc_id=1326124&

   A series of recent announcements underscores a trend in the microcontroller industry to pursue the growing market for battery-powered and mobile devices, particularly those destined to be part of the Internet of Things (IoT). Using the EEMBC ULPBench power benchmark, introduced last year, MCU vendors have become engaged in a game of leapfrog, announcing new products with ever-improving benchmark results and (temporarily) claiming leadership in ultra-low power processing.

   While this may seem like a marketing game, developers will ultimately be the winners as vendors refine their techniques for saving power.

   In the past, a low powered MCU also meant low performance, but vendors have been challenging this correlation by offering increasingly powerful MCUs for low-power applications. Developers, however, faced a problem in evaluating these offerings. Traditional specifications such as operating current in mW/MHz and sleep-mode leakage currents became increasingly difficult to evaluate in the face of the multiple power states that devices offered, and in the face of inconsistency in the industry in the descriptions and specifications used to characterize low-power operation.

   Reply
8. March 26, 2015 at 11:52 am

   Tomi Engdahl says:

   Flash chips manufacturers are looking for more storage capacity of 3D structures, which are made ​​by stacking layers. Toshiba’s latest memory is 48 floors, which is a new industry record.

   Toshiba has received the BICS memory (three dimensional stacked cell structure of flash memory) 128-gigabit storage capacity. Stored in the memory of two bits in each cell. Tacking makes the memory write and erase process more reliable and faster. BICS is particularly useful, for example, SSD memory circuits.

   Source: http://www.etn.fi/index.php?option=com_content&view=article&id=2604:3d-muisti-sai-lisaa-kerroksia&catid=13&Itemid=101

   Reply
9. March 26, 2015 at 12:37 pm

   Tomi Engdahl says:

   Improving analog design verification using UVM
   http://www.edn.com/electronics-blogs/formal-design—verification/4439002/Improving-analog-design-verification-using-UVM?_mc=NL_EDN_EDT_EDN_analog_20150326&cid=NL_EDN_EDT_EDN_analog_20150326&elq=ee2178f3a4b74161b414f6f951b29e36&elqCampaignId=22255&elqaid=25002&elqat=1&elqTrackId=2ec597a40ab2485ead09f704169de7d4

   As technology becomes more integrated into our everyday life, our chips need to better communicate with the analog world. Most modern system on chip (SoC) designs therefore contain analog and mixed-signal (AMS) elements integrated with digital components. According to Sandip Ray of Intel, AMS elements currently consume about 40% of the design effort, and an estimated 50% of errors in recent chips that require a redesign are due to bugs in the AMS portion of the design [1].

   This increase in AMS content in silicon creates several verification challenges: how do we verify the analog design itself, its integration with the digital, and whether the combination achieves the intended overall function? However, there is no standard or even widely adopted approach to this despite the continuous increase in analog content. One potential route is via an efficient, reusable AMS verification approach using the Universal Verification Methodology (UVM)

   This approach to verification is multi-layered:

   1. We must verify the analog IP design itself using traditional SPICE simulations

   2. We must verify the integration of the analog with the digital:
   i) At block level
   ii) And at SoC level

   3. Verification of the accuracy of the model

   So, we are able to bring the full power of UVM to a test bench that mixes digital design with models of the analog parts of the chip.

   Reply
10. March 26, 2015 at 12:41 pm

    Tomi Engdahl says:

    Engineering correct-by-design PCBs
    http://www.edn.com/design/pc-board/4439023/Engineering-correct-by-design-PCBs?_mc=NL_EDN_EDT_EDN_analog_20150326&cid=NL_EDN_EDT_EDN_analog_20150326&elq=ee2178f3a4b74161b414f6f951b29e36&elqCampaignId=22255&elqaid=25002&elqat=1&elqTrackId=5726727c6d6f43aca22bd02cedd36eab

    As both chip and board complexities continue to spiral upwards, so do the number of challenges faced by designers. The proliferation of multi-Gbps differential signals, for example, brings with it the need for tightly length-matched routing and restrictions on the use of vias. Extensive simulation to characterize these busses, including long bit streams to validate performance down to very low bit error rate (BER levels), is necessary to ensure adequate system margins. This requirement is no longer unique to high-speed serial links, but has now spread to single-ended, parallel links like DDR4. PCBs have to be tested for signal integrity, power integrity, and radiated emissions, in order to ensure that the design works correctly before the first prototype is even built.

    As such, designing a modern, high-speed PCB is a pretty daunting task. It requires high levels of expertise in a number of different areas. Infusing that expertise into the design process, however, can be made more practical through the use of rules-based verification.

    Concurrent Verification During Layout
    Every design requires that a set of constraints be developed during each phase of the project.
    Floorplanning constraints are essential for a number of reasons involving several disciplines. For example, certain components may need to be placed close together to ensure timing margins are met or loss budgets are not exceeded. If terminations are used on a signal, these termination components need to be placed close to a driver or receiver to be effective. Decoupling capacitors need to be placed as close to an IC as possible to limit the inductance between the capacitor and the power pins of the IC. Mechanical constraints on placement, including placement interferences or heating concerns, must also be considered when doing floorplanning.

    As critical nets are routed, they must conform to requirements set by the electrical constraints. They must not exceed maximum length limits. Signals often have to be tightly length-matched to other signals. They must not be routed with an excessive number of vias. They must be routed with certain widths and above solid reference planes so as to maintain a consistent characteristic impedance. They must not be routed too close together to alleviate crosstalk concerns.

    Similarly, care must be taken when routing power nets. There must be adequate metal to supply all the current-carrying needs of the ICs. Planes adjacent to high-speed routing need to be solid and continuous.

    Summary
    In order to meet schedule constraints, complex printed circuit boards need to be designed right the first time. Validating that the PCB meets all of the electrical design requirements is a huge undertaking.

    Reply
11. March 27, 2015 at 9:48 am

    Tomi Engdahl says:

    Optocomponent, sensors, actuators and other erillispiirejä was sold last year to 63.8 billion dollars. IC Insights’, the market grew at a record high. Last year growth was 9 percent.

    For discrete ICs couple of the previous year had been weak, even though the semiconductor market grew by the way. Last year, with the general increase in demand, however, raised the erillispiirien sales growth.

    Above all CMOS circuits and the LED chip sales increased optocomponent market 31.6 billion US dollars. Led sales will continue to grow this year.

    Source: http://www.etn.fi/index.php?option=com_content&view=article&id=2607:erillispiireja-myytiin-ennatysmaara&catid=13&Itemid=101

    Reply
12. March 27, 2015 at 9:50 am

    Tomi Engdahl says:

    The new structure will cram 10 terabytes to solid-state disk

    Intel and Micron have developed a new 3D flash technology, which provides up to three times the recording density of the current of the NAND techniques. Technology provides a standard 2.5-inch solid state hard disk imported up to 10 terabytes of storage capacity.

    Technology is the secret of the so-called floating GATE. a floating gate structure. It is commonly used in the technology, which is now for the first time decided to take advantage of 3D NAND circuit, the better the performance, quality and reliability possible.

    Intel’s new and Micron NAND flash memory of the memory cells 32 are stacked on top of each layer. MLC structure resulting in a 256-gigabyte circuit structure and TLC (triple-level cell) 384-gigabyte chip. According to Intel, the structure allows more than 3.5 terabytes of memory implementation of the old stick of gum-sized solid-state memory.

    Source: http://www.etn.fi/index.php?option=com_content&view=article&id=2610:uusi-rakenne-ahtaa-10-teratavua-ssd-levylle&catid=13&Itemid=101

    Reply
13. March 27, 2015 at 9:52 am

    Tomi Engdahl says:

    MIT and Stanford University researchers have developed a solar cell, which is connected to two different layers. The aim is to be converted to electricity greater part of the sunlight spectrum.

    The new tandem structure is based on the normal silicon-based cells. It is connected to the top of the semi-transparent perovskite layer.

    Simpler structure makes the cells based on easier and less costly to manufacture. At the moment, the first versions of the new structure of the efficiency is 13.7 percent, but the researchers believe that the structure’s efficiency is easy to increase to 30 per cent.

    Source: http://www.etn.fi/index.php?option=com_content&view=article&id=2609:kaksikerrosrakenne-tehostaa-aurinkokennoa&catid=13&Itemid=101

    Reply
14. March 29, 2015 at 5:55 am

    Tomi Engdahl says:

    Wall Street Journal:
    Intel is in talks to buy programmable logic device maker Altera, which would be its largest acquisition ever given Altera’s $10.4B market capitalization

    Intel in Talks to Buy Altera
    Altera, a maker of chips for networks and cars, would be Intel’s biggest purchase ever
    http://www.wsj.com/articles/intel-in-talks-to-buy-altera-1427485172

    Intel Corp. is in advanced talks to buy chip partner Altera Corp., according to people familiar with the matter, a move that would represent the semiconductor giant’s biggest-ever acquisition.

    Reply
15. March 30, 2015 at 8:44 am

    Tomi Engdahl says:

    Nanolaser Enables On-Chip Photonics
    Using light to communicate instead of electricity
    http://www.eetimes.com/document.asp?doc_id=1326138&

    Sending communications signals around chips, and between chips and boards is an area of intense research worldwide. Now University of Washington (Seattle) and Stanford University (Calif.) have created an on-chip laser that can be electro-modulated for easy optical communications.

    Most materials from which on-chip lasers can be built are not compatible with silicon substrates, but these researchers has high hopes for their atomically thin (just 0.7 nanometers thick) laser can be integrated onto standard silicon chips.

    “Today we are using a tungsten photonics cavity sandwiched between layers of selenium, but we hope to achieve the same results with silicon nitride in the future,”

    Reply
16. March 30, 2015 at 8:48 am

    Tomi Engdahl says:

    Bosch Rides Apple to MEMS Dominance
    2014 MEMS Ranking
    http://www.eetimes.com/document.asp?doc_id=1326146&

    Two market research firms, IHS and Yole Développement, issued MEMS reports this week, both naming Robert Bosch GmbH as the undisputed No. 1 in the market.

    Bosch grew its MEMS revenue by 20% in 2014, with sales revenues totaling $1.2 billion, according to Yole. Yole now calls Bosch a future “MEMS titan,” noting a widening gap between Bosch and STMicroelectronics. The disparity between the two companies now stands at more than $400 million.

    The force separating winners from losers in the MEMS market today is Apple. “Apple dictates the ranking of top 10 MEMS manufacturers in 2014,” IHS observed.

    Beyond iPhone, contributing to Bosch’s rise to “titan” status is its history.

    “Having both markets – auto and consumer – allows Bosch to optimize a fab infrastructure.”

    With slight differences in the rankings, both market research firms identified Bosch, Texas Instruments, ST, Hewlett-Packard and Knowles as the top five MEMS vendors. Jean-Christophe Eloy, president & CEO at Yole, pointed out that Bosch now holds a third of the $3.8 billion revenue shared by the top five.

    Asked what other breakthroughs might help the MEMS market grow, Mounier pointed out, “Sensor fusion (not only inertial, but also gas sensors, humidity, temperature …), 300mm manufacturing, new packaging (TSV, WLCSP)/New detection principles, and others.”

    Reply
17. March 30, 2015 at 8:52 am

    Tomi Engdahl says:

    Robotic Bacteria Senses Humidity
    Graphene quantum dots stud living sensor
    http://www.eetimes.com/document.asp?doc_id=1326153&

    -The best humidity sensors today use a polymer that shrinks and expands as the humidity changes, but University of Illinois at Chicago researchers claim that in the future bacterial spores (inert seeds) studded with graphene quantum dots will not only outperform polymer-humidity sensors by 10X, but can endure the extremes of temperature, vaccuum and ultra-low humidity.

    “The is no manmade material that can respond with the same speed and energy density as our bacterial spores,” Vikas Berry told EE Times. “We have extensive experience with polymers and spores beat them all.”

    Called a Nano-Electro-Robotic Device (NERD) it is based on a bacterial spore, which essentially a bacterium in hibernation. If it were to get wet, it would “wake up” and need nutrients, but as a spore it has no external needs and will not wake up even at high levels of humidity. However, because the spore is “waiting” for wet conditions to bring it out of hibernation, it is extremely sensitive to changes in humidity, even at the low-end of the scale –the bane of most polymers. In fact, it becomes even more sensitive under low-humidity conditions, the opposite of polymer-based humidity sensors.

    Reply
18. March 30, 2015 at 8:58 am

    Tomi Engdahl says:

    The world’s smallest capacitor

    French IPDiA has introduced the world’s smallest size of the capacitors. 0101-sized novelty is one of the nanofarad capacitor. It can be used, for example, a DC filter for up to 10 GHz microwave range of the power of applications.

    The capacitor voltage range of 450 volts (1,3nF / mm2) – 11 volts (250 nF / mm2)

    Source: http://www.etn.fi/index.php?option=com_content&view=article&id=2615:maailman-pienin-kondensaattori&catid=13&Itemid=101

    Reply
19. March 31, 2015 at 7:21 am

    Tomi Engdahl says:

    5 Don’ts and Do’s for Working with a Contract Manufacturer
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1326141&

    An OEM’s relationship with its contract electronics manufacturer (CEM) can be a lynchpin in ensuring that viable products reach the marketplace successfully. And by “viable” I mean much more than “designs that work” – I mean economically viable, too.

    DON’T

    1. Let the CM Be the Last to Know — If we’re the last people to view the product design, bill of materials, and so on, then we’re not able to add value.

    2. Lock-Down Designs Prior to a DFM Review — The design-for-manufacturing (DFM) review is where we add some of the greatest value.

    3. Single-Source Materials — Designing in components that have only one source can be the demise of even the best electronics products. Products with single-source components are vulnerable and more costly.

    4. Over-Design — An over-designed electronics product is often an economic failure. The most successful electronics products balance adequate, reliable performance with a low cost to manufacture.

    5. Under-Automate — There is a very simple equation in manufacturing: manual = expensive. Designs that minimize the need for manual labour will fetch higher margins.

    DO

    1. Start Talking Early — It is literally never too early to start talking to your contract manufacturer.

    2. Be Open Minded — A manufacturer sees things very differently from a designer, and both viewpoints have great value.

    3. Prepare Detailed Documentation — I don’t think it’s possible to under-communicate when it comes to providing instructions to a CEM.

    4. Design for Manufacture — DFM essentially means considering how easy and cost-effective it is to manufacture an assembly, and designing to reduce those costs.

    5. Design for Test — Testing an electronics assembly may require extra space or components on the board. It’s worthwhile to design a product with testing in mind because it helps ensure the right product the first time.

    Reply
20. March 31, 2015 at 7:27 am

    Tomi Engdahl says:

    Researchers Claim 44x Power Cuts
    New on/off transceivers reduce power 80%
    http://www.eetimes.com/document.asp?doc_id=1326161&

    Researchers sponsored by the Semiconductor Research Corp. (SRC, Research Triangle Park, N.C.) claim they have extended Moore’s Law by finding a way to cut serial link power by as much as 80 percent. The innovation at the University of Illinois (Urbana) is a new on/off transceiver to be used on chips, between chips, between boards and between servers at data centers.

    “While this technique isn’t designed to push processors to go faster, it does, in the context of a datacenter, allow for power saved in the link budget to be used elsewhere,”

    Today on-chip serial links consume about 20 percent of a microprocessor’s power and about seven percent of the total power budget of a data center. By using transceivers that only consume power when being used, a vast amount can be saved from their standby consumption.

    The reason the links are always on today is to maximize speed. The new architecture reduces their power-up time enough to make it worth turning them off when not it use. The team estimates that data centers alone would save $870 million per year by switching to their transceiver architecture.

    Other groups have tried to build on/off transceivers, but according Hanumolu, their power-on time was too slow–in the 100s of nanoseconds range–and of course there is Energy Efficient Ethernet (IEEE 802.3az) but it requires microseconds to power-on, whereas the University of Illinois design takes just 22 nanoseconds.

    Of course, the power savings is dependent on the application, and circuits that are always-on, like clocks, would not be appropriate. However, there are so many seldom, but necessary, serial links on- and between-chips and systems that on average the new transceiver consumes 10-times less power than the convention kind, according to Hanumolu.

    The researchers estimate that serial links are idle more than 50-to-70 percent of the time on average, making a significant waste of power to leave them on all the time.

    Reply
21. March 31, 2015 at 7:30 am

    Tomi Engdahl says:

    How Will Deep Learning Change SoCs?
    http://www.eetimes.com/document.asp?doc_id=1326149&

    Deep Learning is already changing the way computers see, hear and identify objects in the real world.

    However, the bigger — and perhaps more pertinent — issues for the semiconductor industry are: Will “deep learning” ever migrate into smartphones, wearable devices, or the tiny computer vision SoCs used in highly automated cars? Has anybody come up with SoC architecture optimized for neural networks? If so, what does it look like?

    “There is no question that deep learning is a game-changer,” said Jeff Bier, a founder of the Embedded Vision Alliance. In computer vision, for example, deep learning is very powerful. “The caveat is that it’s still an empirical field. People are trying different things,” he said.

    There’s ample evidence to support chip vendors’ growing enthusiasm for deep learning, and more specifically, convolutional neural networks (CNN). CNN are widely used models for image and video recognition.

    Earlier this month, Qualcomm introduced its “Zeroth platform,” a cognitive-capable platform that’s said to “mimic the brain.” It will be used for future mobile chips, including its forthcoming Snapdragon 820, according to Qualcomm.

    Cognivue is another company vocal about deep learning. The company claims that its new embedded vision SoC architecture, called Opus

    Nvidia is banking on the all aspects of deep learning in which GPU holds the key.

    China’s Baidu, a giant in search technology, has been training deep neural network models to recognize general classes of objects at data centers. It plans to move such models into embedded systems.

    One thing is clear. Gone are the frustration and disillusion over artificial intelligence (AI) that marked the late 1980’s and early ‘90’s. In the new “big data” era, larger sets of massive data and powerful computing have combined to train neural networks to distinguish objects. Deep learning is now considered a new field moving toward AI.

    Reply
22. March 31, 2015 at 7:33 am

    Tomi Engdahl says:

    Analysts Cool on Intel/Altera Combo
    http://www.eetimes.com/document.asp?doc_id=1326165&

    Wall Street’s excitement on Friday over reports x86 giant Intel Corp. was in talks to acquire FPGA maker Altera has left some analysts cold on Monday morning.

    On Friday, the Wall Street Journal and Reuters reported Intel was in talks to acquire Altera. The FPGA maker’s stock shot up from $34.74 to $44.41 within thirty minutes, pushing the price of what would be Intel’s largest acquisition ever from $10 billion to $13 billion. Altera’s stock price cooled slightly Monday to about $42.

    “People have been talking about something like this for two or three years but when I run down the advantages to Intel, I’m not so sure I come up with a very long list,”

    The deal would help Intel diversify beyond the slumping PC market, expanding its growing business in sectors such as telecom. Like Intel, Altera sells chips at relatively high average prices and profit margins.

    However the volumes of the FPGA market are tiny by comparison to Intel’s computer markets.

    Intel and Altera have grown close in recent years, potentially sparking talk of an acquisition. Altera will use Intel as a supplier of 14nm foundry capacity, although it still maintains a longstanding relationship with TSMC which makes most of its chips.

    Altera is the second largest maker of FPGAs, following Xilinx. IC Insights ranks it as the 39th largest chip maker with revenues of $1.9 billion in 2014 compared to Xilinx at #30 with $2.4 billion. Semico projects the FPGA market as a whole will grow from $5.4 billion this year to $7.4 billion in 2019, slightly faster than industry.

    Intel has experimented with links between its server processors and FPGAs, an approach Microsoft is starting to adopt in its data centers. However, Intel does not have to acquire Altera to get access to FPGA technology.

    Reply
23. March 31, 2015 at 7:33 am

    Tomi Engdahl says:

    Neural Networks Take on Embedded Vision
    Synopsys convolutional neural network coprocessor lowers power for vision processing.
    http://www.eetimes.com/document.asp?doc_id=1326162&

    The growth in embedded vision systems—systems that extract meaning from visual inputs—is driving demand for more performance- and power-efficient vision-processing capabilities. Many companies have risen to respond to this demand: AMD, CEVA, Imagination, Intel, Nvidia, and various ARM licensees. They use a variety of hardware: FPGAs, FPGA/MPU combinations, graphics processing units, and specialized heterogeneous multicore designs optimized for the task.

    Reply
24. March 31, 2015 at 7:38 am

    Tomi Engdahl says:

    New Part Day: Modern PALs
    http://hackaday.com/2015/03/30/new-part-day-modern-pals/

    Back in the bad old days, if you needed a little bit of custom logic you would whip out a tiny chip known as a PAL. A Programmable Logic Array is just what it sounds like and is the forerunner of modern, unsolderable CPLDs and FPGAs.

    PALs and GALs have died off

    now it seems the only programmable logic you can buy are huge, 100-pin monstrosities.

    Enter the Greenpak. [Nick] had a dev kit for these ‘modern PALs’ sitting around and decided to give it a go. They’re small – they max out at 20 pins – but there are a few features that make it a little more interesting than a simple array of AND and OR gates. The Greenpak3 features analog comparators, look-up tables, RC oscillators, counters, and GPIO that will work well enough as circuit glue. They also work at 5V, something you’re just not going to find in more complex programmable logic.

    These tiny chips are programmed in a graphical IDE, but the datasheet (PDF) includes full documentation for the bitstream; someone needs to write a Verilog or VHDL compiler for it soon

    http://www.silego.com/greenpak3.html

    Reply
25. March 31, 2015 at 8:19 am

    Tomi Engdahl says:

    Hand-Drawn and Inkjet Printed Circuits for the Masses (Video)
    http://hardware.slashdot.org/story/15/03/30/1942206/hand-drawn-and-inkjet-printed-circuits-for-the-masses-video

    We started looking at ways to make instant hand-drawn or inkjet-printed circuit boards because Timothy met an engaging young man named Yuki Nishida at SXSW. Yuki is a co-founder of AgIC, a company that makes conductive ink pens and supplies special paper you can use to write or draw circuits or, if you have the right model of Brother printer, to print them with special inkjet inks.

    A little cursory Google searching will soon lead you to other companies selling into the home/prototype circuit board market, including Cartesian Co and their Argentum 3-D printer that does prototype and short-run PCBs and only costs $899

    Reply
26. March 31, 2015 at 9:09 am

    Tomi Engdahl says:

    Intel could buy Altera for £7bn in IoT push
    Reported deal would be Intel’s largest acquisition
    http://www.theinquirer.net/inquirer/news/2402128/intel-reportedly-in-talks-to-buy-altera-for-gbp7bn-in-iot-push

    INTEL IS REPORTEDLY IN TALKS to buy programmable logic device (PLD) manufacturer Altera for $10.4bn (about £7bn).

    A report in The Wall Street Journal quoting people familiar with the matter said that Intel is “in advanced talks to buy chip partner Altera” in what would be the chip giant’s biggest acquisition.

    Altera is the world’s second largest supplier of PLDs and system-on-chip (SoC) field programmable gate arrays (FPGAs). The company employs over 3,000 people worldwide and had reported revenues of $1.9bn last year.

    If the rumours are true, Intel’s largest purchase would follow on the heels of a long series of semiconductor mergers and acquisitions, including NXP and Freescale, Cypress Semiconductor and Spansion, and Lattice Semiconductor and Silicon Image.

    “Intel is already the leading supplier of high-performance wired and wireless telecoms infrastructure processor solutions and, with an increasing market for IoT-connected devices, these markets provide opportunity for the right solutions.

    Reply
27. April 1, 2015 at 6:16 am

    Tomi Engdahl says:

    Philips Offloads LED Lighting Components Unit for $2.8 Billion
    http://www.eetimes.com/document.asp?doc_id=1326186&

    Philips has agreed to sell an 80.1 percent stake in the company’s lighting components division for $2.8 billion to Go Scale Capital, a technology fund that will seek to build the company’s automotive LED business.

    The deal, which herald a bigger strategic move for Philips that will see the company spin off its main lighting division, via a stock market flotation, with the Dutch group opting to focus more on medical technology and selected consumer electronics in future.

    The deal is expected to be completed in the third quarter of 2015 subject to regulatory approval. The newly formed company will be called Lumileds and will continue to act as a supplier to Philips.

    Philips, which is the world’s largest lighting manufacturer, estimates that the value the sale of the lighting components subsidiary represent $3.3 billion including debt. The lighting components division comprises an automotive lighting unit and the Lumileds LED manufacturing business. The unit made a 2014 profit of 141 million euros on sales of 1.42 billion euros.

    Philips has described the components subsidiary as a stable cash-generator. Philips will retain a 34 percent stake in the U.S.-based LED arm.

    Reply
28. April 1, 2015 at 6:49 am

    Tomi Engdahl says:

    3D Qualcomm SoCs by 2016
    Adding unlimited layers sans STVs
    http://www.eetimes.com/document.asp?doc_id=1326174&

    The future of three-dimensional (3D) very large scale integration (VLSI) for system-on-chips (SoCs) will not stack die connected by through-silicon-vias (TSVs), but will build them on a single layered die, according to Karim Arabi, vice president of engineering at Qualcomm speaking at the International Symposium on Physical Design (ISPD-2015, Mar. 29-April 1).

    “Our 3D VLSI technology, which we call 3DV, enables die size to be shrunk in half, while simultaneously increasing yields,” Arabi told us.

    Qualcomm’s motivation, according to Arabi, is market share in the 18 billion smartphones that he predicts will be produced by 2018 — “more than all the computers and other electronic devices combined,” he told us.

    In the long term, Qualcomm is building neural processing units (NPUs) modeled on the human brain, “because they are highly flexible and highly efficient for the next generation of mobile devices, cloud computing, Big Data processing, deep learning and machine learning,”

    Qualcomm is creating two basic types of 3DV interconnection methods with the hope of deploying them by 2016. These new types of 3D interconnection comes in two flavors face-to-back (F2B) and face-to-face (F2F).

    F2B is easier because it doesn’t need precision bonding but instead just puts a thin layer of silicon on top of the finished first layer and starts building the second layer using traditional vias.

    F2F, on the other hand, allows both chips to use copper interconnects and optimally performing transistors, but has the disadvantage, according to Arabi, that the F2F method requires larger vias the size of which are limited by the accuracy with which the two facing wafers can be bonded. Qualcomm, however, believes that by using a mix of the two techniques it will be able to produce fully optimized 3DV SoCs with an unlimited number of layers.

    Reply
29. April 1, 2015 at 6:51 am

    Tomi Engdahl says:

    Neural Networks Take on Embedded Vision
    Synopsys convolutional neural network coprocessor lowers power for vision processing.
    http://www.eetimes.com/document.asp?doc_id=1326162&

    The growth in embedded vision systems—systems that extract meaning from visual inputs—is driving demand for more performance- and power-efficient vision-processing capabilities. Many companies have risen to respond to this demand: AMD, CEVA, Imagination, Intel, Nvidia, and various ARM licensees. They use a variety of hardware: FPGAs, FPGA/MPU combinations, graphics processing units, and specialized heterogeneous multicore designs optimized for the task.

    Now Synopsys Inc. (Mountain View, CA) has released its alternative solution, the DesignWare EV processor core family
    designed to be integrated into an SoC with any of a number of host CPUs, including those from ARM, Intel, Imagination MIPS, PowerPC and others.

    The EV52 and EV54 are optimized for vision computing applications using convolutional neural network (CNN) algorithms, which draw their inspiration from the way humans process visual information. CNNs make use of feed-forward artificial neural networks in which individual neurons are tiled in such a way that they respond to overlapping regions in the visual field. Such overlap is key to the way the human eye tracks movement, recognizes changes in the environment, discriminates between objects, and responds to subtle changes in facial expressions.

    Reply
30. April 1, 2015 at 6:52 am

    Tomi Engdahl says:

    News & Analysis
    Graphene’s First Commercial Success: Energy-Saving Light Bulbs?
    http://www.eetimes.com/document.asp?doc_id=1326173&

    The first commercially viable consumer product to use graphene will be an energy-saving lightbulb which is slated to go on sale later in 2015 according to the device’s developers.

    The dimmable light bulb, which is claimed cut energy use by 10% and last longer, will contain a filament-shaped LED coated in graphene was designed at Manchester University, where graphene was first discovered in 2004 by Andre Geim and Konstantin Novoselov, two Russian-born scientists who both earned the Nobel Prize for Physics and knighthoods.

    The light bulb was developed by a Canadian-financed company called Graphene Lighting

    The graphene-based product is expected to be priced lower than some LED bulbs, which can cost about £15 each.

    Reply
31. April 1, 2015 at 7:20 am

    Tomi Engdahl says:

    Micro PMIC squeezes into wearable devices
    http://www.edn.com/electronics-products/other/4439058/Micro-PMIC-squeezes-into-wearable-devices?_mc=NL_EDN_EDT_EDN_today_20150330&cid=NL_EDN_EDT_EDN_today_20150330&elq=34152ab6d8cc45df969460e9fdb5887f&elqCampaignId=22293&elqaid=25055&elqat=1&elqTrackId=cc215cc6a82144269e7d31db3266c655

    A multiple-rail PMIC (power-management IC) complete with battery-charging circuitry, the AS3701 from ams comes in a tiny chip-scale package that is just 2×2×0.4 mm for use in products that operate from a single lithium-ion cell, such as smart watches, sports bands, wearable medical devices, handheld GPS units, and mobile phones. Its power rails include two 200-mA LDO regulators, a 500-mA step-down DC/DC converter, and two 40-mA programmable current sinks. The synchronous step-down converter, which switches at frequencies of up to 4 MHz, requires only a small inductor and a 10-µF output capacitor.

    Other features of the AS3701 include an I2C interface and multipurpose I/Os for general control tasks.

    Reply
32. April 1, 2015 at 8:07 am

    Tomi Engdahl says:

    Meet The Machines That Build Complex PCBs
    http://hackaday.com/2015/03/31/meet-the-machines-that-build-complex-pcbs/

    You can etch a simple PCB at home with a few chemicals and some patience. However, once you get to multilayer boards, you’re going to want to pay someone to do the dirty work.

    The folks behind the USB Armory project visited the factories that build their 6 layer PCB and assemble their final product. Then they posted a full walkthrough of the machines used in the manufacturing process.

    Reply
33. April 1, 2015 at 9:18 am

    Tomi Engdahl says:

    Samsung takes Google into third dimension of flashy storage
    Flash-flood: Korean 3D flash-furtler melts heart of the Chocolate Factory
    http://www.theregister.co.uk/2015/04/01/samsung_taking_google_into_third_dimension/

    It’s a 3D flash flood: Korean 3D flash-furtler Samsung has landed Google as a customer, according to the Korean Times.

    The report says Google’s data centres will use Sammy’s 3D NAND, which the paper has previously reported will also be used in forthcoming MacBooks from Apple, and which we understand is also utilised by Amazon, and is currently used in Kaminario K2 all-flash arrays.

    Neither Google nor Sammy commented in the report. If true it’s further confirmation that, by stacking 32 layers of planar 2D NAND built using 39-30nm-class cell geometry in a die, Samsung has got itself a significant price/performance advantage over other flash fabricators.

    Its 3D NAND is generally available while Intel/Micron and SanDisk/Toshiba’s have just entered the sampling stage with GA late this year or in 2016. SanDisk/Toshiba is sampling a 48-layer chip, but we can expect Sammy to hit that level soon enough.

    These supply deals with Amazon, Apple and Google – Facebook is also mentioned in passing by the report – mean that these hyper-scale data centre operators will be buying less planar NAND than otherwise from the other flash suppliers.

    Reply
34. April 1, 2015 at 11:54 am

    Tomi Engdahl says:

    Sean Gallagher / Ars Technica:
    Atmel ARM-based microcontroller chip could extend battery life of low-power devices to decades

    New ARM-powered chip aims for battery life measured in decades
    Atmel’s 32-bit SAM L controllers, shipping soon, take low power to new extremes .
    by Sean Gallagher – Mar 31, 2015 1:45am EEST
    http://arstechnica.com/information-technology/2015/03/new-arm-powered-chip-aims-for-battery-life-measured-in-decades/

    Atmel, the San Jose-based microcontroller maker, today released samples of a new type of ultra-low power, ARM based microcontroller that could radically extend the battery life of small low-power intelligent devices. The new SAM L21 32-bit ARM family of microcontroller (MCUs) consume less than 35 microamps of power per megahertz of processing speed while active, and less than 200 nanoamps of power overall when in deep sleep mode—with varying states in between.

    The chip is so low power that it can be powered off energy capture from the body, as Andreas Eieland, Atmel’s Director of Product Marketing for low-power products, demonstrated at CES earlier this year.

    The majority of existing low-power MCUs operate in the range of about 120 to 160 microamps per MHz of processing speed, according to Eieland, who spoke with Ars this week.

    Based on the Embedded Microprocessor Benchmark Consortium’s (EEMBC’s) ULPbench ultra-low power benchmark, the L21 is the lowest power microprocessor ever, achieving a score of 185—50 percent higher than that of the closest competitor (STMicro’s STM32L4) and of Atmel’s last generation of low-power MCUs.

    “What we’ve done on the L21 is that we have five power domains—we don’t just gate away the clock, but we can also take away leakage (of power)from unused modules.” This capability includes a mode that allows peripheral devices to continue to communicate with each other when the CPU core is essentially asleep.

    The L21 MCU uses a 42 MHz Cortex M0+ CPU core—the smallest 32-bit ARM processor. It also carries up to 256 kilobytes of Flash memory, up to 32 kilobytes of static RAM, and up to 8 kb of separate low-power static RAM

    As part of the sample release, Atmel is also offering kits based on the L21 for developers in the form of the SAML21 Xplained Pro (XPRO) evaluation board for rapid protyping.

    Reply
35. April 2, 2015 at 7:37 am

    Tomi Engdahl says:

    Select circuit-protection devices with free online tool
    http://www.edn.com/electronics-products/electronic-product-reviews/other/4439076/Select-circuit-protection-devices-with-free-online-tool?_mc=NL_EDN_EDT_EDN_systemsdesign_20150401&cid=NL_EDN_EDT_EDN_systemsdesign_20150401&elq=2a6fb3acc7c84eadb53f0e1ea4531252&elqCampaignId=22333&elqaid=25105&elqat=1&elqTrackId=f5b4cc671c9f4bfbb26609b4fe971a6f

    The free ESD Suppression Selection Tool, from Littelfuse captures the environment where a circuit-protection device resides, and then runs a software simulation of the device. “This tool doesn’t evaluate our part as a standalone device because the part never operates as a standalone device,” said Chad Marak, director of semiconductor business development for Littelfuse. “It always operates with something else—an ASIC or an IC. You have to consider the whole system.”

    Targeted at overvoltage situations involving ESD (electrostatic discharge), the new tool distills the process of selecting TVS (transient voltage suppressor) diode arrays down to about five minutes. Users enter the specifics of the environment via software and add device settings, including maximum capacitance, maximum leakage current, application details, and the number of lines that need to be protected. From that information, the software simulates the operation of protection devices, then creates a list of devices that offer the most robust performance for the application.

    Littelfuse iDesign
    https://littelfuse.transim.com/login.aspx

    Reply
36. April 2, 2015 at 9:59 am

    Tomi Engdahl says:

    Toshiba Ups Ante in 3D NAND Fray
    http://www.eetimes.com/document.asp?doc_id=1326180&

    The transition to 3D NAND is picking up speed as Toshiba announced in late March it was shipping samples of its 48-layer 3D Bit Cost Scalable (BiCS) stacked cell structure flash.

    The news comes on the heels of Intel and Micron announcing their joint 3D NAND flash technology that stacks flash cells vertically in 32 layers to achieve 256-Gbit multilevel cell (MLC) and 384-Gbit triple-level cell (TLC) die that fit within a standard package.

    the company has continued to invest in its floating-gate technology, having announced a 15nm process technology to produce NAND flash last year.

    “Floating gate is not necessarily going away,” Nelson said. 3D is targeting higher density applications, such as SSDS, although “lots of applications still require lower densities.”

    Nelson said the challenge with its 48-layer BiCS flash has been going vertical and being able to connect all of the layers because it is a precise operation to connect everything in the manufacturing process. He said as manufacturing ramps up in 2016 Toshiba will be able to cost-effectively provide the technology.

    Jim Handy, principal analyst with Objective Analysis, told EE TImes that the move to 3D NAND is going to be most complex transition in the world of semiconductors.

    Reply
37. April 2, 2015 at 10:05 am

    Tomi Engdahl says:

    Analog EDA Finally Automated
    Bosch transferred method to Cadence
    http://www.eetimes.com/document.asp?doc_id=1326192&

    Historically analog designers were almost mysterious and old-school as radio frequency (RF) designers. After acquiring years of experience manipulating the many parameters not present in digital designs, analog designers become fountains-of-knowledge in how to add the”secret sauce” to all the different sorts of analog circuits in use today, often reluctant to embrace automation as an alternative, according to presenters here at the International Symposium on Physical Design (ISPD-2015, Mar 29-to-April 1).

    Nevertheless, analog design automation tools that rival digital design automation tools are arriving on the scene. One approach is to use a design flow where traditional bottom-up techniques (standard cells) meet top-down automated optimization techniques according to professor Jurgen Scheible from the Robert Bosch Center Electronic Design Automation (EDA) division, at Reutlingen University (Germany). Bosch has spent considerable funding the automation of analog design tools, the technology for which it transferred to Cadence Design Systems Inc. (San Jose, Calif.), according to Scheible.

    Reply
38. April 2, 2015 at 1:34 pm

    Tomi Engdahl says:

    Switched-capacitor AC-DC/DC-DC converters boost efficiency in power supplies
    http://www.edn.com/design/power-management/4439069/Switched-capacitor-AC-DC-DC-DC-converters-boost-efficiency-in-power-supplies?_mc=NL_EDN_EDT_EDN_analog_20150402&cid=NL_EDN_EDT_EDN_analog_20150402&elq=cc01d7e98b164c4c974c7c4a9b84e24b&elqCampaignId=22352&elqaid=25126&elqat=1&elqTrackId=c0fba6f7efd348588f3feb521778b562

    In the power electronics industry, companies celebrate when gaining a fraction of a percent efficiency in their product. In today’s energy market, efficiency is the “Holy Grail” of specifications.

    Recently, a fabless semiconductor company called Semitrex, claims to be making headway toward solving the major power issue of our time: energy efficient power supplies. The method on which this company is focusing is called the TRONIUM™ Power Supply System(s) on a Chip™ (PSSoC).

    Semitrex’s Muxcapacitor™ technology provides energy efficiencies of at least 95 percent across heavy to light current loads, even down to 50 milliamps.

    Getting from the power mains to the low voltages required as Point-of-Load (POL) for most IC chips is a huge conversion ratio. Getting these input voltage levels down after rectifying (US at 170 VDC and EU at 325 VDC) is a daunting task.

    Lowering the voltage seen by the primary converter input helps achieve better efficiency. The switched capacitor technique converts one DC voltage to another without the use of lossy magnetics. This technique also has a smaller footprint, handles high voltages and is easier for monolithic integration. As a bonus, the efficiency is not degraded at light loads.

    In terms of passive elements, SC DC-DC converters benefit from the significantly higher energy density of capacitors over inductors. For example, a 1μF 35V SMD capacitor occupies a volume of about 1mm3, achieving an energy density of about 1mJ/mm3, whereas a 100μH 100mA SMD inductor occupies a volume of about 20mm3, achieving an energy density of about 0.05μJ/mm3.

    Reply
39. April 2, 2015 at 1:35 pm

    Tomi Engdahl says:

    Reducing PDN impedance at high frequencies
    http://www.edn.com/design/pc-board/4439014/Reducing-PDN-impedance-at-high-frequencies?_mc=NL_EDN_EDT_EDN_analog_20150402&cid=NL_EDN_EDT_EDN_analog_20150402&elq=cc01d7e98b164c4c974c7c4a9b84e24b&elqCampaignId=22352&elqaid=25126&elqat=1&elqTrackId=35812019cc4941398a7813d43cfe6669

    This paper discusses the importance of low PDN (power-distribution network) impedance on high-speed PCBs, and the ways to achieve lower impedance at high frequencies. The study is conducted with post-layout power integrity analysis using Mentor Graphics Hyperlynx.

    It is important to keep the PDN impedance on a PCB low to minimize the generation of switching noise due to transient current in ICs connected to the power rail. With reference to equation (1), transient current in an IC interacts with PDN impedance and generates switching noise. This noise is induced to the power rail and could cause jitter, SI (signal integrity), and EMI (electromagnetic interference) problems.

    Noise ripple = transient current × PDN impedance

    This paper focuses on the effect of loop inductance and plane capacitance, and how they are manipulated to achieve lower PDN impedance in the high frequency domain. The effect can be achieved by proper placement of decoupling capacitors and applying thinner substrates between layers of power and ground planes. The study is conducted with post-layout PI (power integrity) analysis using Mentor Graphics Hyperlynx.

    Reply
40. April 2, 2015 at 1:37 pm

    Tomi Engdahl says:

    OIF demonstrates 50 Gbps signals using two modulations
    http://www.edn.com/electronics-blogs/rowe-s-and-columns/4439071/OIF-demonstrates-50-Gbps-signals-using-two-modulations?_mc=NL_EDN_EDT_EDN_analog_20150402&cid=NL_EDN_EDT_EDN_analog_20150402&elq=cc01d7e98b164c4c974c7c4a9b84e24b&elqCampaignId=22352&elqaid=25126&elqat=1&elqTrackId=e5dd5c3a4ddf4a7e91e29548475c122a

    Last week at OFC 2015, the OIF (Optical Internetworking Forum) demonstrated two 50 Gbps transmissions using both PAM4 and NRZ formats. Over the past year, PAM4 has emerged as what appears to be the modulation format of choice for many systems, although NRZ will still have its place.

    PAM4, the topic of the Jitter Panel at DesignCon 2015, looks to become the modulation format for LR (long reach) and MR (medium reach) optical links. In particular, PAM4 looks to take over from NRZ for electrical links that lead up to an optical module and across backplanes. For XSR (extra-short reach) applications, NRZ is likely to live on in applications where signal-to-noise ratio is important such as within an optical module or in memory buses.

    Molex shows a 50 Gbps PAM4 signal traveling over a 0.54 m Molex backplane.

    Silicon that can generate a 56 Gbps data stream using NRZ is available

    Reply
41. April 2, 2015 at 1:38 pm

    Tomi Engdahl says:

    14 bit, 2 GSPS ADQ14 single-to-quad digitizer with Xilinx FPGA
    http://www.edn.com/electronics-products/electronic-product-reviews/other/4439108/14-bit–2-GSPS-ADQ14-single-to-quad-digitizer-with-Xilinx-FPGA?_mc=NL_EDN_EDT_EDN_analog_20150402&cid=NL_EDN_EDT_EDN_analog_20150402&elq=cc01d7e98b164c4c974c7c4a9b84e24b&elqCampaignId=22352&elqaid=25126&elqat=1&elqTrackId=ccdb205a86ed44ada60f555de97f1b1a

    SP Devices has introduced their data acquisition platform – ADQ14.

    This device is a unique and compact multi-channel 14-bit digitizer which offers sampling rates up to 2 GSPS in single, dual or quad channel configurations with multi-port synchronization capability.

    The ADQ14 is the first digitizer from SP Devices to host a Xilinx Kintex-7 FPGA, pre-programmed with data acquisition firmware, and is open to the user with the ADQ14 Development Kit for customized real-time signal processing needs. The device can transfer data to a host PC as fast as 3.2 GB/s on PCI Express.

    Particle physics experiments usually need high speed, multi-channel digitizers for their systems.

    Advanced time-of-flight applications are also a fit for this device with the dynamic range capability plus high sampling rate used in this arena.

    Software Defined Radio (SDR) designs can also benefit from the high dynamic range and sampling rate.

    Reply
42. April 2, 2015 at 1:46 pm

    Tomi Engdahl says:

    CoolCube 3D Goes Monolithic
    2D techniques keep vias small
    http://www.eetimes.com/document.asp?doc_id=1326213&

    CoolCube 3D chip designs come from the Laboratoire d’électronique des technologies de l’information (CEA-Leti, Grenoble, France) funded by the French government IBM and many others including Qualcomm specifically for its 3D chip technology. CEA-Leti’s goal is to be one of the first licensing entities for monolithic 3D chips. CoolCube chips combine traditional complementary metal oxide semiconductor (CMOS) processing with monolithic tier stacking techniques that exploits cooler CMOS processing steps with tungsten interconnects and normal-sized vias in the middle layers, and copper on top, according professor Olivier Billoint of the University of Grenoble Alpes (France) at the International Symposium of Physical Design (ISPD-2015, March 29-April 1).

    “CoolCube is a monolithic 3D chip making technique that processes the bottom layer using traditional CMOS hot processing with cool CMOS processing techniques for the inner tiers,”

    Reply
43. April 7, 2015 at 4:05 am

    Tomi Engdahl says:

    Intel changes its accounting practices, will no longer report mobile group losses
    http://venturebeat.com/2015/04/06/intel-changes-its-accounting-practices-will-no-longer-report-mobile-group-losses/

    Intel said that it will now combine the operating results of its PC and mobile device groups in its quarterly reports. The move mirrors an effort in sales to hit customers with a unified sales pitch, rather than subjecting them to multiple pitches from two divisions, the company said.

    The results will certainly make things look better. Intel has been losing about $1 billion a quarter in its Mobile and Communications Group, while the PC Client Group is Intel’s cash cow, as Intel is still the world’s largest provider of chips for PCs.

    Starting on April 14, Intel will offer results that combine the results of the PC Client Group and the Mobile and Communications Group into the Client Computing Group.

    Reply
44. April 7, 2015 at 7:25 am

    Tomi Engdahl says:

    Taiwanese manufacturer Foxconn is the world’s largest contract manufacturer.
    Second is Taiwanese Pegatron.
    Third, the largest is Flextronics, which started from USA but is listed on the Singapore Exchange.

    The largest European electronics contract manufacturer is German Zollner Elektronik (just outside largest 10 manufacturers list).

    Source: http://www.etn.fi/index.php?option=com_content&view=article&id=2637:nokian-tabletin-valmistaja-maailman-suurin&catid=13&Itemid=101

    Reply
45. April 7, 2015 at 7:29 am

    Tomi Engdahl says:

    CCD Image Sensors are Dead, says Yole
    http://www.eetimes.com/document.asp?doc_id=1326226&

    Pierre Cambou, imaging and sensors analyst at market research firm Yole Developpement, has commented on the end of the line for charge-coupled device (CCD) image sensors in an opinion article published by imveurope.

    The article was prompted by a move by the market leader Sony to exit the manufacturing of CCD sensor and camera business that has been commented on by Sony customers. The expectation is that Sony will discontinue production of CCD sensors at its 200mm wafer line at the Kagoshima Technology Centre in March 2017 with a phase out lasting until 2020.

    Cambou says that CCDs still offer the highest performance and for some demanding applications will not be replaced by CMOS image sensors

    End of the line for the CCD?
    http://www.imveurope.com/news/news_story.php?news_id=1637

    Sony has initiated the process of exiting its charge-coupled device (CCD) sensor and camera business. As is usual in this kind of matter, Sony is currently discussing the move with its main customers and distributors, with a preliminary schedule being 2017, with progressive phase out until 2020.

    The timing might not be yet definitive as discussions are ongoing. One thing is certain: this is the beginning of the end for Sony CCDs. This should not astonish anyone in the industry. Those who have been around long enough have witnessed the end of tube technology and then transitions between different CCD technology nodes. Yole Développement, the market research and strategy consulting company, recently covered those transitions in its latest report, ‘Status of the CMOS image industry, 2015 edition’.

    The time of CMOS image sensors (CIS) has now come. Volume CCD manufacturers like Sony have to take the necessary steps to get out of this business before their revenues fall below the running cost of their organisation and facilities. The fact that Sony was the leader in CCD means they were mostly dependent on high volume applications like digital still cameras (DSC) and security. Without that volume their CCD business model has vanished, condemning the remaining applications like machine vision.

    Indeed, this announcement has a major effect on the machine vision community.

    For system manufacturers who were relying on Sony, it is time to make a choice. They must either change to the remaining suppliers such as Teledyne Dalsa, On Semiconductor (Truesense), e2v, Fairchild Semiconductor, or take the big leap to CMOS.

    Strategically, this is a very interesting move to watch. Sony has had a singular approach in handling the CCD to CMOS shift and is now accelerating the change.

    It is always sad for technologists to watch the creative destruction of technology shifts. I believe this major transition will renew the innovation drive of the industry.

    Reply
46. April 7, 2015 at 7:32 am

    Tomi Engdahl says:

    Top 50 Contract Manufacturers Ranked
    http://www.eetimes.com/document.asp?doc_id=1326229&

    A website called Manufacturing Market Insider has released a list of the largest 50 electronics manufacturing services companies ranked by sales.

    The top 50 aggregate sales reached $265 billion up by about 4 percent and more than $10 billion over the equivalent figure in 2013,

    In order, the top ten were:

    Hon Hai (Foxconn ),
    Pegatron,
    Flextronics,
    Jabil,
    New Kinpo Group,
    Sanmina,
    Celestica,
    Benchmark Electronics,
    Shenzhen Kaifa Technology
    Universal Scientific Industrial

    The MMI Top 50 for 2014
    http://mfgmkt.com/mmi-top-50/

    Reply
47. April 7, 2015 at 8:04 am

    Tomi Engdahl says:

    Steven Musil / CNET:
    Samsung estimates $5.4B operating profit in Q1, a decrease of 31% from a year ago, beating analyst expectations; forecasts 12% sales decline YoY

    Samsung beats estimates but expects profit decline in Q1
    Electronics giant estimates operating profit declined 30 percent year-over-year.
    http://www.cnet.com/news/samsung-beats-estimates-but-expects-profit-decline-in-q1/

    Reply
48. April 7, 2015 at 8:19 am

    Tomi Engdahl says:

    New CMOS Device Could Cut Costs of Night Vision, Thermal Imaging
    http://www.techbriefs.com/component/content/article/1198-ntb/news/news/21921

    Engineers at The University of Texas at Dallas have created semiconductor technology that could make night vision and thermal imaging affordable for everyday use.

    Researchers in the Texas Analog Center of Excellence (TxACE) in the University’s Erik Jonsson School of Engineering and Computer Science created an electronic device in affordable technology that detects electromagnetic waves to create images at nearly 10 terahertz, which is the highest frequency for electronic devices. The device could make night vision and heat-based imaging affordable.

    The UT Dallas device is created using Schottky diodes in Complementary Metal- Oxide Semiconductor (CMOS) technology. “There are no existing electronic detection systems operating in CMOS that can reach above 5 terahertz,” said Zeshan Ahmad, lead author of the work, electrical engineering doctoral candidate and a research assistant in TxACE. “We designed our chip in such a way that it can be mass produced inexpensively, has a smaller pixel and operates at higher frequencies.”

    Reply
49. April 7, 2015 at 8:21 am

    Tomi Engdahl says:

    Analog design online classroom gives designers needed expertise
    http://www.edn.com/design/analog/4439025/Analog-design-online-classroom-gives-designers-needed-expertise?_mc=NL_EDN_EDT_EDN_weekly_20150402&cid=NL_EDN_EDT_EDN_weekly_20150402&elq=42e07ddef43e4a96a225d6d70224c977&elqCampaignId=22353&elqaid=25127&elqat=1&elqTrackId=ef3f1ce442f64a0f9676461c78339e01

    In present day electronics design, time-to-market is more critical than it has ever been. To compound the problem in getting quality product out and into customer’s hands, a great majority of companies lack the extensive technical expertise, experience and the manpower to design all but basic analog circuitry into their systems.

    Today’s electronics designer needs to be a more well-rounded and versatile engineer than ever before. Without an abundant supply of good analog mentors, the complex task of designing precision or high speed analog circuitry into a system is a formidable one. That not only includes the design, but also the layout as well.

    Recognizing this shortfall in the industry, Texas Instruments Analog team developed TI Precision Labs which provides engineers with on-demand, hands-on learning.

    The program is free; the modular curriculum includes more than 30 hands-on trainings and lab videos covering analog amplifier design considerations with online coursework.

    Reply
50. April 7, 2015 at 8:26 am

    Tomi Engdahl says:

    Bias power made easy
    http://www.edn.com/design/power-management/4439061/Bias-power-made-easy?_mc=NL_EDN_EDT_EDN_today_20150402&cid=NL_EDN_EDT_EDN_today_20150402&elq=e0840df78b93461b899a6c549990397d&elqCampaignId=22369&elqaid=25147&elqat=1&elqTrackId=2602917436f84fe2a668d3cdb4c2caac

    Many offline-powered systems today need a low-voltage bias supply to power its control circuitry and intelligence. In some cases, bias supply outputs are not required to be isolated from the AC mains, but are used to power a system microcontroller, LED display, drive relays or AC switches. Some examples include home automation, e-metering, standby power supplies in TVs, home appliances, and many others.

    End equipments have become more power-hungry with time as more and more “smarts” and functionalities are being added. Electricity meters, for instance, have transformed from simple metrology with just energy measurement and mechanical displays, to smart e-meters that incorporate radio frequency (RF) communication such as Wi-Fi, ZigBee® and/or power line communication (PLC), LCD displays, AC disconnect relays, and so on. Consequently, their AC/DC power supply requirements have transformed from a single output rail with a few mA to multiple rails with hundreds of mA.

    There are a few different topology options to consider for bias-supply designs. The classic 60-Hz step-down transformer and AC capacitive-drop solutions are both well-known and robust solutions. However, they fall short when it comes to efficiency, size and standby power performance. Similarly, an isolated-flyback switch-mode power supply would be far too complex and expensive to design for this need.

    Off-line bias-supply design specifications and performance requirements vary widely, based on the application and end equipment. However, most system designers are seeking low component count solutions that offer ease of use and simple scaling to reduce overall system design cycle time.

    http://www.ti.com/product/ucc28880

    Reply