Here is my list of electronics industry trends and predictions for 2016:
There was a huge set of mega mergers in electronics industry announced in 2015. In 2016 we will see less mergers and how well the existing mergers went. Not all of the major acquisitions will succeed. Probably the the biggest challenge in these mega-mergers is “creating merging cultures or–better yet–creating new ones”.
Makers and open hardware will boost innovation in 2016. Open source has worked well in the software community, and it is coming more to hardware side. Maker culture encourages people be creators of technology rather than just consumers of it. A combination of the maker movement and robotics is preparing children for a future in which innovation and creativity will be more important than ever: robotics is an effective way for children as young as four years old to get experience in the STEM fields of science, technology, engineering, mathematics as well as programming and computer science. The maker movement is inspiring children to tinker-to-learn. Popular DIY electronics platforms include Arduino, Lego Mindstorms, Raspberry Pi, Phiro and LittleBits. Some of those DIY electronics platforms like Arduino and Raspberry Pi are finding their ways into commercial products for example in 3D printing, industrial automation and Internet of Things application fields.
Open source processors core gains more traction in 2016. RISC-V is on the march as an open source alternative to ARM and Mips. Fifteen sponsors, including a handful of high tech giants, are queuing up to be the first members of its new trade group for RISC-V. Currently RISC-V runs Linux and NetBSD, but not Android, Windows or any major embedded RTOSes. Support for other operating systems is expected in 2016. For other open source processor designs, take a look at OpenCores.org, the world’s largest site/community for development of hardware IP cores as open source.
GaN will be more widely used and talked about in 2016. Gallium nitride (GaN) is a binary III/V direct bandgap semiconductor commonly used in bright light-emitting diodes since the 1990s. It has special properties for applications in optoelectronic, high-power and high-frequency devices. You will see more GaN power electronics components because GaN – in comparison to the best silicon alternative – will enable higher power density through the ability to switch at high frequencies. You can get GaN devices for example from GaN Systems, Infineon, Macom, and Texas Instruments. The emergence of GaN as the next leap forward in power transistors gives new life to Moore’s Law in power.
Power electronics is becoming more digital and connected in 2016. Software-defined power brings to bear critical need in modern power systems. Digital Power was the beginning of software-defined power using a microcontroller or a DSP. Software-defined power takes this to another level. Connectivity is the key to success for software-defined power and the PMBus will enable the efficient communication and connection between all power devices in computer systems. It seems that power architectures to become software defined, which will take advantage of digital power adaptability and introduce software control to manage the power continuously as operating conditions change. For example adaptive voltage scaling (AVS) is supported by the AVSBus is contained in the newest PMBus standard V 1.3. The use of power-optimization software algorithms and the concept of the Software Defined Power Architecture (SDPA) are all being seen as part of a brave new future for advanced board-power management.
Nanowires and new forms of memory like RRAM (resistive random access memory) and spintronics are also being researched, and could help scale down chips. Many “exotic” memory technologies are in the lab, and some are even in shipping product: Ferroelectric RAM (FRAM), Resistive RAM (ReRAM), Magnetoresistive RAM (MRAM), Nano-RAM (NRAM).
Nanotube research has been ongoing since 1991, but there has been long road to get practical nanotube transistor. It seems that we almost have the necessary parts of the puzzle in 2016. In 2015 IBM reported a successful auto-alligment method for placing them across the source and drain. Texas Instruments is now capable of growing wafer scale graphene and the Chinese have taken the lead in developing both graphene and nanotubes according to Lux Research.
While nanotubes provide the fastest channel material available today, III-V materials like gallium arsenide (GaAs) and indium gallium arsenide (InGaAs) are all being explored by IBM, Intel, Imec and Samsung as transistor channels on silicon substrates. Dozen of researchers worldwide are experimenting with black phosphorus as an alternative to nanotubes and graphene for the next generation of semiconductors. Black phosphorus has the advantage of having a bandgap and works well alongside silicon photonics device. 3-Molybdenum disulphide MoS2 is also a contender for the next generation of semiconductors, due to its novel stacking properties.
Graphene has many fantastic properties and there has been new finding in it. I think it would be a good idea to follow development around magnetized graphene. Researchers make graphene magnetic, clearing the way for faster everything. I don’t expect practical products in 2016, but maybe something in next few years.
Optical communications is integrating deep into chips finally. There are many new contenders on the horizon for the true “next-generation” of optical communications with promising technologies in development in labs and research departments around the world. Silicon photonics is the study and application of photonic systems which use silicon as an optical medium. Silicon photonic devices can be made using existing semiconductor fabrication. Now we start to have technology to build optoelectronic microprocessors built using existing chip manufacturing. Engineers demo first processor that uses light for ultrafast communications. Optical communication could also potentially reduce chips’ power consumption on inter-chip-links and enable easily longer very fast links between ICs where needed. Two-dimensional (2D) transition metal dichalcogenides (TMDCs), which may enable engineers to exceed the properties of silicon in terms of energy efficiency and speed, moving researchers toward 2D on-chip optoelectronics for high-performance applications in optical communications and computing. To build practical systems with those ICs, we need to figure out how make easily fiber-to-chip coupling or how to manufacture practical optical printed circuit board (O-PCB).
Look development at self-directed assembly.Researchers from the National Institute of Standards and Technology (NIST) and IBM have discovered a trenching capability that could be harnessed for building devices through self-directed assembly. The capability could potentially be used to integrate lasers, sensors, wave guides and other optical components into so called “lab-on-a-chip” devices.
Smaller chip geometries are come to mainstream in 2016. Chip advancements and cost savings slowed down with the current 14-nanometer process, which is used to make its latest PC, server and mobile chips. Other manufacturers are catching to 14 nm and beyond. GlobalFoundries start producing a central processing chip as well as a graphics processing chip using 14nm technology. After a lapse, Intel looks to catch up with Moore’s Law again with with upcoming 10-nanometer and 7-nm processes. Samsung revealed that it will soon begin production of a 10nm FinFET node, and that the chip will be in full production by the end of 2016. This is expected to be at around the same time as rival TSMC. TSMC 10nm process will require triple patterning. For mass marker products it seems that 10nm node, is still at least a year away. Intel delayed plans for 10nm processors while TSMC is stepping on the gas, hoping to attract business from the likes of Apple. The first Intel 10-nm chips, code-named Cannonlake, will ship in 2017.
Looks like Moore’s Law has some life in it yet, though for IBM creating a 7nm chip required exotic techniques and materials. IBM Research showed in 2015 a 7nm chip will hold 20 billion transistors manufactured by perfecting EUV lithography and using silicon-germanium channels for its finned field-effect transistors (FinFETs). Also Intel revealed that the end of the road for Silicon is nearing as alternative materials will be required for the 7nm node and beyond. Scaling Silicon transistors down has become increasingly difficult and expensive and at around 7nm it will prove to be downright impossible. IBM development partner Samsung is in a race to catch up with Intel by 2018 when the first 7nm products are expected. Expect Silicon Alternatives Coming By 2020. One very promising short-term Silicon alternative is III-V semiconductor based on two compounds: Indium gallium arsenide ( InGaAs ) and indium phosphide (InP). Intel’s future mobile chips may have some components based on gallium nitride (GaN), which is also an exotic III-V material.
Silicon and traditional technologies continue to be still pushed forward in 2016 successfully. It seems that the extension of 193nm immersion to 7nm and beyond is possible, yet it would require octuple patterning and other steps that would increase production costs. IBM Research earlier this year beat Intel to the 7nm node by perfecting EUV lithography and using silicon-germanium channels for its finned field-effect transistors (FinFETs). Taiwan Semiconductor Manufacturing Co. (TSMC), the world’s largest foundry, said it has started work on a 5nm process to push ahead its most advanced technology. TSMC’s initial development work at 5nm may be yet another indication that EUV has been set back as an eventual replacement for immersion lithography.
It seems that 2016 could be the year for mass-adoption of 3D ICs and 3D memory. For over a decade, the terms 3D ICs and 3D memory have been used to refer to various technologies. 2016 could see some real advances and traction in the field as some truly 3D products are already shipping and more are promised to come soon. The most popular 3D category is that of 3D NAND flash memory: Samsung, Toshiba, Sandisk, Intel and Micron have all announced or started shipping flash that uses 3D silicon structure (we are currently seeing 128Gb-384Gb parts). Micron’s Hybrid Memory Cube (HMC) uses stacked DRAM die and through-silicon vias (TSVs) to create a high-bandwidth RAM subsystem with an abstracted interface (think DRAM with PCIe). Intel and Micron have announced production of a 3D crosspoint architecture high-endurance (1,000× NAND flash) nonvolatile memory.
The success of Apple’s portable computers, smartphones and tablets will lead to the fact that the company will buy as much as 25 per cent of world production of mobile DRAMs in 2016. In 2015 Apple bought 16.5 per cent of mobile DRAM.
After COP21 climate change summit reaches deal in Paris environmental compliance 2016 will become stronger business driver. Increasingly, electronics OEMs are realizing that environmental compliance goes beyond being a good corporate citizen. On the agenda for these businesses: climate change, water safety, waste management, and environmental compliance. Keep in mindenvironmental compliance requirements that include the Waste Electrical and Electronic Equipment (WEEE) directive, Restriction of Hazardous Substances Directive 2002/95/EC (RoHS 1), and Registration, Evaluation, Authorization and Restriction of Chemicals (REACH). It’s a legal situation: If you do not comply with regulatory aspects of business, you are out of business. Some companies are leading the parade toward environmental compliance or learning as they go.
Connectivity is proliferating everything from cars to homes, realigning diverse markets. It needs to be done easily for user, reliably, efficiently and securely.It is being reported that communications technologies are responsible for about 2-4% of all of carbon footprint generated by human activity. The needs for communications and faster speeds is increasing in this every day more and more connected world – penetration of smart devices there was a tremendous increase in the amount of mobile data traffic from 2010 to 2014.Wi-Fi has become so ubiquitous in homes in so many parts of the world that you can now really start tapping into that by having additional devices. When IoT is forecasted to be 50 billion connections by 2020, with the current technologies this would increase power consumption considerably. The coming explosion of the Internet of Things (IoT) will also need more efficient data centers that will be taxed to their limits.
The Internet of Things (IoT) is enabling increased automation on the factory floor and throughout the supply chain, 3D printing is changing how we think about making components, and the cloud and big data are enabling new applications that provide an end-to-end view from the factory floor to the retail store. With all of these technological options converging, it will be hard for CIOs, IT executives, and manufacturing leaders keep up. IoT will also be hard for R&D.Internet of Things (IoT) designs mesh together several design domains in order to successfully develop a product. Individually, these design domains are challenging. Bringing them all together to create an IoT product can place extreme pressure on design teams. It’s still pretty darn tedious to get all these things connected, and there’s all these standards battles coming on. The rise of the Internet of Things and Web services is driving new design principles as Web services from companies such as Amazon, Facebook and Uber are setting new standards for user experiences. Designers should think about building their products so they can learn more about their users and be flexible in creating new ways to satisfy them – but in such way that the user’s don’t feel that they are spied on what they do.
Subthreshold Transistors and MCUs will be hot in 2016 because Internet of Things will be hot in 2016 and it needs very low power chips. The technology is not new as cheap digital watches use FETs operating in the subthreshold region, but decades digital designers have ignored this operating region, because FETs are hard to characterize there. Now subthreshold has invaded the embedded space thanks to Ambiq’s new Apollo MCU. PsiKick Inc. has designed a proof-of-concept wireless sensor node system-chip using conventional EDA tools and a 130nm mixed-signal CMOS that operates with sub-threshold voltages and opening up the prospect of self-powering Internet of Things (IoT) systems. I expect also other sub-threshold designs to emerge. ARM Holdings plc (Cambridge, England) is also working at sub- and near-threshold operation of ICs. TSMC has developed a series of processes characterized down to near threshold voltages (ULP family for ultra low power are processes). Intel will focus on its IoT strategy and next-generation low voltage mobile processors.
FPGAs in various forms are coming to be more widely use use in 2016 in many applications. They are not no longer limited to high-end aerospace, defense, and high-end industrial applications. There are different ways people use FPGA. Barrier of entry to FPGA development have lowered so that even home makers can use easily FPGAs with cheap FPGA development boards, free tools and open IP cores. There was already lots of interest in 2015 for using FPGA for accelerating computations as the next step after GPU. Intel bought Altera in 2015 and plans in 2016 to begin selling products with a Xeon chip and an Altera FPGA in a single package – possibly available in early 2016. Examples of applications that would be well-suited for use of ARM-based FPGAs, including industrial robots, pumps for medical devices, electric motor controllers, imaging systems, and machine vision systems. Examples of ARM-based FPGAs are such as Xilinx’s Zynq-7000 and Altera’s Cyclone V intertwine. Some Internet of Things (IoT) application could start to test ARM-based field programmable gate array (FPGA) technology, enabling the hardware to be adaptable to market and consumer demands – software updates on such systems become hardware updates. Other potential benefits would be design re-use, code portability, and security.
The trend towards module consolidation is applicable in many industries as the complexity of communication, data rates, data exchanges and networks increases. Consolidating ECU in vehicles is has already been big trend for several years, but the concept in applicable to many markets including medical, industrial and aerospace.
It seems to be that AXIe nears the tipping point in 2016. AXIe is a modular instrument standard similar to PXI in many respects, but utilizing a larger board format that allows higher power instruments and greater rack density. It relies chiefly on the same PCI Express fabric for data communication as PXI. AXIe-1 is the uber high end modular standard and there is also compatible AXIe-0 that aims at being a low cost alternative. Popular measurement standard AXIe, IVI, LXI, PXI, and VXI have two things in common: They each manage standards for the test and measurement industry, and each of those standards is ruled by a private consortium. Why is this? Right or wrong, it comes down to speed of execution.
These days, a hardware emulator is a stylish, sleek box with fewer cables to manage. The “Big Three” EDA vendors offer hardware emulators in their product portfolios, each with a distinct architecture to give development teams more options. For some offerings emulation has become a datacenter resource through a transaction-based emulation mode or acceleration mode.
LED lighting is expected to become more intelligent, more beautiful, more affordable in 2016. Everyone agrees that the market for LED lighting will continue to enjoy dramatic year-on-year growth for at least the next few years. LED Lighting Market to Reach US$30.5 Billion in 2016 and Professional Lighting Markets to See Explosive Growth. Some companies will win on this growth, but there are also losers. Due currency fluctuations and price slide in 2015, end market demands in different countries have been much lower than expected, so smaller LED companies are facing financial loss pressures. The history of the solar industry to get a good sense of some of the challenges the LED industry will face. Next bankruptcy wave in the LED industry is possible. The LED incandescent replacement bulb market represents only a portion of a much larger market but, in many ways, it is the cutting edge of the industry, currently dealing with many of the challenges other market segments will have to face a few years from now. IoT features are coming to LED lighting, but it seem that one can only hope for interoperability
Other electronics trends articles to look:
Hot technologies: Looking ahead to 2016 (EDN)
CES Unveiled NY: What consumer electronics will 2016 bring?
Analysts Predict CES 2016 Trends
LEDinside: Top 10 LED Market Trends in 2016
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Tomi Engdahl says:
Home> Led Design Center > How To Article
LEDs will inherit the world
http://www.edn.com/design/led/4442454/LEDs-will-inherit-the-world?_mc=NL_EDN_EDT_EDN_funfriday_20160729&cid=NL_EDN_EDT_EDN_funfriday_20160729&elqTrackId=da395cbd04634c02bdd8bfafdf14794a&elq=58d25e4ab85b42949e9551489f96164e&elqaid=33241&elqat=1&elqCampaignId=29063
As we continue to celebrate 60 years of EDN, we look to the future of a technology that was invented in 1962, just 7 years after EDN published its first issue: LEDs.
LEDs are already the brightest light source in the universe—upscaling the previous champ, the arc-lamp. By 2076 they will have not only replaced every other light source, but will also have replaced all other short-range communications (such as Wi-Fi and Bluetooth) with light-pulse encoded signals coming out of every SSL (solid-state light), from freeway lamps to automobile head- and tail-lights, to commercial and home lighting systems.
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AWGs sport up to 8 synchronous channels
http://www.edn.com/electronics-products/other/4442480/AWGs-sport-up-to-8-synchronous-channels-?_mc=NL_EDN_EDT_EDN_productsandtools_20160808&cid=NL_EDN_EDT_EDN_productsandtools_20160808&elqTrackId=6c84288b1ba04f1c920bad7aa750c885&elq=8c3881627b83440eaffdce5d3734fafc&elqaid=33366&elqat=1&elqCampaignId=29167
LXI-based generatorNetbox 14-bit and 16-bit arbitrary waveform generators from Spectrum Instrumentation generate signals from DC to 400 MHz for use in automated test and remote applications. Seven instruments make up the generatorNetbox lineup offering two, four, or eight fully synchronized channels.
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Scope option eases MIPI M-PHY debugging
http://www.edn.com/electronics-products/other/4442497/Scope-option-eases-MIPI-M-PHY-debugging?_mc=NL_EDN_EDT_EDN_productsandtools_20160808&cid=NL_EDN_EDT_EDN_productsandtools_20160808&elqTrackId=38dd77bde68846fd881ab79f679bb521&elq=8c3881627b83440eaffdce5d3734fafc&elqaid=33366&elqat=1&elqCampaignId=29167
Triggering and decoding option RTO-K44 for Rohde & Schwarz RTO2000 digital oscilloscopes allows developers to debug devices and components containing MIPI M-PHY interfaces. Defined as a physical layer, M-PHY serves as the basis for a number of protocol standards that have been optimized for rapid data transmission in mobile devices.
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National Instruments’ NIWeek Trifecta
http://www.edn.com/electronics-blogs/test-cafe/4442482/National-Instruments–NIWeek-Trifecta?_mc=NL_EDN_EDT_EDN_today_20160809&cid=NL_EDN_EDT_EDN_today_20160809&&elqTrackId=94c62c7858fd4aae9baba18d161afcb5&elq=9dd02a75cda94997bb157247dcf35ba8&elqaid=33380&elqat=1&elqCampaignId=29173
It’s August. It’s Texas. It’s hot. Yes, it must be another NIWeek conference hosted by National Instruments in Austin, Texas
NI saves many announcements for NIWeek. There’s always a LabView update. This year was no different, with LabView 2016 adding a control wire for exchanging data between two asynchronous processes. Indeed, LabView is front and center at NIWeek this year, with a particularly emphasis in customization of FPGAs within instruments.
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The Higher Cost Of Automotive
http://semiengineering.com/the-higher-cost-of-automotive/
Suppliers looking to enter this market pay a premium in design time, certification and verification requirements.
A revolution is occurring under the hoods of vehicles today, as the automotive industry continues to add sophistication via electronics to vehicles at a pace never seen before. But because of the automotive ecosystem’s tiered structure, system companies, IP and embedded software developers and tools vendors must invest more just to participate.
Robert Bates, chief safety officer in Mentor Graphics’ Embedded Systems Division, said there are many changes underway in the automotive industry today that appear to be headed in two orthogonal directions.
“There is a push for more and more formalism, through ISO 26262, and the revamp that’s coming,” said Bates. “What that’s doing is asking the OEMs, the Tier 1s and the Tier 2s, to design and develop in a more standardized way than they were used to.
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2-D PV to Rival Graphene
Photovoltaics excel in monolayers
http://www.eetimes.com/document.asp?doc_id=1330268&
A popular photovoltaic material called “perovskites” can rival graphene when grown in hybrid monolayers one atom thin, according to Department of Energy (DoE) funded researchers. This high energy material is easier to grow than graphene and can be doped to make the various varieties of ionic semiconductors needed to beat other two-dimensional (2-D) materials with tunable electronic/photonic properties.
“The high-quality 2D crystals exhibit efficient photoluminescence, and color tuning could be achieved by changing sheet thickness as well as composition via the synthesis of related materials,” the researchers said in Science.
http://science.sciencemag.org/content/349/6255/1518
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Big Three Chipmakers Likely to Boost Capex
http://www.eetimes.com/document.asp?doc_id=1330272&
TAIPEI — The big three chipmakers — Intel, Samsung and TSMC — are likely to increase capital expenditures during the second half of this year while the rest of the semiconductor industry tightens the belt, according to a market research firm.
The top-three companies will probably spend $20 billion for capex, representing a 90 percent increase from the first half of 2016, IC Insights said in a report emailed to EE Times on August 4. The companies will need to boost spending later this year to meet full year capex targets, according to the Scottsdale, Arizona-based company.
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OLEDs to beat LCDs in smartphones by 2020, says IHS Markit
http://www.eetimes.com/document.asp?doc_id=1330275&
Although liquid-crystal display (LCD) has dominated mobile phone displays for more than 15 years, organic light-emitting diode (OLED) display technology is expected to become the leading smartphone display technology in 2020, according to IHS Markit’s recent figures.
AMOLED displays with a low-temperature polysilicon (LTPS) backplane will account for more than one-third (36 percent) of all smartphone displays shipped in 2020, becoming the most-used display technology in smartphone displays, surpassing a-Si (amorphous silicon) thin-film transistor (TFT) LCD and LTPS TFT LCD displays.
“While OLED is currently more difficult to manufacture, uses more complicated materials and chemical processes, and requires a keen focus on yield-rate management, it is an increasingly attractive technology for smartphone brands,” notes David Hsieh, senior director at IHS Markit.
“OLED displays are not only thinner and lighter than LCD displays, but they also boast better colour performance and enable flexible display form factors that can lead to more innovative design.”
Samsung Electronics has already adopted OLED displays in its smartphone models, and there is also increasing demand from Chinese Huawei, OPPO, Vivo, Meizu and other smartphone brands. Apple is also now widely expected to use OLED displays in its upcoming iPhone models.
Samsung Display, LG Display, Sharp, JDI, BOE, Tianma, GVO, Truly, and CSOT are also starting to ramp up their AMOLED manufacturing capacities
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Murata’s Playbook: Smartphones, Auto, Battery
Q&A with Murata executive vice president
http://www.eetimes.com/document.asp?doc_id=1330271&
Forget all those storied but stodgy consumer electronics companies like Sony and Panasonic. And today’s embattled Japanese semiconductor vendors… Renesas, Socionext? Forget about them, too.
The new hope for Japan’s electronics industry is component suppliers who started out making lowly components: ceramic condensers, SAW filters, switches, inductors, etc.
Among these upstarts, Murata Manufacturing Co. stands out.
Murata has become one of the world’s biggest suppliers of wireless modules for smartphones. Designed into Apple and Samsung phones, Murata’s communication modules – whose size and power are optimized to fit, snug and cool in very slim smartphones – command an estimated 50 percent of the global smartphone market.
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Towards the T-1000: Liquid metals propel future electronics
https://www.rmit.edu.au/news/all-news/2016/august/liquid-metals-propel-future-electronics
Science fiction is inching closer to reality with the development of revolutionary self-propelling liquid metals – a critical step towards future elastic electronics.
While building a shape-shifting liquid metal T-1000 Terminator may still be far on the horizon, the pioneering work by researchers at RMIT University is setting the foundation for moving beyond solid state electronics towards flexible and dynamically reconfigurable soft circuit systems.
researchers dream of being able to create truly elastic electronic components – soft circuit systems that can act more like live cells, moving around autonomously and communicating with each other to form new circuits rather than being stuck in one configuration.
Liquid metals, in particular non-toxic alloys of gallium, have so far offered the most promising path for realising that dream.
As well as being incredibly malleable, any droplet of liquid metal contains a highly-conductive metallic core and an atomically thin semiconducting oxide skin – all the essentials needed for making electronic circuits.
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Facebook Opens EE Honeypot
New hardware lab aims to attract EEs
http://www.eetimes.com/author.asp?section_id=36&doc_id=1330259&
Facebook, of all companies, is becoming one of the hot new hardware spots in Silicon Valley. How do you like that?
I’ve been following Facebook for a while now thanks to its Open Compute Project which creates multi-vendor specs for everything from servers to switches to 100 Gbit/second optical interconnects and a GPU server.
Then along came Oculus and a smattering of moonshot research programs such as Aquila and OpenCellular, often related to its corporate initiative to spread Internet access (and thus Facebook advertising opportunities) to every end of the planet.
A Facebook blog on the new lab said it includes an EE lab and a prototyping lab. It described in lavish detail the cool gear the prototyping lab will contain including:
A 9-axis mill-turn lathe, used for making its custom two-axis gimbal for air-to-air and air-to-ground laser communications.
A 5-axis vertical milling machine, used to create parts associated with Terragraph, the companies 60 GHz system
A 5-axis water jet, capable of cutting full 10′ x 5′ sheets several inches thick of material, including aluminum, steel, granite, stone, etc.
Two sheet metal shear and CNC folder machines
A CNC fabric cutter
A coordinate measuring machine capable of reverse-engineering a part and turning it into a 3D computer model
An electron microscope – this is at Facebook! — and a CT scanner, used for examining components for failure analysis
Clearly, the company wants to make EEs around the world drool and scramble for their resumes. Strategically, I expect it hopes many of them leave GoogleX labs just a few miles away.
Meanwhile, welcome to the new Silicon Valley and electronics industry where work that used to get done at Bell Labs and Xerox PARC is now funded by advertising around cute cat videos and pictures of dinners people are about to eat.
Inside Facebook’s hardware labs: Moving faster with more collaboration
https://code.facebook.com/posts/561611824036387/inside-facebook-s-hardware-labs-moving-faster-with-more-collaboration/
Hardware engineering traditionally happens behind closed doors, in isolated labs. We fell into this pattern ourselves early on at Facebook, as we opened individual hardware labs to support new teams. Some of our first labs — including one in a repurposed mail room, in our old Palo Alto headquarters — were built for our Infrastructure teams to prototype custom racks, servers, storage systems, and network switches for our data centers. As new, hardware-oriented teams like Connectivity Lab and Oculus started to form, we built additional labs for those teams to design, prototype, and test. Today we have hardware labs all over the world — from our Oculus facilities in the Seattle area to our Aquila hangar in the U.K. to our laser communications lab in Southern California — as well as a number of custom labs in our Menlo Park office that are used by the Oculus, Connectivity Lab, and Infrastructure teams.
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NI Increases Hardware-in-the-Loop (HIL) Test System Customizability With Turnkey HIL Simulators
http://www.ni.com/newsroom/release/ni-increases-hardware-in-the-loop-hil-test-system-customizability-with-turnkey-hil-simulators/en/
New HIL Simulators reduce development and test risk without compromising needed flexibility by building on open, commercial off-the-shelf platforms
Austin, Texas – August 2, 2016 – NIWeek – NI (Nasdaq: NATI), the provider of platform-based systems that enable engineers and scientists to solve the world’s greatest engineering challenges, today announced turnkey HIL Simulators built on an open, modular architecture to help automotive and aerospace embedded software testers maintain quality while handling the demands of shortened schedules, constantly changing test requirements and reduced manpower.
NI systems easily integrate new technologies like camera processing and RF I/O, along with traditional HIL components,into a single system because they are built on open, off-the-shelf hardware and software platforms. Unlike existing approaches, this adaptability lets engineers keep pace with advancing technologies like advanced driver assistance systems, system electrification and advanced sensor integration (that is, radar). With HIL Simulators from NI, test engineers can now choose a turnkey test system based on open, industry-standard platforms rather than having to decide between closed, unadaptable test systems or building the entire system from the ground up.
With HIL Simulators users can:
Customize systems to include technologies like camera data, RF measurement and generation for radar targets, passive entry/passive start, tire pressure monitoring systems and FPGAs for running advanced models, all of which ensures maximum software test coverage
Quickly begin testing to find more defects faster with a turnkey HIL Simulator delivered with VeriStand test software for real-time simulation, stimulus generation and data acquisition
Reuse existing models and hardware by easily integrating third party software models and third-party systems using the ASAM XIL industry standard
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Blog Review: Aug. 10
http://semiengineering.com/blog-review-aug-10/
Is the end near for FinFETs? Applied’s Mike Chudzik digs into the impact of rising parasitic resistance and parasitic capacitance and the challenges of scaling to 5nm.
Fins and Wires. How do we get to 5nm?
http://blog.appliedmaterials.com/fins-and-wires-5nm
As the industry moves beyond 10nm to the 7nm and 5nm nodes, fundamental shifts are needed to address scaling challenges. Among the priority concerns driving industry changes, particularly with respect to materials and architecture, is the impact on transistor performance from rising parasitic resistance and parasitic capacitance or RC. I spoke about this industry dilemma recently at the SEMICON West tradeshow.
Transistor gate lengths have shrunk a thousand-fold over the past 40 years. Various techniques have been used to support continuous CMOS scaling including fixed voltage scaling, oxide scaling and the introduction of strain engineering/HKMG materials to the architectural revolution of 3D FinFET-body width scaling.
The FinFET transistor structure sustained the chip industry by rescuing it from the short-channel effects that limited the device scalability of conventional planar transistors. But this same issue and the alarming rise in parasitic RC is signifying that the FinFET is also reaching it limits.
FinFETs scale by getting taller and narrower. Taller, more rectangular fins help improve drive current and narrower fins enable faster switching and gate length scaling. However, as devices shrink node to node, up to 30% of contact width per node is lost, driving up resistance.
So, is the end near for FinFETs? Several process and design modifications enable FinFET scaling to 7nm, delivering the increased performance the industry demands.
But FinFET scalability beyond 7nm is extremely challenging, as fin widths needed for gate length (Lg) scaling increase threshold voltage (Vt) variability. At 5nm, it appears that silicon and the FinFET structure will not be thick enough to prevent quantum tunneling and gate leakage.
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What DFT history teaches us
http://www.edn.com/electronics-blogs/test-voices/4442443/What-DFT-history-teaches-us?_mc=NL_EDN_EDT_EDN_today_20160810&cid=NL_EDN_EDT_EDN_today_20160810&elqTrackId=c11b7533bb9b4f1cad1f9cdaa3e41a87&elq=8093f7b687074db4bf5808e328342269&elqaid=33394&elqat=1&elqCampaignId=29185
Reading Dan Strassberg’s 1988 article “Pioneering engineers begin to adopt board-level automatic test generation” (PDF) made me realize that there are two DFT-related rules for success that are as true today as they were 30 years ago.
First, it’s important to implement the right amount of DFT. If you implement too little, your test cost will likely grow and you’ll reduce your test coverage. If you implement too much, you risk incurring unnecessary area overhead and a larger hit on the design schedule.
By the early ’90s, ASIC sizes had already grown by an order of magnitude making scan design a necessity.
The next test paradigm came a decade later when scan-based ATPG alone could no longer keep up with growing design sizes. ATPG compression was introduced early in the 2000s and originally provided around a 10× reduction in test pattern volume and test time.
With today’s designs having some 100 million or more gates, a new test-generation paradigm is underway. The relatively new hierarchical ATPG compression approach breaks up the test generation problem into smaller manageable pieces. Going hierarchical typically results in an order of magnitude reduction in test generation time and the required compute memory resource.
The second DFT rule for success is that you should choose the right DFT solution for each application.
This all started changing about a year ago with the explosive growth of automotive designs. The reliability-driven in-system test requirements specified within the automotive ISO 26262 standard are driving rapid and widespread adoption of logic BIST. Although the constraints of using logic BIST have not substantially changed, the automotive requirements have changed the playing field and made this DFT solution a must-have capability.
Tomi Engdahl says:
Home> Community > Blogs > Test Voices
Design for test boot camp, part 2: Test compression
http://www.edn.com/electronics-blogs/test-voices/4436962/Design-for-test-boot-camp–part-2–Test-compression
The size of designs continues to grow and IC manufacturers are pushing for higher test quality, especially in mission-critical applications such as transportation and medicine. More advanced nodes also require new types of tests to catch more subtle defects. The result: exploding test pattern set sizes that result in longer test times and the need for more tester capacity for a given device ship rate. That drives up manufacturing cost.
To help manage the size of test patterns without sacrificing test quality, DFT (design for test) software tools employ compression techniques to reduce the size of the patterns that have to be transferred to the device under test (DUT). The technique involves adding a small amount of circuitry to the DUT and special processing of the test patterns when they are generated by the ATPG (automatic test pattern generation) software. Test compression levels of two orders of magnitude compared to uncompressed patterns are routinely achieved. Once compressed test patterns are expanded within the device under test, they can be applied to a much higher number of shorter internal scan chains than is possible for patterns applied externally. Thus, compression also results in reduced test times.
Tomi Engdahl says:
Intel to Acquire Deep Learning Nervana
Nervana neural chip part of the deal
http://www.eetimes.com/document.asp?doc_id=1330281&
Intel will announce its intention to acquire Nervana Systems at its Intel Developer Forum next week (IDF 2016, San Francisco, Calif., August 16-to-18)—a bid to obsolete the graphics processor unit (GPU) for deep learning artificial intelligence (AI) applications.
Intel dominates the high-performance computing (HPC) market, but Nvidia has made significant inroads into deep learning verticals with its sophisticated GPUs. However, Nervana Systems (Palo Alto, Calif.) has already made a significant dent in Nvidia’s Cuda software for its GPUs with Nervana’s Neon cloud service that is Cuda-compatible. Intel, however, is acquiring Nervana for its promised deep-learning accelerator chip, which it promises by 2017. If the chip plays out as advertised, Intel will sell Deep Learning accelerator hardware boards that beat Nvidia’s GPU boards, while its newly acquired Neon cloud service will outperform Nvidia’s Cuda software.
Tomi Engdahl says:
ADI, Linear Deal Highlights Key Power Trends
http://www.eetimes.com/author.asp?section_id=36&doc_id=1330276&
Peter Real, CTO and senior vice president at Analog Devices (Norwood, MA) speaks with EE Times Europe about the company’s recent acquisition of Linear Technology.
The market of technology has driven Analog into the power management space.
Digital power management
He argues that much of the design of today’s analog components is actually digital anyway. “From our own portfolio, let’s say you pick a data converter design that needs analog and mixed signal, when you look under the hood you might be amazed by the amount of signal processing that goes on, be it correction loops, calibration or minimizing transistor mismatch effects, there a lot of processing that goes on that the customer doesn’t need to know about.”
“We have processors to do the calibration, so I think there is a systemic underestimation in the amount of software firmware and algorithmic capability that exists in a company such as ours and that is a journey we have been on for some time.”
Software defined power is something is very definitely on the radar, bringing together the power devices from Linear and the software from ADI from its experience in software defined radio for cellular basestations.
Tomi Engdahl says:
Faster and Fewer Patterns with Breakthrough ATPG to the Rescue
http://www.eetimes.com/author.asp?section_id=36&doc_id=1330283&
New semiconductor technologies like FinFETs are giving rise to new types of fault effects not covered by standard stuck-at and at-speed tests.
Automatic test pattern generation (ATPG) tools perform two key functions: (1) they generate stimulus/response patterns used by automatic test equipment (ATE) to determine whether or not a digital or mixed-signal design is defective, and (2) if the design is defective, they isolate the probable location of the fault(s). For decades, ATPG has proven a reliable workhorse in performing these functions, but now a young, sleek stallion has come to pasture — in order to accommodate recent trends in the semiconductor industry, Synopsys has re-engineered ATPG from the ground up to be smarter and more efficient.
Tomi Engdahl says:
DRAMs to drag ICs to -2% in 2016
http://www.eetimes.com/document.asp?doc_id=1330288&
Oversupply of DRAM will drive average selling prices (ASPs) of the memory chips down 16% this year, dragging down the overall IC market to a contraction of 2% in 2016, according to the latest report from market watcher IC Insights.
Declining shipments of PC, notebooks and tablets as well as a slowdown in smartphone growth will contribute to an overall decline of 19% in the DRAM market this year, the company said. DRAM prices are known for big swings with ASPs hitting a recent high of $3.16 in 2014 up from a recent low of $1.69 in 2012.
Tomi Engdahl says:
Automotive Is the New Black
http://www.eetimes.com/author.asp?section_id=36&doc_id=1330263&
If you are designing a tailored automotive chip but new to the market, here’s a newbie’s guide to selecting processor IP for safety-critical applications.
As the automotive market for electronics continues to expand and the volume of automobiles being manufactured increases, there is a growing need for tailored semiconductor devices, especially for safety-critical applications.
This market potential is attracting existing semiconductor companies and new start-ups to invest in automotive for the first time. With the PC market declining and a flat mobile market, everyone wants in on the latest trend.
To keep up with the competition, designers must ramp up quickly on the unique requirements of automotive applications and learn how to most efficiently address them.
One important decision designers must make is choice of processor IP.
With the additional requirements needed to achieve ISO 26262 automotive safety standard compliance, it’s essential to understand the key criteria for selecting processor IP.
Tomi Engdahl says:
A new kind of switch to revolutionize the electronics
A new kind of switch is able to combine with each other to work with electricity and electronics to work with light transmission.
Usually the information is processed electronically and transmitted optically. The processing takes place in the semiconductor chips and optical fiber transmission. This accounting change habits requires a change in the optical signal into an electrical and vice versa. Conversion is a modern data processing and data transmission weakest link, because it is relatively slow and requires a lot of energy.
Cambridge University researchers have developed a new release, the way to combine the electrical and lighting. The switch is based on the only state with an identified polaritoni- Bose-Einstein condensate. It mixes electrical and optical signals and use very little energy.
The prototype device has demonstrated the invention to work, but it works only at cryogenic temperatures, ie close to absolute zero. Scientists are working to get the switch to operate at room temperature.
Light matter switch in the future mass production is possible because the prototype is manufactured in mass production based on a scalable method.
Sources:
http://www.tivi.fi/Kaikki_uutiset/uudenlainen-kytkin-mullistaa-elektroniikan-samaan-aikaan-seka-valoa-etta-nestetta-6572726
http://www.tekniikkatalous.fi/tekniikka/ict/nestemainen-kytkin-poistaa-elektroniikan-pullonkaulan-valoaine-on-melkoinen-keksinto-6572410?_ga=1.30598970.424548409.1402643309
Tomi Engdahl says:
What’s Holding Back Analog?
http://semiengineering.com/whats-holding-back-analog/
Tools and methodologies are outdated, which limits innovation.
The uneasy relationship between digital and analog, coupled with tools that are either ineffective or outright ignored by the analog community, may be limiting the growth potential and technological advances in that market.
That certainly doesn’t mean analog isn’t growing. In fact, analog is an increasingly critical component of ICs and the electronic devices they inhabit. The global electronics market is set to incorporate more than 127.5 billion analog ICs this year, according to Semico Research. This equates to several analog chips per device, with anticipated sales of $8 billion by 2020. But Semico also points to an inflection point on the horizon.
Tomi Engdahl says:
High-voltage converter targets smart homes
http://www.edn.com/electronics-products/other/4442466/High-voltage-converter-targets-smart-homes?_mc=NL_EDN_EDT_EDN_productsandtools_20160801&cid=NL_EDN_EDT_EDN_productsandtools_20160801&elqTrackId=3ecfeabf947d45f5b258791b105ebde7&elq=1f9914bfda864326b3705248a4ae7a38&elqaid=33257&elqat=1&elqCampaignId=29076
VIPer01 from ST Microelectronics is an offline AC/DC converter that integrates an 800-V avalanche-rugged MOSFET with PWM current-mode control. The part enables designers to build a low-power switch-mode power supply with a 5-V output for use in home appliances, building and home control, lighting, and motion control, as well as small industrial and consumer applications. It also provides the auxiliary supply to microcontrollers in IoT devices that are permanently connected to the internet or local network.
With its low power consumption and automatic PFM operation under light load, the VIPer01 meets stringent energy-saving standards, including U.S. Energy Star and the European EuP Lot 6 Tier 2 of the EC Ecodesign Directive. System input power consumption is less than 10 mW at 230 VAC in no-load condition and less than 400 mW at 230 VAC with a 250-mW load.
http://www.st.com/content/st_com/en/products/power-management/ac-dc-converters/high-voltage-converters/viperplus/viper01.html?icmp=tt3928_gl_pron_jul2016
Tomi Engdahl says:
Takashi Mochizuki / Wall Street Journal:
Taiwan’s Foxconn completes $3.81B acquisition of Sharp; Sharp CEO Kozo Takahashi resigns
Taiwan’s Foxconn Completes Acquisition of Sharp
The iPhone assembler will begin restructuring efforts to turn around Japanese company
http://www.wsj.com/article_email/taiwans-foxconn-completes-deal-to-acquire-sharp-1470994207-lMyQjAxMTA2NjEwMjUxNDI0Wj
Tomi Engdahl says:
DuoSkin
http://duoskin.media.mit.edu/
DuoSkin is a fabrication process that enables anyone to create customized functional devices that can be attached directly on their skin. Using gold metal leaf, a material that is cheap, skin-friendly, and robust for everyday wear, we demonstrate three types of on-skin interfaces: sensing touch input, displaying output, and wireless communication. DuoSkin draws from the aesthetics found in metallic jewelry-like temporary tattoos to create on-skin devices which resemble jewelry. DuoSkin devices enable users to control their mobile devices, display information, and store information on their skin while serving as a statement of personal style. We believe that in the future, on-skin electronics will no longer be black-boxed and mystified; instead, they will converge towards the user friendliness, extensibility, and aesthetics of body decorations, forming a DuoSkin integrated to the extent that it has seemingly disappeared.
Tomi Engdahl says:
FO-WLP Packs Eye Panel Process
http://www.eetimes.com/author.asp?section_id=36&doc_id=1330300&
Fan-out wafer level packages are on the rise as vendors explore panel-based processes to make them less expensive.
Over the next year, volumes for fan-out wafer level packages (FO-WLPs) will be driven by application processors, RF transceivers and switches, power management integrated circuits, audio codec, connectivity modules, and radar modules for cars.
Many companies like the small form-factor, low-profile features of WLPs. But as they move to the next semiconductor nodes, the face of the die is too small to route all the I/O without using tiny solder balls that might have board reliability issues. This is especially true for audio codec and RF ICs.
FO-WLP for application processors is a gamer changer compared with traditional flip chip on laminate substrates found in package-on-package (PoP) because a substrate is no longer required. That impacts substrate shipments in both unit volumes and revenue because the substrates used for the logic die in the bottom PoP have higher average selling prices.
With FO-WLP, as with any package, there is a demand for cost reduction. Several companies are researching, developing, or installing panel-based production lines, though many technical and economic issues still need to be considered.
Tomi Engdahl says:
Micron Moves 3D NAND Into Mobile
http://www.eetimes.com/document.asp?doc_id=1330303&
Until recently 3D NAND has been only hitting the market within SSDs, but now Micron Technology said it’s ready for mobile devices.
Last week the company introduced its first 3D NAND memory technology optimized for mobile devices and its first products based on the Universal Flash Storage (UFS) 2.1 standard. Micron’s first foray into mobile 3D NAND is a 32GB offering aimed at the high and mid-end smartphone segments, which make up approximately 50% of worldwide smartphone volume, said Gino Skulick, VP of marketing in Micron’s mobile business unit in a telephone interview with EE Times. The company is sampling the new 3D NAND with mobile customers and partners, and it will be widely available by the end of 2016.
Micron 3D NAND for mobile is the first to be built using floating gate technology, and stacks layers of data storage cells vertically to create storage capacity that is three times that of previous generation planar NAND technologies.
Tomi Engdahl says:
RF DAC suits diverse applications
http://www.edn.com/electronics-products/other/4442531/RF-DAC-suits-diverse-applications?_mc=NL_EDN_EDT_EDN_today_20160816&cid=NL_EDN_EDT_EDN_today_20160816&elqTrackId=6af63c9274b14e0383f7602831f0fe0d&elq=d734a017446b40b28f668bba0c641a49&elqaid=33478&elqat=1&elqCampaignId=29259
Analog Devices’ AD9164 16-bit, 12-Gsamples/s DAC with on-chip DDS performs direct RF synthesis at 6 Gsamples/s. This compact device brings high resolution and improved accuracy to a wide range of applications, from radar systems to smart-phone testing.
The AD9164’s integrated direct digital synthesizer ensures phase-coherent fast frequency hopping of less than 300 ns for up to 32 different frequencies.
In addition, the AD9164 includes a 2× interpolator (FIR with 85-dB digital attenuation) that enables configurability for lower data rates and converter clocking to reduce overall system power and ease filtering requirements.
According to the manufacturer, the AD9164 offers 100 to 1000 times improved spectral purity versus previous-generation ADI parts (20 dB to 30 dB better). Higher agility with frequency change time is now 100 times shorter than conventional ADI PLL systems.
AD9164 16-Bit, 12 GSPS, RF DAC and Direct Digital Synthesizer
http://www.analog.com/en/products/digital-to-analog-converters/high-speed-da-converters/ad9164.html
Tomi Engdahl says:
Ian King / Bloomberg:
Intel announces licensing agreement with ARM, opening its 10-nanometer production lines to third-parties to make the chips
Intel Licenses ARM Technology to Boost Foundry Business
http://www.bloomberg.com/news/articles/2016-08-16/intel-licenses-arm-technology-in-move-to-boost-foundry-business
ntel Corp., the world’s biggest semiconductor maker, said it’s licensing technology from rival ARM Holdings Plc, a move to win more customers for its business that manufactures chips for other companies.
The two chipmakers, whose designs and technology dominate in computing and mobile, unveiled the agreement Tuesday at the Intel Developer Forum in San Francisco. The accord will let Intel offer third-party semiconductor companies its most advanced 10-nanometer production lines for manufacturing the complex chips usually used in smartphones.
Intel, which gets the majority of its revenue from making personal-computer processors, has failed to gain ground in the larger and faster-growing phone market — the stronghold of ARM’s technology. Under Chief Executive Officer Brian Krzanich, Intel is trying to persuade other chipmakers to use its factories for their production.
Intel’s embrace of the competing technology comes as the PC market continues to decline and growth in the lucrative server-chip market slows.
Intel announced that LG Electronics Inc., South Korea’s second-biggest phone maker behind Samsung Electronics Co., will use Intel’s foundry business to manufacture 10 nanometer mobile-phone parts.
Separately, Intel said it won’t use extreme ultraviolet lithography as a manufacturing technique in its 10-nanometer production. The technology isn’t ready for the next generation of production, 7 nanometer, Intel also said, and the company won’t use the chipmaking technique until it delivers the promised efficiency.
Tomi Engdahl says:
Korea’s LG plans to make its own mobile chips — in Intel’s factories
The move could be a blow to Qualcomm.
http://www.recode.net/2016/8/16/12507216/lg-chip-manufacture-korea-intel
Korean phone maker LG, which has largely relied on processors from Qualcomm, plans to start making a new generation of homegrown mobile chips using Intel factories.
The news, delivered in a single slide at a technical session at Intel’s developer forum in San Francisco, ended months of speculation that such a move was in the works.
LG, which often takes its cue from Samsung, is following its larger rival further into the chip business.
Apple and China’s Huawei also have their own chip designs, while the rest of the phone industry generally uses processors from Qualcomm or Chinese rivals.
LG will take advantage of Intel’s next-generation 10-nanometer manufacturing technology
chips will be made in Intel plants
Tomi Engdahl says:
Shifts Sited in Mixed-Signal Design
http://www.eetimes.com/author.asp?section_id=36&doc_id=1330301&
Profound changes in the design of high-speed mixed-signal ICs are needed to cope with their increasing complexity and performance demands.
Traditional functional partitions and expertise domains — such as circuit design, layout design, and verification — are rapidly blurring. The ability of developers to innovate across different technology spaces is key. The implications of these technology trends go beyond product development–they deeply impact business strategies.
High speed mixed signal systems bridge digital signal processing, RF (including microwave/millimeter wave) and wired communications, creating a formidable combination of technology and business-related challenges. These challenges are being driven by the rapid increase in demand for pervasive access to high throughput data transmissions.
5G communications promise even faster and more ubiquitous connectivity, supporting multiple communication standards while reducing the size and operating costs of infrastructure. The demands for higher integration, lower power consumption and cost reduction are all expected to accelerate to a level that simply doesn’t seem to be supported by what might, in fact, be a decelerating Moore’s law.
The focus of Moore’s law has been transistor density. But in the past CMOS scaling also provided speed gains benefitting both digital and analog circuits, albeit to the detriment of many other crucial analog properties.
Tomi Engdahl says:
Printed electronics training begins in Oulu
Printed electronics product developers begin to train in the autumn of Oulu. Training is jointly organized by the Oulu University of Applied Sciences (Oulu UAS) and the University of Oulu. There is a world-class equipment for making printed electronics.
” Our company has become the message that education sector is needed, as in the future in almost all electronic devices will be printed electronics and ICT professionals is not enough, ” says Senior Researcher Marja Nissinen Renewable Natural Resources Library.
” Printed electronics education is still the world each time fragmented. In cooperation with the implementation of the training gives students the unique information on the area, as well as a very good start for the future, because particularly in the Oulu region, many companies are expanding in the direction of the printed electronics business, ” says Professor Tapio Fabritius from the University of Oulu.
Source: http://www.uusiteknologia.fi/2016/08/16/painetun-elektroniikan-koulutus-alkaa-oulussa/
Tomi Engdahl says:
Designing high-speed analog signal chains from DC-to-wideband
http://www.edn.com/design/analog/4442529/Designing-high-speed-analog-signal-chains-from-DC-to-wideband?_mc=NL_EDN_EDT_EDN_today_20160815&cid=NL_EDN_EDT_EDN_today_20160815&elqTrackId=a62a89d085ee4fc6844e7aed0ca55066&elq=e11b265140fe47b985a1fdfc282f77e9&elqaid=33463&elqat=1&elqCampaignId=29242
The design of the input configuration, or “front end,” ahead of a high performance, analog-to-digital converter (ADC) is always critical to achieving the desired system performance. Typically the focus is capturing wideband, RF-y type frequencies, like bigger than a 1GHz. However, in some applications DC or near DC signals are also required and can be appreciated by the end user as they too carry important information. Therefore, optimizing the overall front end design to capture both DC and wideband signals requires a DC coupled front end that leads all the way down to the high-speed converter.
Because of the nature of the application, an active front end design will need to be developed as using a passive front end or balun to couple the signals into the converter are inherently AC coupled. In this paper, an overview on the importance of common mode signals and how to properly level shift the amplifier front end will be presented in a real system solution example.
Tomi Engdahl says:
10nm Race Heats Up
http://semiengineering.com/10nm-race-heats-up/
Intel announces 10nm and IP deal with ARM.
The 10nm process and foundry race is heating up, as Intel announced its 10nm technology at its annual conference.
As part of the multi-pronged announcement, Intel’s foundry unit forged a major partnership with ARM. Specifically, ARM will make its physical intellectual-property (IP) available on Intel’s 10nm process. Intel, in turn, will offer the IP for foundry customers.
And on top of that, Intel Custom Foundry announced two new customers—LG Electronics and Spreadtrum.
In fact, TSMC and Samsung are separately readying their respective 10nm finFET processes. Samsung hopes to move into 10nm production by year’s end. Meanwhile, TSMC plans to ramp up the technology in the first quarter of 2017, with 7nm slated for 2018.
Foundry customers will soon have some new but confusing choices at those nodes. For one thing, there is some confusion between 10nm and 7nm.
“Not all 10nm technologies are the same,”
Intel plans to stay on the traditional gate pitch scaling curve, while others tend to have what Bohr calls “looser gate pitches.”
Optimization Challenges For 10nm And 7nm
http://semiengineering.com/optimization-challenges-for-10nm-and-7nm-2/
Experts at the Table, Part 2: Heat is becoming a serious issue as thermal densities rise and this creates problems for industries such as automotive that require robust, long-lived components.
SE: Another change involves the integral of power – heat. Thermal effects are not instantaneous and mean that we have to consider the design over time.
Balachandran: People are already dealing with thermal challenges. This started before 10nm, so it is more a function of how many cores they have on the chip. It is a function of how fast they want to run them. Everyone has heard of dark silicon because you don’t want to use up all the space and integrate everything on the chip and then have to turn them off because you are going to burn the chip. So the dark silicon problem will become worse in 10nm and 7nm because you have more space. You have a doubling of the area, so you can put twice the amount of logic on the die.
SE: Power reductions for 10nm and 7nm are not keeping up with Moore’s Law, so the Power Trends issues will get worse. That will create new problems that did not exist in the past.
Bjerregaard: It is a combination of things that is getting worse. In one dimension you have the systems getting bigger, and the other dimension is that the power density is increasing. 10nm finFET is accelerating the benefits of scaling, but they are accelerating the challenge so it starts to become an exponential problem.
Tomi Engdahl says:
Focus Shifting To Photonics
http://semiengineering.com/focus-shifting-to-photonics/
Using light to move data will save power and improve performance; laser built into process technology overcomes huge hurdle.
Silicon photonics finally appears ready for prime time, after years of unfulfilled expectations and a vision that stretches back at least a couple decades.
The biggest challenge has been the ability to build a light source directly into the silicon process, rather than trying to add one onto a chip after manufacturing. Intel today said it has achieved that milestone, setting the stage for building economies of scale into the process. That may take several more years, but it nonetheless represents an important step for this technology.
The first implementations of this technology will be between systems within a data center, where silicon photonics already is in widespread use. This is a relatively price-insensitive but fast-growing market, supported by improvements in performance and energy that are amortized across thousands of servers. But with a laser built into the semiconductor manufacturing process, the economics of photonics will change significantly.
“The play for photonics is immense bandwidth with the scale of silicon and silicon manufacturability,” she said. “Right now we can drive a 3X per bit power reduction. So you have higher-rate switches, and you get an improvement in power consumption. The core differentiator there is the laser integrated on silicon.”
“For about the next five years, you’ll see it confined to high-performance systems,” McGregor said. “After that, it will be used in more places. As we start seeing massive servers and enterprise neural networks, with machine learning and artificial intelligence, that will require next-generation processors. We’re already starting to see some of those next-generation processors being developed. Silicon photonics is likely to be one of the enablers.”
Seeing the light
There are a number of advantages to using silicon photonics. For one thing, light pulsing through a waveguide on a chip generates much less heat than electrons moving through copper wire—particularly a very skinny copper wire where resistance, as well as the power necessary to drive those electrons, generate heat. Light is also faster that electrons, less prone to cybersecurity issues, and there are fewer physical effects. Photons do not interact the way electrons do, which allows them to be bunched together much more tightly and to cross paths without affecting signal integrity.
“This is a new way to multiplex signals,” said Chris Cone, product marketing manager at Mentor Graphics. “But it also will require new architectures. Topologically, you need to connect everything with wave guides. You etch, grow, and then anneal to smooth the sidewalls to allow light to bounce through them. One thing that helps, though, is that it’s possible to cross waveguides. It will not short out like electrical signals because photons don’t interact the way electrons do.”
Cone said there are a number of emerging markets where this kind of technology will be useful, such as in the biomedical field where light can be used to interact with potential pathogens in body fluids run through a chip. “And you don’t need to use the most advanced process to make this work. It could be done at 350nm rather than 14nm.”
In the short-term, the real target is cloud farms. “As we disaggregate processing from the memory, you need a high-bandwidth connection between the memory and where data is processed,” said Gilles Lamant, distinguished engineer at Cadence. “In the past, we saw this with network appliances connected to fiber. Now, it’s being used for cloud farm environments.”
Tomi Engdahl says:
Solid-State Battery Could Extinguish Fire Risks
https://hardware.slashdot.org/story/16/08/17/2335227/solid-state-battery-could-extinguish-fire-risks
“Researchers have designed a new type of battery that, unlike traditional models containing liquid or gel electrolytes, consists purely of solid chemical compounds and is non-flammable, representing a huge boost for improving battery safety,” reports The Stack.
Solid-state battery could extinguish fire risks
https://thestack.com/world/2016/08/17/solid-state-battery-could-extinguish-fire-risks/
Responding to dangers linked to traditional lithium-ion batteries, the team based at the Swiss Federal Institute of Technology in Zurich (ETH), has built a solid alternative which contains only solid-state electrodes and electrolyte.
‘Solid electrolytes do not catch fire even when heated to high temperatures or exposed to the air,’ explained lead researcher and ETH electrochemical materials professor Jennifer Rupp.
while the solid batteries could operate at normal temperatures, at current development state they performed best at 95°C and above as the lithium ions can move more freely.
Afyon suggested that this capability could be applied in battery storage power plants: ‘Today, the waste heat that results from many industrial processes vanishes unused… By coupling battery power plants with industrial facilities, you could use the waste heat to operate the storage power plant at optimal temperatures,’ he said.
Tomi Engdahl says:
Monolithic JFETs are alive and well
http://www.edn.com/electronics-products/electronic-product-reviews/other/4442559/Monolithic-JFETs-are-alive-and-well?_mc=NL_EDN_EDT_EDN_analog_20160818&cid=NL_EDN_EDT_EDN_analog_20160818&elqTrackId=e6b919db11d142b5ba3f97c313fc68fc&elq=61948c42998a478788e9c2bc780be953&elqaid=33507&elqat=1&elqCampaignId=29290
Home> Tools & Learning> Products> Product Review
Monolithic JFETs are alive and well
Steve Taranovich -August 15, 2016
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High integration in today’s analog ICs is ever expanding, but there are time when a circuit designer needs to design a better differential stage to an amplifier, especially an audio amp or pre-amp, or a voltage controlled resistor, thermally stable follower, sample and hold or matched current sources or when the source is a very high impedance as in electrometer designs where super low bias current and low noise is critical.
Circuit design engineers need to look closely at the benefits of using discrete active devices like these. Jim Williams and Bob Pease were masters of using high-performance discrete active transistors to enhance their design performance when placed in critical areas of their system designs.
Tomi Engdahl says:
How Small Will Transistors Go?
http://semiengineering.com/how-small-will-transistors-go/
Leaders of Imec, Leti and SRC talk about what’s after 7nm, who will play there, and what the challenges will be.
There is nearly universal agreement that Moore’s Law is slowing down. But whether it will truly end, or just become too expensive and less relevant—and what will supplant device scaling—are the subject of some far-reaching research and much discussion.
SE: How far will device scaling go and what will it look like?
Marie Semeria, CEO of Leti: We will push scaling as far as we can. We can push to 3nm. We have designs at 3nm. But it will be costly…There is a new platform for 5nm (CMOS). So for 10 years we have been working on nanowire. We believe that nanowire will be the first platform for CMOS development. We also pioneered FD-SOI technology and proved the scalability of that technology up to 7nm. It is important for companies to know that they can develop their products for many different nodes. 28nm FD-SOI is already under fabrication.
Luc Van den hove, president and CEO of Imec: Clearly, finFET is the dominant technology at 14nm and 10nm. It will most likely be extended to 7nm. But going beyond 7nm, it’s going be hard for a classical finFET.
Ken Hansen, president and CEO of SRC: The clarity is there to 7nm. There is a lot of activity at 5nm. I am convinced that there will be a 5nm node that’s based on mostly traditional kinds of devices, notwithstanding a gate-all-around as opposed to a finFET or something like that. If you get 5nm, that leads to the next node, which is 3nm. 3nm is very sketchy at this point in time.
SE: Will it be economically feasible to move forward beyond 5nm?
Semeria: It’s always a question of the compromise between cost, performance and energy saving. But that’s the story of the semiconductor development. It’s a combination of the architecture, the transistor, the strain, and so on…Even now there are only really four companies working on finFET. Nanowire is just the next version of finFETs. You can use nanowires or nanosheets. It’s not so complicated compared to finFETs. It’s quite close. It’s 3D design.
SE: How does advanced packaging fit into this picture?
Semeria: That’s another way. You can go with 2.5D and 3D.
Van den hove: If you talk about geometry-based scaling, we are not going to stay on a two-year cadence. It’s going to slow down. We will compensate that slowdown by moving into the third dimension. We are going to stay on Moore’s Law.
Hansen: There is a unique package approach born every day. Fan-out packaging, in general, is an explosive area. The only thing that’s holding back fan-out, which is just another form of SIP packaging, has always been cost.
SE: What else are you seeing?
Semeria: We have done comparisons between FD-SOI, finFETs and nanowire at 10nm, 7nm and 5nm. At 5nm nanowires are better compared to FD-SOI and finFETs in terms of electrostatic control. And you can stack the nanowires to reach higher currents, so you can have performance. We will push nanowire to one more node.
Van den hove: There is incremental progress needed on all fronts.
Hansen: We’ve eliminated some [transistor candidates at 3nm and beyond]. Of all the categories, the magneto-electric ones seem to have the highest potential. But that’s speculative at this point.
SE: As we move into the IoT era, what changes?
Semeria: It depends on the application. To keep the low-voltage advantage of FD-SOI, we prefer PCRAM (phase-change memory) or OxRAM (oxide-based RAM). FinFETs will be required to address the high-end market. FD-SOI will be for IoT, especially for automotive, because it shows hardness against radiation. That’s a key advantage for automotive applications. We try to put more and more function in FD-SOI. So it has to be compatible with RF. FinFET isn’t so compatible with RF.
Van den hove: One of the trends is that we see more collaboration along the value chain. We see more of the fabless companies, and even systems companies and OEMs, being involved in the R&D part.
Hansen: Power consumption. The other side is security.
What Transistors Will Look Like At 5nm
http://semiengineering.com/going-to-gate-all-around-fets/
As finFETs run out of steam after 7nm, what comes next? The debate is just beginning.
Chipmakers are currently ramping up 16nm/14nm finFET processes, with 10nm and 7nm just around the corner.
The industry also is working on 5nm. TSMC hopes to deliver a 5nm process by 2020. GlobalFoundries, Intel and Samsung are doing R&D for that node.
But 5nm technology presents a multitude of unknowns and challenges. For one thing, the exact timing and specs of 5nm remain cloudy. Then, there are several technical and economic roadblocks. And even if 5nm happens, it’s likely that only a few companies will be able to afford it.
“My current assumption is that 5nm will happen, but it won’t hit high-volume manufacturing until after 2020,” said Bob Johnson, an analyst at Gartner. “If I were to guess, I’d say 2021 to 2022.”
At 5nm, it will cost $500 million or more to design a “reasonably complex SoC,”
For those who can afford to migrate to 5nm, there are two main transistor contenders at this node—the finFET and the lateral gate-all-around FET. Gate-all-around (GAA), sometimes called the lateral nanowire FET, is a finFET on its side with a gate wrapped around it.
In fact, momentum is building for gate-all-around in the industry.
But the jury is still out on the feasibility of gate-all-around, prompting the industry to consider finFETs at 5nm.
What is gate-all-around?
Today, chipmakers are ramping up finFETs, but not everyone is at the leading edge. In logic, for example, the sweet spot is still at the 40nm and 28nm planar nodes.
Many foundries, in fact, have recently “experienced a surge in 28nm business, especially from communication customers,”
The market also is heating up at the high end. Starting at 22nm and 16nm/14nm, chipmakers migrated from planar devices to finFET transistors.
Eventually, the finFET runs into several issues, though. “Post-7nm, we do see some challenges,”
What’s next?
In R&D, chipmakers are also looking at 3nm and beyond, although it’s unclear if these nodes will ever happen.
For 3nm, the industry is exploring horizontal gate-all-around FETs and vertical nanowire FETs.
Tomi Engdahl says:
Programmable Analog Coprocessor Takes Many Sensor Inputs
http://www.eetimes.com/document.asp?doc_id=1330320&
Cypress Semiconductor’s latest PSoC programmable system-on-chip, the PSoC Analog Coprocessor, simplifies the design of next-generation industrial, home appliance and consumer systems that require multiple sensors.
Many IoT applications require multiple sensors and can benefit from dedicated coprocessors that offload sensor processing from the host and reduce overall system power consumption. The new chip integrates programmable analog blocks, including a new Universal Analog Block (UAB), which can be configured with GUI-based software components. This combination simplifies the design of custom analog front ends for sensor interfaces by allowing engineers to update sensor features quickly with no hardware or host processor software changes, while also reducing BOM costs.
Based on a 32-bit ARM Cortex-M0+, the PSoC Analog Coprocessor comes in a 3.7×2.0mm chip-scale package option.
The PSoC Analog Coprocessor is currently sampling with production expected in the fourth quarter of 2016.
Tomi Engdahl says:
Intel Grabs ARM for 10nm Foundry
Best density claimed in 10nm node
http://www.eetimes.com/document.asp?doc_id=1330311&
Intel revealed its 10nm process could outperform other foundries and will be used to make ARM-based mobile chips for companies including LG Electronics. To enable the move, Intel partnered with ARM’s Artisan division that is porting a reference design for one of its 64-bit cores to the process.
The news at the annual Intel Developer Forum here reinforced the x86 giant’s continued strength in process technology. It also highlighted its need for a still-fledging foundry business to participate fully in the mobile market.
Separately, China’s Spreadtum will make mobile chips in Intel’s current 14nm process. In addition, Intel’s 14nm Stratix 10 FPGAs will sample next quarter using a novel packaging technology that provides a lower cost than existing 2.5D techniques.
The Intel 10nm node, still in a development stage, will sport a 54nm gate pitch. It’s the “tightest gate pitch any company will have in production for several years,” said Mark Bohr, a senior fellow in Intel’s manufacturing group.
Bohr said both Intel’s 10nm and 7nm processes will continue the trend of delivering both denser chips and a lower cost per transistor.
Both Intel’s 14 and 10nm nodes are expected to deliver tighter logic area and lower transistor cost than historic trends.
Tomi Engdahl says:
Laser Slicing to Slash SiC Wafer Costs, Boost Yield
http://www.eetimes.com/document.asp?doc_id=1330333&
Japanese ingot processing equipment manufacturer DISCO Corporation has unveiled a new laser-based technique to slice wafers out of a SiC ingot, producing 50% more wafers through reduced material losses while slashing production times by a factor of six.
Dubbed KABRA (for Key Amorphous-Black Repetitive Absorption), the patent-pending process uses a focused laser to form an amorphous layer of SiC decomposed into its constituents silicon (Si) and carbon (C), which becomes the base point for separating the wafer through cleavage.
While today’s wafer production typically involves the use of multiple diamond wire saws, taking several days to slice through an ingot and producing considerable material waste (about 200µm of material loss per wafer)
Tomi Engdahl says:
Oscilloscopes integrate with education
http://www.edn.com/electronics-products/electronic-product-reviews/other/4442554/Oscilloscopes-integrate-with-education?_mc=NL_EDN_EDT_EDN_productsandtools_20160822&cid=NL_EDN_EDT_EDN_productsandtools_20160822&elqTrackId=8c96f46f49334a08992f76744eb0d826&elq=7161632ed76c415f91f22646897efadc&elqaid=33547&elqat=1&elqCampaignId=29324
The low-end of the oscilloscope market bandwidth is still an extremely active segment. Working engineers, do-it-yourselfers, and educators use them every day. Because oscilloscopes of 100 MHz and lower bandwidth make such a large segment of the oscilloscope market, Tektronix has introduced the TBS2000 series, which consists of four models, two-channel four-channel at 70 MHz and 100 MHz.
The TBS2000 series basic specs are 1 Gsample/s sampling rate with 20 Msamples of waveform memory.
Because many low-bandwidth oscilloscopes are in the hands of students, makers, and casual users, these instruments include more than just the usual help menus. Yes, they have a “HelpEverywhere” feature that provides help for settings such as Acquire, Trigger, Vertical, Math, FFT, Cursor, Reference, Measurement, and Utility (you can turn HelpEverywhere off if you don’t need it). But they also include an integrated handbook that explains measurements in greater detail.
Designed partly as a teaching tool, the TBS2000 lets educators take advantage of the Tektronix Courseware Resource Center,
http://www.tek.com/courseware
Tomi Engdahl says:
VTT and the Dutch PhoeniX Software developed by the EU ACTPHAST project software tools for silicon photonics development. They can be implemented more easily fast data transfer solutions as well as sensors.
In Finland, VTT is one of the pioneers of silicon photonics development – already since 1997. Piifotoniikan design, manufacture and testing of methods have been developed by VTT, in close cooperation with customers and partners.
optical integrated circuits developed on a textured silicon wafers commercial Micronova state of Espoo, where the goal is also a significant commercial production.
VTT used three microns thick silicon light channels offer a combination of extremely dense integration, small attenuation and independence of polarization.
Source: http://www.uusiteknologia.fi/2016/08/23/uusia-tyokaluja-nopeaan-piifotoniikkaan/
Tomi Engdahl says:
Advances Get a Grip on Single Photons & Molecules
Single molecules & photons can be detected, emitted
http://www.eetimes.com/document.asp?doc_id=1330340&
The Moscow Institute of Physics and Technology (MIPT) is probing cutting edge diamond technologies to emit single photons (for uncrackable cybersecurity) and graphene to detect single molecules (for pathogen early detection). While experts around the world are also addressing these angstrom (one-tenth of a nanometer) scale problems, few laboratories are making headway in both.
Dmitry Fedyanin, a researcher from MIPT’s Laboratory of Nano-optics and Plasmonics together with his Italian colleague Mario Agio from the University of Siegen (Germany), may have cracked the most vexing problem in uncrackable quantum encryption. By using diamonds as high-speed emitters of single angstrom-scale quantum encoded photons they may have opened the door to high-intensity (that is high-speed of 100-MHz) quantum key communications.
“Our collaborative work is focused on the design and development of infrared single-photon sources, which provide high intensity of single-photon emission under electrical pumping, and are characterized by high energy efficiency and work at room- and high- temperatures alike,” Fedyanin told EE Times in an exclusive interview.
Today single-photon sources for uncrackable encryption keys, such as quantum dots, operate at extremely low rates — just a few photons per second — making their light extremely dim.
Tomi Engdahl says:
Semiconductor Horizon Gets Wider
http://www.eetimes.com/author.asp?section_id=36&doc_id=1330347&
Semiconductors are pivoting again, and the space is exploding.
As someone who’s been involved with semiconductor flows from front to back over the years, I’m observing a profound shift. Many tremendous opportunities in semiconductors – nascent just a short while ago – are suddenly coming into focus.
When I started in the industry over 35 years ago, we were building chips for mainframes. Today, semiconductors and the applications they enable are moving into every industry verticals that were unimaginable just a short while ago.
Today we are finding that the sky is no longer the limit. Here are a few of my views on the current horizon.
Semiconductors heading into new industry verticals will require a different approach than in the past, demanding some level of understanding to meet each vertical’s needs. In each, optimization of critical factors such as performance, functionality, reliability and cost for specific industries will be essential.
With each industry, we will be picking the best technologies to fit the needs – this includes re-using older process nodes or increasingly more powerful reconfigurable interconnects.
On the production side, the need for low-cost, low-power, low-level processing at the edge will send us back to using older process nodes. The cool upshot of the Internet of Things, for instance, is that we can dust off old fabrication designs that are good enough for edge-of-network sensors. IoT can go crazy on something we developed 10 years ago.
Lifecycle also plays a part. For example, those designing in spaces such as automotive must learn how to embrace innovation within longer overall hardware lifecycles.
Security is likely to get baked in at every level. The need for security is rising as applications move into a real world where cars crash and industrial control technologies get hacked with people’s lives at stake.
Every vertical has different requirements and we’re going to need specialists in each one
Tomi Engdahl says:
19 Views of IDF16
PC giant aims to play a new tune
http://www.eetimes.com/document.asp?doc_id=1330332&
Whether Intel can remain the world’s largest semiconductor company in the wake of the PC tsunami is anyone’s guess. But there’s no doubt the company is trying to move fast on multiple fronts to participate in a richly diverse set of opportunities ahead.
This year’s Intel Develop Forum showed the company racing to get traction with a broad set of new platforms in machine vision, the Internet of Things, FPGAs, machine learning and more. None of them will replace the PC, but some collection of them could someday more than fill that gap.
Analysts’ opinions were mixed. In a research note entitled, “Battleship is turning,” Ross Seymore of Deutsche Bank said he was “impressed by Intel’s commitment to move beyond its PC heritage into a wide array of new markets … this transition will become increasingly apparent in 2017 as PC-related revs fall to ~50% of the company’s mix.
He and others praised the company for an update on its 10nm node that showed “its ability to keep pace with Moore’s law when others have found doing so more difficult.”
PC was probably was “the most important design win of all time…but it’s not clear IoT will be the same horn of plenty…I think ARM is going to be the long term winner in IoT,”
Tomi Engdahl says:
Renesas Sets Sights on Intersil
http://www.eetimes.com/document.asp?doc_id=1330343&
The Japanese economic newspaper Nikkei, reported early Monday that Renesas Electronics is “in the final stages of negotiations to acquire Intersil.”
The genesis of the deal is believed to be Renesas’ desire to bolster its position in the global automotive chip market.
Renesas, which held the number one position in the automotive semiconductor market in 2014, fell back to the third place in 2015, behind NXP Semiconductors, which merged with Freescale in 2015, and Infineon.
Tomi Engdahl says:
Advances Get a Grip on Single Photons & Molecules
Single molecules & photons can be detected, emitted
http://www.eetimes.com/document.asp?doc_id=1330340&
Tomi Engdahl says:
Stepping Back From Scaling
http://semiengineering.com/stepping-back-from-scaling/
New architectures, business models and packaging are driving big changes in chip design and manufacturing.
Architectures, packaging and software are becoming core areas for semiconductor research and development, setting the stage for a series of shifts that will impact a large swath of the semiconductor industry.
This is evident in TSMC’s earnings reports, which show a general downward trend for revenue obtained from advanced nodes over the past eight years. TSMC is by far the largest foundry with 54.3% market share, according to Gartner, although it is not the only foundry manufacturing chips at the latest process nodes, or the only one seeing this shift.
Even Intel, which has been an unwavering proponent of Moore’s Law and its two-year cadence, said last week it will increase the amount of time between nodes—essentially turning the “Tick-Tock” strategy it defined at the turn of the Millennium into Tick-Tock-Tock.
“Moore’s Law is slowing down,”
“The necessity for moving to 28nm, and 28nm pricing, is still high,”
Meanwhile, GlobalFoundries and Samsung have developed 28nm FD-SOI planar processes to control current leakage, which has been a persistent design issue after 55nm.
Plenty of options for most companies
While this may limit how quickly advanced processor and large FPGA vendors move forward, for the vast majority of semiconductor companies the decision about what to do after 28nm is still several years out. Many chips, particularly analog, are being developed at 250nm or larger. Mainstream chips for the IoT, automotive, and a number of other vertical markets currently are somewhere between 130nm and 40nm. Even for chipmakers working at 40nm, 28nm is just one more shrink along a well-defined path, with the same economies of scale and power/performance improvements that previous nodes provided. The 28nm node still uses planar transistors, rather than finFETs, and only requires single patterning.
Tomi Engdahl says:
Can Analog And Digital Get Along Better?
http://semiengineering.com/can-analog-and-digital-get-along-better/
Combining both in a mixed-signal design brings challenges in a different realm. Expertise is the key to success.
How to bridge analog and digital is getting renewed attention as the amount of analog content that needs to be processed balloons with consumer and industrial IoT applications.
Solving that problem isn’t going to be easy, though. To begin with, digital designers view designs in terms of voltages. Analog designers, in contrast, look at currents.
“Unless you can analyze an analog circuit and understand those electrons and the motion of the currents, it’s difficult to get it right,” said Sundari Mitra, CEO of NetSpeed Systems and an analog engineer by training. “More for analog than for digital, a CAD tool will help create bad designs if you don’t have your fundamentals clear.”
Even with tools that address both markets, this combination isn’t always clear.