Chip Market Brightens in 2017. The semiconductor industry may yet have been flat in 2016, but expects it is expected that the electronics industry rebounds in 2017, probably in the first half. Wall Streeter predicts return to 5% growth. Total IC business growth is expected to be around five percents for few years to come.There seems to several promises to this direction, especially in memory business. Chips Execs See Maturing Industry article says that pessimism about immediate revenue and R&D growth is a sign of a maturing industry.
Thanks to both rising prices and volume sales, the memory sector is expected to lead overall semiconductor sales growth. Sales of memory chips will increase 10% next year to a new record high of $85.3 billion, according to the latest report from IC Insights. NAND flash will grow almost as fast at 10% next year. The average annual growth rate for the memory market is forecast to be 7.3% from 2016-2021. Every year we need 5.6% more bits than previous year, and the unit prices are increasing on both DRAM and Flash.
There will be also other growth sectors. The data center will be the fastest growth segment next year, rising 10%, followed by automotive at 9% and communications at 7%. Consumer and industrial markets growing at about 4% in line with the overall industry. PCs will be the big drag on 2017, declining 2%.
China Dominates Planned Chip Fabs as more than 40% of front end semiconductor fabs scheduled to begin operation between 2017 and 2020 are in China, a clear indication that China’s long-stated ambition to build a significant domestic semiconductor industry is taking shape.
Trump Win Could Mean Big Questions for Manufacturing as while Trump vowed to keep American manufacturing jobs, he offered little in the way of stated policy other than the promise to punish companies that sent manufacturing job outside the US. Questions about trade also could directly affect US manufacturing. How that plays out is a big unknown.
Europe will try to advance chip manufacturing, but not much results in 2017 as currently there is almost no leading-edge digital chip manufacturing left in Europe as the local companies have embraced outsourcing of digital semiconductor manufacturing to foundries. The European Commission intends to reconvene a high-level group of European CEOs and executives to exchange views on Europe’s 10/100/20 nanoelectronics and chip manufacturing project and make adjustments as necessary for a wave of European Union investment supposedly starting in 2020. The two most advanced wafer fab locations left in Europe in terms of deep sub-micron miniaturization belong to Intel in Leixlip, Ireland and Globalfoundries in Dresden, Germany.
Smaller geometries are to be taken into use and researched in 2017. Several chipmakers ramp up their 10nm finFET processes, with 7nm just around the corner. As TSMC, GF/Samsung Battle at 7nm the net result is in the course of 18 months chip designers will see at least three variants of 7nm — separate immersion variants from TSMC and Globalfoundries and the EUV version from GF/Samsung. Intel has yet to detail its 7nm node.
At the same time R&D has begun for 5nm and beyond, but Uncertainty Grows For 5nm, 3nm as costs are skyrocketing. Both 5nm and 3nm present a multitude of unknowns and challenges. To put this in perspective, there are roughly two silicon atoms in 1nm of line width in a chip. Etching Technology Advances as atomic layer etch (ALE) moves to the forefront of chip-making technology—finally. TSMC recently announced plans to build a new fab in Taiwan at a cost of $15.7 billion targeted for TSMC’s 5nm and 3nm processes, which are due out in 2020 and 2022.
Moore’s Law continues to slow as process complexities and costs escalate at each node. Moore’s Law is dead, just not in the way everyone thinks. SiFive believes open source hardware is the way forward for the semiconductor industry. Technological advances keep allowing chips to scale, but the economics are another story – particularly for smaller companies that can’t afford chips in the volumes. The solution, according to San Francisco-based startup, SiFive, is open-source hardware, specifically an architecture developed by the company’s founders called RISC-V (pronounced “risk-five”). Done right SiFive, which was awarded Startup of the Year at the 2016 Creativity in Electronics (ACE) Awards, believes that RISC-V will do for the hardware industry what Linux has done for software. For example 5th RISC-V Workshop Points to Growing Interest in the RISC-V Platform.
Sensors are hot in 2017. These tiny, powerful solutions are creating the interface between the analog and the digital world. Data is everywhere, and sensors are at the very heart of that. While no one really knows what technology’s next “killer application” will be, we are confident that any killer app will rely on sensors.Appliance autonomy promises to make life simpler, but this field has still lots of to improve even after year 2017.
Interface ICs will continue to help simplify high-bandwidth designs while making them more robust and reliable. Application areas that will benefit include automotive, communications, and industrial. Both wired and wireless interface solutions have plenty of applications.
Analog’s status is rising as more sensors and actuators are added into electronic devices, pressure is growing to more seamlessly move data seamlessly back and forth between analog and digital circuitry. IoT pushes up demand for analog content and need for communication between these two worlds will continue to grow. Analog and digital always have fit rather uncomfortably together, and that discomfort has grown as SoCs are built using smaller feature sizes. The demand for analog silicon has always existed in the embedded space, but the advent of the Internet of Things (IoT) is increasing the demand for connected mixed-signal content. At 28nm and 16/14nm, standard “analog” IP includes a fair amount of digital content.
It seems that hardware designer is a disappearing resource and software is the king in 2017. It is becoming less and less relevant in what format the device is used in many applications. Card computers are standard products and are found in many different card formats that can be used in very many applications. Embedded development is changing to more and more coding. More software designers that understand some hardware are needed, but it is not easy to leap to move to the hardware to software.
The power electronics market is moving at very fast pace. Besides traditional industrial, renewable, and traction sectors, new applications such as energy-storage systems, micro-grids, and dc chargers are emerging. As the automotive world moves to electric vehicles, this creates challenges for IGBT and SiC-MOSFET ICs, and their associated gate drivers. New packages for high-voltage IGBTs and high-voltage SiC-MOSFETs are introduced.
More custom power distribution and higher voltages on data center computer systems in 2017. OpenRack and OpenCompute projects are increasing the distribution voltage inside the server itself. This approach, plus transitioning to new materials such as gallium nitride in the power-conversion systems, can reduce overall power consumption by 20% and increase server densities by 30-40%.”
Power Modules and Reference Designs will be looked at in 2017 even more than earlier in power electronics. The semiconductor and packaging technologies used in power modules have advanced considerably, and the industry is developing modules today that are denser, less expensive, and easier to use. Designers want to rely on power modules to speed up designs and optimize space using smaller, easy-to-use power modules. Module manufacturers hope that engineers will increasingly choose a module over a discrete design in many applications.
The bi-directional DC/DC converter has been around for a while, but new applications are quickly emerging which necessitate the use of this architecture in so many more systems. Battery back-up systems need bi-directional DC/DC converters. Applications today require better energy efficiency and such systems as green power with solar or wind generation, need storage so that when there is no wind or sun available the electricity flow is not interrupted.
Power supplies need to become more efficient. Both European Union’s (EU) Code of Conduct (CoC) Tier 1 and CoC Tier 2 efficiency standards are to be taken into use. The European Union’s CoC Tier 1 effectively harmonizes the EU with US DoE Level VI and became effective as a voluntary requirement from January 2014, two years ahead of Level VI. Its adoption as an EU Ecodesign rule is currently under review to become law with an implementation date of January 2017. The key difference between the CoC requirements and Level VI is the new 10% load measure, which imposes efficiency requirements under a low-load condition where historically most types of power supplies have been notoriously inefficient. CoC Tier 2 further tightens the no-load and active mode power consumption limits.
During 2016, wireless-power applications started to pick up across many fields in the semiconductor industry, and it will continue to do so. Wireless power will continue to gain traction with increased consumer demand. Hewlett Packard, Dell, jjPlus, and Witricity have already announced products based on Airfuel standards. And, products based upon the Qi standard will continue to grow at a rapid pace.
Other prediction articles:
In Power & Analog 2017 Forecast: What Experts Are Saying article representatives from major players in the semiconductor industry share their predictions for 2017 regarding power modules, wireless power, data converters, wireless sensing, and more.
Looking Ahead to 2017 article tells on to what SIA is focused on working with. “U.S. semiconductor technology should be viewed as a strategic national asset, and the Administration should take a holistic approach in adopting policies to strengthen this vital sector,” the letter says
Hot technologies: Looking ahead to 2017 article collection has EDN and EE Times editors explore some of the hot technologies in 2017 that will shape next year’s technology trends and beyond.
1,115 Comments
Tomi Engdahl says:
Chip Consolidation Nearly Over, Analyst Says
http://www.eetimes.com/document.asp?doc_id=1332297&
After about three years and hundreds of billions of dollars in mergers and acquisitions, the consolidation of the global semiconductor industry is pretty much finished, according to Bill Wiseman, a senior partner with management consultancy McKinsey.
“The issue is that there aren’t a whole lot of deals left,” said Wiseman, who prior to joining McKinsey in 2001 was designing mixed-signal integrated circuits for IBM and before that was a U.S. Navy Seal. “There aren’t that many deals left because there aren’t that many attractive targets out there.”
Most of the consolidation has been based on cost and synergy, Wiseman said at the grand opening keynote session of Semicon Taiwan this week. The industry has been in a slow-growth rut for quite a long time, he added.
Those doldrums may be past as the outlook is for overall industry revenue to soar to $400 billion this year from $339.7 billion in 2016, and consolidation starts to pay off, Wiseman said. For the first time in years, semiconductor prices are increasing, and that doesn’t just mean memory chips, he said.
“Because of consolidation, we’re seeing rising prices for mature products,” according to Wiseman.
One measure of the health of the industry is the R&D cost-to-revenue ratio, which even after the recent buying spree remains very stable at around 14 to 15 percent. If it gets to 17 percent, chip suppliers need to raise prices, “and this is an industry that doesn’t like that — unless you’re a memory provider,” Wiseman quipped.
Now may be a time for the acquirers in the chip industry to sit back and digest the companies they’ve gobbled up.
“Most of the companies that felt confident to make acquisitions are busy integrating the companies they bought,”
Deals Still on the Table
Some deals still on the table may spell the end for the industry M&A activity, based on the McKinsey outlook.
Toshiba’s lucrative NAND flash memory business remains a hotly pursued quarry for several groups led by Bain Capital, Western Digital and Foxconn. Apple continues to be an active player in the bidding, according to Bloomberg.
There’s also Qualcomm’s plan to acquire NXP for a price of $110 a share, or a total of $38 billion in cash.
Tomi Engdahl says:
What’s After 7nm?
Power and performance will continue to improve, but not necessarily because everything is smaller.
https://semiengineering.com/whats-after-7nm/
The rollout of 10/7nm was a long time coming, and for good reason. It’s hard stuff, and chipmakers have to be ready to take a giant step forward with new processes, tools, and to deal with a slew of physical effects that no longer can be handled by just guard-banding a design.
The big question is what’s next, when it will happen, and how much it will cost. Preparing for the next process node is no longer an automatic progression. It takes time, equipment, and it requires dealing with an ever-expanding list of new issues.
It’s important to clarify who’s defining node numbers, too. The 7nm node introduced by TSMC and Samsung is roughly the equivalent of 10nm as defined by Intel and GlobalFoundries. Each new node represents roughly a doubling of transistors.
Tech Talk: 7nm Thermal Effects
The impact of heat on reliability at advanced nodes and in automotive electronics.
https://semiengineering.com/tech-talk-7nm-thermal-effects/
Tomi Engdahl says:
Multi-Physics Combats Commoditization
https://semiengineering.com/multi-physics-combats-commoditization/
In a world of billion-gate designs, it is increasingly difficult to create a differentiated product without incorporating multi-physics elements.
The semiconductor industry has benefited greatly from developments around digital circuitry. Circuits have grown in size from a few logic gates in the 1980s to well over 1 billion today. In comparison, analog circuits have increased in size by a factor of 10. The primary reason is that digital logic managed to isolate many of the physical effects from functionality, and to provide abstractions that made fast analysis and automation possible.
But all of that has stopped. The advantages of each new node are decreasing and raw transistor count has stopped being a way to differentiate one design from another. Even going to the latest node does not escape the need to take on multi-physics problems.
Tomi Engdahl says:
Frenzy At 10/7nm
Focus is on cutting costs across the board, and it turns out there is still quite a bit to cut.
https://semiengineering.com/the-rush-to-107nm/
The number of chipmakers rushing to 10/7nm is rising, despite a slowdown in Moore’s Law scaling and the increased difficulty and cost of developing chips at the most advanced nodes.
How long this trend continues remains to be seen. It’s likely that 7/5nm will require new manufacturing equipment, tools, materials and transistor structures. Beyond that, there is no industry-accepted roadmap, making the future far murkier than at past nodes. But at least for now, more companies are betting big on 10/7nm than anyone would have anticipated several years ago—and that is not a decision anyone is taking lightly.
“Before 28nm, companies may have done less business analysis to determine if the business case for making a node-over-node jump made sense,”
Tomi Engdahl says:
MicroLED Pits Big Apple vs. Tiny LED Chips
Does microLED even exist? Why do we care?
http://www.eetimes.com/document.asp?doc_id=1332298
Differentiating one smartphone from another is no easy feat. A display, however, is the one constant that smartphone vendors believe they can depend on to wow their customers. A new display technology with visible differences in a screen size, resolution, brightness and power consumption could scramble the market.
Apple’s anxiously awaited iPhone X, unveiled just this week, is the first iPhone to feature an OLED display — long after competitors Samsung and LG brought to market smartphones with OLED. Of course, unlike Samung and LG, Apple doesn’t have its own display technology. Yet.
What if Apple were to develop a display technology of its own, featuring all the advantages of OLED but even better … like microLED? While the company has remained tight lipped — as is its custom — Apple has amassed an impressive portfolio of micoLED patents and there is speculation that it is using a Silicon Valley fab it bought from Maxim in 2015 to develop the technology. And Apple isn’t the only big name tech company working on microLED.
MicroLED displays consist of an array of microscopic LEDs forming individual pixel elements. Unlike OLED, microLED uses conventional gallium-nitride LED technology.
MicroLED proponents claim their total brightness can be 30 times that of OLED products while offering higher efficiency in lux per watt.
Whether Apple will trigger the shift to microLED has long been a topic of intense discussion among Apple watchers and display technology experts, not to mention driven speculation that Apple would soon use microLED in Apple Watch.
Tomi Engdahl says:
TSMC Updates its Silicon Menu
First 7-nm chips, EUV migration described
http://www.eetimes.com/document.asp?doc_id=1332293
TSMC reported progress in 7 nm and extreme ultraviolet (EUV) lithography and bolstered a planar process that competes with fully depleted silicon-on-insulator at an annual event here. It also gave updates on its work in packaging and platforms for key market segments.
The foundry, celebrating its 30th anniversary, expects to tape out more than 10 7-nm chips this year and start volume production with the process next year. The chips include a quad ARM A72 core processor running at up to 4 GHz — possibly Huawei’s Kiron mobile processor — a CCIX development platform, and an unnamed ARM server processor.
Tomi Engdahl says:
Why Hardware Emulation’s OS is Like a Computer System
http://www.eetimes.com/author.asp?section_id=36&doc_id=1332292&
Mentor’s Charley Selvidge has been thinking that the operating system of a hardware emulator is a natural evolution of the way software systems are built for emulators.
All of this comes in handy as he explains the landscape of hardware emulation, something about which he knows a thing or two. In the late 1990s, Charley was a founder of Virtual Machine Works, which was located a stone’s throw from MIT in Cambridge, Massachusetts. VMW, as it was known, was acquired by IKOS Systems in 1998, which subsequently became part of Mentor in 2002.
He moves his analogy to emulators and notes: “They consist of a hardware execution platform at the bottom for running a model of a digital chip and a set of application-oriented tasks to run on the emulator.” These tasks often have high-level objectives, such as characterizing the amount of power a chip is consuming or processing a software application that runs on a processor inside the chip. In either case, the entire chip needs to be considered as part of the task.
Undeniably, he adds, these are high-level and complex tasks routinely performed by an emulator. A set of intermediate services standard to emulation inside of an operating system could insulate high-level tasks from the low-level, machine-specific details associated with emulation.
For this reason, Charley affirms, operating systems are an interesting concept for an emulator.
Hardware and software scalability in hardware emulation
All emulators are based on some kind of modeling component; that is, a device that can model a piece of a chip. A multitude of these modeling components are assembled together in a small, medium, or large number to build systems of various sizes. On top of this underlying hardware is a software compilation system. An emulation compiler reads in a database or model of an integrated circuit and writes out a datasteam that configures the array of modeling components in the emulator to form an image of the chip.
Typically, integrated circuits are designed via computer programs that execute a description of the circuit written in one of a few computer languages, generically called hardware description languages (HDLs). The most commonly used HDLs are Verilog, SystemVerilog, and VHDL. The circuit description defines the behavior of the circuit. These descriptions are synthesized into a real integrated circuit and compiled into a model that runs on an emulator.
According to Charley, with a model for a chip, the designer would load it onto the emulator, a machine-specific task performed by the emulator’s OS software.
Tomi Engdahl says:
Piezomagnetic Trick Shrinks 2.5 GHz Antennas
https://hackaday.com/2017/09/15/piezomagnetic-trick-shrinks-2-5-ghz-antennas/
To a ham radio operator used to “short”-wave antennas with lengths listed in tens of meters, the tiny antennas used in the gigahertz bands barely even register. But if your goal is making radio electronics that’s small enough to swallow, an antenna of a few centimeters is too big. Physics determines plausible antenna sizes, and there’s no way around that, but a large group of researchers and engineers have found a way of side-stepping the problem: resonating a nano-antenna acoustically instead of electromagnetically.
Acoustically actuated ultra-compact NEMS magnetoelectric antennas
https://www.nature.com/articles/s41467-017-00343-8
Tomi Engdahl says:
The DRAM memory was invented at the IBM Research Center in 1966. Since then, for almost 50 years, the technology has been the development of the semiconductor industry as defined by the PCs. This era is about to come to an end as NAND flash sales will overtake DRAM sales in 2020.
According to the ChinaFlashMarket report, NAND memories will account for more than half of the memory market in 2020. This year, chip shops will be sold for a total of $ 95 billion, by 2020 over 120 billion.
This year, 43 percent of NAND circuits are implanted on SSDs. Embedded memories – for example smart phones – are 42 percent of chips.
This year NAND circuits are sold for $ 40 billion.
Source: http://etn.fi/index.php?option=com_content&view=article&id=6845&via=n&datum=2017-09-15_15:03:56&mottagare=30929
Tomi Engdahl says:
NEW! Isolated Measurement Systems
https://www.tek.com/isolated-measurement-systems
Whether designing an inverter, optimizing a power supply, testing communication links, measuring across a current shunt resistor, debugging EMI or ESD issues, or trying to eliminate ground loops in your test setup, common mode interference has caused engineers to design, debug, evaluate, and optimize “blind.”
Revolutionary IsoVu™ technology uses optical communications and power-over-fiber for complete galvanic isolation.
Tektronix IsoVu Measurement System White Paper
https://www.tek.com/document/whitepaper/tektronix-isovu-measurement-system-white-paper
Tomi Engdahl says:
TSMC Teams Up with ARM and Cadence to Build 7nm Data Center Test Chips in Q1 2018
by Anton Shilov on September 14, 2017 11:45 AM EST
https://www.anandtech.com/show/11832/tsmc-teams-up-with-arm-and-cadence-to-build-7-nm-chip-in-q1-2018
TSMC has announced plans to build its first test chips for data center applications using its 7 nm fabrication technology. The chip will use compute cores from ARM, a Cache Coherent Interconnect for Accelerators (CCIX), and IP from Cadence (a DDR4 memory controller, PCIe 3.0/4.0 links). Given the presence of the CCIX bus and PCIe 4.0 interconnects, the chip will be used to show the benefits of TSMC’s 7 nm process primarily for high-performance compute (HPC) applications. The IC will be taped out in early Q1 2018.
The 7 nm test chips from TSMC will be built mainly to demonstrate capabilities of the semiconductor manufacturing technology for performance-demanding applications and find out more about peculiarities of the process in general. The chip will be based on ARMv8.2 compute cores featuring DynamIQ, as well as a CMN-600 interconnect bus for heterogeneous multi-core CPUs. ARM and TSMC do not disclose which cores they are going to use for the device – the Cortex A55 and A75 are natural suspects, but that’s a speculation at this point.
Tomi Engdahl says:
AI Reshaping Fab Operations
http://www.eetimes.com/document.asp?doc_id=1332302&
Chipmakers are adopting artificial intelligence to boost fab operations, an effort that is starting to pay off, according to Micron Technology.
Fab managers need to juggle fluid customer demand while simultaneously implementing constantly changing process technologies in multiple manufacturing sites around the globe. All this happens as chipmakers aim to achieve yield and quality targets on a corporate level as quickly as possible, according to Buddy Nicoson, vice president of wafer fabs with Micron.
Tomi Engdahl says:
The U.S., China and the Chip Industry
http://www.eetimes.com/author.asp?section_id=40&doc_id=1332319
Beijing cried foul over Trump’s decision to block the acquisition of Lattice Semiconductor. It should be prepared for more of the same.
It comes as little surprise that last week’s decision by U.S. President Donald Trump to block the acquisition of Lattice Semiconductor by an equity firm funded partly by the Chinese government ruffled a few feathers in China.
According to the state run news agency Xinhua, a spokesman for China’s Ministry of Commerce balked at the decision, telling reporters at a press conference that foreign governments shouldn’t use government review of acquisitions to implement protectionism under the guise of protecting national security.
Tomi Engdahl says:
Fab Tool Spending on Pace to Shatter Record
http://www.eetimes.com/document.asp?doc_id=1332323&
In what is shaping up to be a banner year for the semiconductor equipment industry in every way measurable, combined spending on new and refurbished fab tools is not expected to shatter a six-year-old record.
Total fab equipment spending is expected to grow 37 percent this year to reach $55 billion, according to the latest forecast from the SEMI trade association. This would obliterate the previous record for combined spending on new and refurbished equipment of $40 billion set in 2011.
SEMI expects fab tool spending to increase by another 5 percent next year to reach $58 billion.
Tomi Engdahl says:
NOR Flash Standard Meets Instant-On Expectations
http://www.eetimes.com/document.asp?doc_id=1332320&
Jedec’s new xSPI standard for non-volatile memory (NVM) devices is aimed meeting the demands of instant-on applications while also maintaining performance standards for NOR flash sitting outside of the SoC.
Adesto Technologies, known for its small, ultra-low power NVM products, is claiming to be first out the gate, having been working on products and collaborating on the standard for the past three years. In a telephone interview with EE Times, Adesto Chief Techology Officer Gideon Intrater said its eXecute-in-Place (XiP) EcoXiP product family takes advantage of the new Jedec standards to give customers such as system developers and controller designers assured compatibility with controllers and peripheral devices that should accelerate adoption.
Developed by a task force comprised of representatives from most NOR flash device manufacturers and several PC and microcontroller companies, the xSPI standard establishes mechanical, electrical and transactional guidelines for developing high-throughput octal devices.
NOR flash is “old in the tooth,” he said, but it’s made progress in terms of process technology and the about amount of bandwidth that you go can get out of devices has improved dramatically in the last decade. Recently emerged applications such as the Internet of Things (IoT) and automotive infotainment systems have created a great deal of demand for embedded devices that need more program memory than what can be implemented economically on-chip using embedded flash or SRAM.
Tomi Engdahl says:
7 Good Reasons Why You Should Use Integrated Load Switches
http://www.electronicdesign.com/power/7-good-reasons-why-you-should-use-integrated-load-switches?NL=ED-003&Issue=ED-003_20170920_ED-003_50&sfvc4enews=42&cl=article_1_b&utm_rid=CPG05000002750211&utm_campaign=13071&utm_medium=email&elq2=1f786a87c302472a8784b512e6c843b1
Sponsored by: Texas Instruments. Before turning to integrated load switches for your application, it’s a good idea to have a fundamental understanding of these devices in comparison to their discrete-component brethren.
A load switch is simply a switch, mechanical or electronic, that connects or disconnects a load to the high side of a power source. A wall light switch is a load switch. Any off/on switch on an appliance or electronic product is a load switch. A relay can be a load switch.
However, a load switch is also a small electronic switch used in many products to configure and manage power distribution. You can make a load switch with discrete components, but there are significant advantages to using a fully integrated IC load switch. This article presents an option you may not know is available.
Figure 1 shows the simple idea of a load switch, where a power source provides a voltage to one or more loads. The switches are controlled by a microcontroller unit. The source is typically dc, but an ac source is possible. Different types of load switches are used for dc and ac
Tomi Engdahl says:
How to Test Switched-Mode Power Devices
This Design FAQ is brought to you by Continental Resources.
http://www.electronicdesign.com/test-measurement/how-test-switched-mode-power-devices
Tomi Engdahl says:
Manufacturing the Internet of Things
http://www.electronicdesign.com/iot/manufacturing-internet-things
IoT will impact the way products are developed and manufactured. In this paper we explore challenges that lie ahead and how to efficiently bring reliable products to market in this new reality.
The Internet of Things (IoT) applies to a vast number of industries and applications, everything from wearables, to city infrastructures and vehicles. IoT and the technologies that power it, as well as those yet to come present incredible opportunities, however, with this also comes complex challenges to efficiently bring reliable products to market. This paper discusses the test and measurement challenges that lie ahead and suggests a solution to reduce the time and cost of test development.
Tomi Engdahl says:
DDR5 Runs in Rambus’ Labs
Debate rises over next-gen memory interface
http://www.eetimes.com/document.asp?doc_id=1332322
Rambus has working silicon in its labs for DDR5, the next major interface for DRAM dual in-line memory modules (DIMMs). The register clock drivers and data buffers could help double the throughput of main memory in servers, probably starting in 2019 — and they are already sparking a debate about the future of computing.
The Jedec standards group plans to release before June the DDR5 spec as the default memory interface for next-generation servers. However, some analysts note it comes at a time of emerging alternatives in persistent memories, new computer architectures and chip stacks.
“To the best of our knowledge, we are the first to have functional DDR5 DIMM chip sets in the lab. We are expecting production in 2019, and we want to be first to market to help partners bring up the technology,” said Hemant Dhulla, a vice president of product marketing for Rambus.
DDR5 is expected to support data rates up to 6.4 Gbits/second delivering 51.2 GBytes/s max, up from 3.2 Gbits and 25.6 GBytes/s for today’s DDR4. The new version will push the 64-bit link down to 1.1V and burst lengths to 16 bits from 1.2V and 8 bits. In addition, DDR5 lets voltage regulators ride on the memory card rather than the motherboard.
In parallel, CPU vendors are expected to expand the number of DDR channels on their processors from 12 to 16. That could drive main memory sizes to 128 Gbytes from 64 GB today.
Tomi Engdahl says:
Bloomberg:
Toshiba agrees to sell memory chip unit to group led by Bain Capital for $18B; sources say Apple played a crucial role in swinging momentum to the Bain offer — Toshiba Corp.’s board has agreed to sell its flash memory chip unit to a group led by Bain Capital for 2 trillion yen ($18 billion) …
Bain-Led Group to Buy Toshiba Chip Unit in $18 Billion Deal
https://www.bloomberg.com/news/articles/2017-09-20/toshiba-agrees-to-sell-memory-chip-unit-to-bain-led-group
Tomi Engdahl says:
TSMC Process Roadmap Update
https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/archive/2017/09/15/tsmc-oip-17
During the last few days, we have put out many TSMC-related press releases: the CCIX test chip, 7nm and 7nm FinFET+, 12FFC, automotive IP on 16FFC, and TSMC’s 3D packaging technologies CoWoS and InFO (even the names are three dimensional with the careful mix of upper and lower-case letters).
he presentation was given by Cliff Hou, who is VP R&D for the Design and Technology Platform. Historically, until a few years ago, TSMC used mobile as their technology driver and other markets had to make do with whatever resulted from that. As the growth in mobile has slowed, TSMC is focusing on four segments with special technology options: mobile (still), high-performance computing (HPC), automotive, and IoT.
The main processes for each segment are:
Mobile: N7, N7+, and N12
HPC: N7, N7+
IoT: 22ULP 22ULL, but also 55ULP, 40ULP, 28HPC+, 16FFC
Automotive: 16FFC and N7, but also 65/40/28/22
Mobile Platform
N7 process qual is completed and risk start has commenced. The entire EDA flow is exercised and validated. Foundation IP is ready. Ecosystem IP already has some silicon validation. There have been multiple tapeouts already, with over 10 expected by the end of the year. Volume production starts in the first half of 2018.
N7+ is the second-generation 7nm process. It has 1.2X logic density of N7, 8-20% higher speed (at same power) or 15-20% lower power at the same speed. EUV is used on critical layers. The design rules are slightly different for EUV versus 193i, but TSMC has created a migration utility to automate design porting. The effort to port IP is “less than that from v0.5 to v1.0 was”.
Compared to 16FFC, N7 has a 33% speed increase or a 58% power reduction. Going from N7 to N7+ gets another 7% speed gain or another 16% power reduction.
12FFC is a fast PPA upgrade from 16FFC. It is an optical shrink. However, there is also a new 6T standard cell library, that pushes density up 1.2X vs the 7.5T library on 16FFC. v0.1 DRM/SPICE is issued. The V1.0 EDA certification is completed. The IP portfolio is recharacterized and revalidated. The PPA numbers have been confirmed with a customer design.
There are 10 tapeouts expected in 12FFC by the end of the year.
Tomi Engdahl says:
GlobalFoundries Adds 12LP Process for Mainstream and Automotive Chips; AMD Planning 12LP CPUs & GPUs
by Anton Shilov on September 21, 2017 7:00 AM EST
https://www.anandtech.com/show/11854/globalfoundries-adds-12lp-process-tech-amd-first-customer
GlobalFoundries on Wednesday announced its new 12LP (leading performance) fabrication process. The new manufacturing technology was designed to increase transistor density and improve frequency potential compared to GlobalFoundries’ current-gen 14LPP tech. The company expects the new process to be used by suppliers of various ICs (integrated circuits), including designers of CPUs and GPUs as well as developers of chips for automotive applications and telecommunication solutions. One of the first customers to adopt the 12LP fabrication process will be AMD.
GlobalFoundries’ 12LP manufacturing technology builds upon the company’s 14LPP process that has been used for high-volume manufacturing (HVM) since early 2016. Just like its direct predecessor, the 12LP relies on deep ultraviolet (DUV) lithography with argon fluoride (ArF) excimer lasers operating on a 193 nm wavelength. GlobalFoundries promises that its 12LP provides a 15% higher transistor density and enables a 10% higher frequency potential (at the same power and complexity) compared to “16/14nm FinFET solutions on the market today”. The company does not elaborate which process it used for comparison, but a naturally guess would be its own 14LPP which the company knows well.
Tomi Engdahl says:
Let’s Clear Up the Node Naming Mess
The Industry Needs a Standardized Density Metric to Show Where a Process Stands in Relation to the Moore’s Law Curve
https://newsroom.intel.com/editorials/lets-clear-up-node-naming-mess/
The industry needs a standardized density metric to level the playing field. Customers should be able to readily compare various process offerings of a chip maker, and those of different chip makers. The challenge is in the increasing complexity of semiconductor processes, and in the variety of designs.
One simple metric is gate pitch (gate width plus spacing between transistor gates) multiplied by minimum metal pitch (interconnect line width plus spacing between lines), but this doesn’t incorporate logic cell design, which affects the true transistor density. Another metric, gate pitch multiplied by logic cell height, is a step in the right direction with regard to this deficiency. But neither of these takes into account some second order design rules. And both are not a true measure of actual achieved density because they make no attempt to account for the different types of logic cells in a designer’s library. Furthermore, these metrics quantify density relative to the previous generation. What is really needed is an absolute measure of transistors in a given area (per mm2). At the other extreme, simply taking the total transistor count of a chip and dividing by its area is not meaningful because of the large number of design decisions that can affect it – factors such as cache sizes and performance targets can cause great variations in this value.
Tomi Engdahl says:
Node Warfare?
https://semiengineering.com/node-warfare/
GlobalFoundries unveils 12nm finFET process; foundries jockey for position on way to next full node.
GlobalFoundries uncorked a 12nm finFET process, which the company said will provide a 15% increase in density and more than 10% improvement in performance over the foundry’s existing 14nm process.
This is GlobalFoundries’ second 12nm process. It announced a 12nm FD-SOI process called 12FDX last September, although it first mentioned a 12nm process back in July of last year.
The announcement adds to the flood of process node numbers in semiconductor manufacturing these days. The reasoning behind all of this activity is that even though 7nm—the next full node—will be introduced next year, it will take time before that process is mature enough for commercial production. Foundries are trying to provide enough options to hold onto existing customers until that happens, while also tapping potential customers in new markets.
The new business involves sectors such as automotive, IoT, communications infrastructure, and artificial intelligence/machine learning. GlobalFoundries, for example, is taking aim at the automotive and RF/analog markets with its new process. The 12LP process is expected to meet Automotive Grade 2 qualification next quarter, which under AEC-Q100 means it will operate at temperatures between -40°C and +105°C, and it is being targeted for transceivers in 6GHz wireless networks.
Intel’s 14nm process, for example, has double the number of transistors as TSMC’s 16nm, while Intel’s 10nm process is roughly the same as TSMC’s forthcoming 7nm.
Tomi Engdahl says:
Challenges Mount For Photomasks
https://semiengineering.com/challenges-mount-for-photomasks/
Optical proximity correction, EUV pellicles, inverse lithography and actinic inspection make it hard to achieve a return on investment at advanced nodes.
Tomi Engdahl says:
What Happened To ReRAM?
https://semiengineering.com/what-happened-to-reram/
After years of delays, this next-gen memory is finally gaining traction.
Resistive RAM (ReRAM), one of a handful of next-generation memories under development, is finally gaining traction after years of setbacks.
Fujitsu and Panasonic are jointly ramping up a second-generation ReRAM device. In addition, Crossbar is sampling a 40nm ReRAM technology, which is being made on a foundry basis by China’s SMIC. And not to be outdone, TSMC and UMC recently put ReRAM on their roadmaps and are developing the technology for customers within the next year or so.
ReRAM had been touted for years as a replacement for NAND and other traditional memories, but ReRAM has proven to be far more difficult to develop than anyone initially expected. Moreover, NAND has scaled farther than previously thought, causing many to delay or scrap their efforts in ReRAM.
Tomi Engdahl says:
Unsolved Litho Issues At 7nm
https://semiengineering.com/unsolved-litho-issues-at-7nm/
Computational challenges on the rise with EUV. Scanners are no longer interchangeable.
While lithography is viewed as a single technology, EUV actually is a collection of technologies. Not all of those technologies have advanced equally and simultaneously, however. For example, aberrations in the mirror used to reflect the EUV laser beam can result in high background flare. Likewise, imperfections in the lens through which that beam is focused, or other impurities anywhere in the complex array of technologies, can result in surface roughness on the wafer. Add to that photon shot noise, overlay issues, and it’s daunting to get these systems to work at all, let alone consistently.
These issues are diverse, and none individually is a showstopper, but their impact can be cumulative.
Tomi Engdahl says:
Power SiC for Everyone
NCSU tests low-cost PRESiCE process at TI’s X-Fab
http://www.eetimes.com/document.asp?doc_id=1332326&
Silicon carbide (SiC) — a wide-bandgap semiconductor — creates power transistors that are today’s premium alternative to silicon power transistors when paired with a diode to provide the lowest-temperature, highest-frequency power devices available. SiC transistors produce 30 percent less heat than silicon power transistors, but thus far SiC’s higher performance comes at roughly five times the price of silicon.
North Carolina State University (NCSU) professor Jay Baliga argues that proprietary SiC processes have kept prices high and erected barriers to entry. Looking to lower those barriers with a process that can be licensed at low cost, Baliga and his research colleagues devised the Process Engineered for Manufacturing SiC Electronic-devices (PRESiCE) and worked with Texas Instruments’ X-Fab to implement it. T
Tomi Engdahl says:
AMD Copilots Tesla AI Chip, Says Report
http://www.eetimes.com/document.asp?doc_id=1332331&
Tesla is testing samples of a machine-learning chip that it developed in collaboration with Advanced Micro Devices, according to a report from CNBC. AMD and Tesla both declined to comment on the story.
The chip was developed by Tesla’s Autopilot group, a team of about 50 engineers under Jim Keller, a veteran microprocessor designer who led work on AMD’s Zen x86 processor. The chip is expected to replace an Nvidia GPU that Tesla currently uses, which itself replaced a Mobileye chip, said the CNBC report.
Tomi Engdahl says:
Globalfoundries Reportedly Asks EU to Probe TSMC
http://www.eetimes.com/document.asp?doc_id=1332334&
Globalfoundries has asked European regulators to investigate rival chip foundry TSMC, accusing its larger competitor of unfair competition, according to a report by the Reuters news service.
Globalfoundries (Milpitas, Calif.) has claimed to the EU’s legislative and regulatory arm, the European Commission, that TSMC unfairly uses loyalty rebates, exclusivity clauses and bundled rebates as well as penalties to discourage customers from switching to rivals, according to the report, which cites an anonymous semiconductor industry source.
A spokesman for Globalfoundries said the company is not surprised to learn that the European Commission is investigating allegedly anti-competitive behavior by TSMC, which has “a virtual lock” on supply.
“It’s prudent for the regulator to monitor behaviors more closely and Globalfoundries will naturally support regulatory agencies as they take a closer look at this key industrial sector for Europe and the world,” the spokesman said in an emailed statement.
TSMC did not immediately respond to a request for comment by EE Times.
Tomi Engdahl says:
7 Views of Globalfoundries in 2017
Masks are top EUV challenge at 7 nm
http://www.eetimes.com/document.asp?doc_id=1332328
Tomi Engdahl says:
Winner-Takes-All Strategy at Customers’ Expense?
http://www.eetimes.com/author.asp?section_id=36&doc_id=1332330&
Competitors, partners, and customers in our interdependent semiconductor industry often have mutual interests that could benefit from cooperation. By offering customers efficiency, we’d all win. Sadly, that’s not how things often work.
Tomi Engdahl says:
Tim Bradshaw / Financial Times:
Imagination Technologies agrees to sell to China-backed private equity firm Canyon Bridge for £550M; its US-based MIPS unit sold to Tallwood VC for $65M
Imagination Technologies agrees £550m sale to Canyon Bridge
https://www.ft.com/content/931719d6-9fdc-11e7-9a86-4d5a475ba4c5
Sale of UK chipmaker comes after share slump following loss of Apple contract
Tomi Engdahl says:
Increasing efficiency of offline flyback power conversion
https://www.edn.com/electronics-products/electronic-product-reviews/other/4458846/Increasing-efficiency-of-offline-flyback-power-conversion
Designers of the next generation of Power Integrations’ InnoSwitch have somehow managed to improve the efficiency of power adapters to a level of 94%.
Let’s look at some history and put that efficiency in perspective before we can appreciate how significant this level of efficiency is. Legacy adapters have an 87% full load efficiency rating; that is the government spec right now for a 30W, 19V, rectangular adapter with 230VAC input. With a little bit of design expertise, a designer may get up to around 90% efficiency, a 3% improvement on the government spec, which is considered a ‘high efficiency’ design. In 2014, Power Integrations introduced an InnoSwitch version that could achieve 92%.
Small efficiency improvements lead to significant size reductions. Surface area shrinks as the square of efficiency improvement and volume as the cube.
Cell phone companies do not want a cell phone adapter to be the size of a notebook adapter; this type of adapter needs to remain small and lightweight, but with more power output being demanded by the industry.
Tomi Engdahl says:
RS-485 transceiver boasts high isolation
https://www.edn.com/electronics-products/other/4458818/RS-485-transceiver-boasts-high-isolation
Intersil’s ISL32741E RS-485 differential bus transceiver offers a working voltage of 1000 V RMS and reinforced isolation of 6 kV—two times higher than competitive parts, according to the manufacturer. The transceiver also furnishes 12.8 kV of surge immunity. A second device, the ISL32740E has a working voltage of 600 V RMS and isolation of 2.5 kV.
Tomi Engdahl says:
Magnetic sensors are feature-rich
https://www.edn.com/electronics-products/other/4458817/Magnetic-sensors-are-feature-rich
Comprising three families, the Si720xx Hall-effect sensor portfolio from Silicon Labs combines very low power and high sensitivity. Add such features as I2C configurability, built-in tamper detection, and temperature sensing, and these magnetic sensors outclass reed switches and conventional Hall-effect devices in a wide range of open/close and position-sensing applications.
Si72xx series sensors can be used in battery-powered systems without impacting the system’s battery life. Operating below 100 nA (sleep current) and at less than 400 nA with a 5 Hz sampling rate
Prices start at $0.45 each in lots of 10,000 units.
https://www.silabs.com/products/sensors/magnetic
Tomi Engdahl says:
Automotive SMT fuses don’t explode
https://www.edn.com/electronics-products/other/4458871/Automotive-SMT-fuses-don-t-explode
AEM’s new QA F and QF H fuses range from 0603 to 2410 packaging, and are engineered to blow cleanly and predictably when used within specs, especially important when used in electric vehicle battery systems.
Tomi Engdahl says:
China-Backed Fund Canyon Bridge to Buy Imagination
http://www.electronicdesign.com/embedded-revolution/china-backed-fund-canyon-bridge-buy-imagination?NL=ED-003&Issue=ED-003_20170925_ED-003_304&sfvc4enews=42&cl=article_1_b&utm_rid=CPG05000002750211&utm_campaign=13165&utm_medium=email&elq2=837b0d9d788342eaa2113e01caeb7ae6
Canyon Bridge – a private equity firm that raised funds tied to the Chinese government, plotted to buy Lattice Semiconductor for $1.3 billion, stumbled into a venomous proxy battle with another chipmaker, and appealed to President Trump to approve the deal after regulators rejected it twice – is moving onto another target.
On Friday, the financial firm said that it would pay around $742.5 million for the tattered remains of Imagination Technologies, which licenses graphics and video-processing technology to chip companies. Graphics chips were invented for rendering video games but are now used to run artificial intelligence tasks like image recognition.
Tomi Engdahl says:
Massive revenues from RAM, flash make Micron chief a happy chappy
Mehrotra hints beyond 64-layer tech could land next year
https://www.theregister.co.uk/2017/09/27/micron_results/
Massive revenues from DRAM and flash have made Micron CEO Sanjay Mehrotra a happy chief. Third-quarter revenues were good but they have just been eclipsed.
Instead of the forecast midpoint estimate of $5.9bn for Micron’s fourth fiscal 2017 quarter, it made $6.14bn as supply failed to meet demand and prices, and profitability, went up.
A year ago revenues were $3.22bn and a quarter ago they were $5.57bn, meaning increases of 90.7 and 10.2 per cent respectively.
Tomi Engdahl says:
MIPS: Underdog or Dead Horse?
http://www.eetimes.com/author.asp?section_id=36&doc_id=1332351&
MIPS still has a revenue stream. It’s got multi-threading ARM doesn’t have. To think of the semiconductor industry losing the only legitimate alternative CPU IP to ARM would be “a real shame,” some say.
Imagination Technologies’ announcements last week — selling itself to Canyon Bridge while agreeing to sell its MIPS CPU business to Tallwood Venture Capital — have some industry observers scratching their heads.
They asked: “Who wants MIPS now?”
When I asked how MIPS is doing there lately, one of my colleagues at EE Times China in Shenzhen described MIPS cores as “not the mainstream.” She acknowledged that Chinese fabless chip vendors like BLX IC Design Corp. (Loongson), Action and Ingenic are still in MIPSers. But she sees the MIPS ecosystem in China as limited to a small circle of companies.
The proliferation of ARM-based reference designs has made it easy for Chinese design engineers to go with ARM. “There are too many success stories” starring ARM, she added.
MIPS lacks market momentum, to put it mildly.
But MIPS was already suffering from battered “old CPU” syndrome five years ago.
Tomi Engdahl says:
Partnership Puts ReRAM in SSDs
http://www.eetimes.com/document.asp?doc_id=1332348&
TORONTO — Solid state drives (SSDs) are pretty much synonymous with NAND flash, but there have been attempts to use a different persistent memory with varying degrees of success.
Mobiveil Inc. and Crossbar Inc. recently announced they are collaborating to use resistive random access memory (ReRAM) in an SSD. The collaboration will apply Mobiveil’s NVMe SSD IP to Crossbar’s ReRAM IP blocks. The goal is to enable 10 times more IOPs at one-tenth of the latencies of flash NVME SSDs to speed up access to frequently requested information in large data centers, the companies told EE Times in a joint telephone interview.
Mobiveil CEO Ravi Thummarukudy said the company’s NVMe, PCIe and DDR3/4 controllers can easily be adapted to accommodate the Crossbar ReRAM architecture, which is capable of six-million 512B IOPS below 10us latency. He said Mobiveil’s NVM Express Controller architecture is designed to optimize link and throughput utilization, latency, reliability, power consumption and silicon footprint, and can be used along with its PCI Express (PCIe) controller and Crossbar’s ReRAM controller.
Tomi Engdahl says:
What’s The Best Way to Verify Your SSD Controller?
http://www.eetimes.com/author.asp?section_id=36&doc_id=1332335&
To handle the complexity of hardware and software for advanced SoCs, design teams are employing hardware emulation for full chip functional verification of the controller SoC design as well as for the SoC’s firmware.
Tomi Engdahl says:
Power Transistor Market Poised for Growth
http://www.eetimes.com/document.asp?doc_id=1332361&
The power transistor market is poised for steady growth after five years of sluggishness brought about by inventory corrections, economic uncertainty and price erosion, according to market research firm IC Insights.
Power transistor revenue is projected to grow by 6 percent this year to a record $13.6 billion, according to IC Insights’ 2017 0-S-D report. The market grew by 5 percent last year after suffering a 7 percent decline in 2015, according to the firm.
The power transistor market’s projected growth this year is expected to push it past the record of $13.5 billion it set way back in 2011, IC Insights said. The market declined in three of the past five years since, the firm said.
Tomi Engdahl says:
Samsung, Intel Back Process Control Vendor
http://www.eetimes.com/document.asp?doc_id=1332371&
A group of chip companies led by Samsung and Intel have invested $11.2 million in a supplier of semiconductor manufacturing process control systems.
The series C venture round was led by Samsung Venture Investment Corp., the VC arm of South Korea’s Samsung Electronics. Samsung was joined in the funding round by Hitachi High-Tech, sk Hynix and existing investors Intel Capital, Lam Research and MKS Instruments, according to Reno Sub-Systems (Sparks, Nev.).
Reno Sub-Systems was founded in 2014 by a group of semiconductor industry veterans with backgrounds in the manufacturing equipment and process control space. The company offers two principal technologies — flow control for gases used in the chip making and RF power generation and matching for impedance matching of electrical loads used in the process.
Tomi Engdahl says:
Bandying the Benefits of MEMS and MMICs
http://www.mwrf.com/semiconductors/bandying-benefits-mems-and-mmics?NL=MWRF-001&Issue=MWRF-001_20170928_MWRF-001_172&sfvc4enews=42&cl=article_1_b&utm_rid=CPG05000002750211&utm_campaign=13261&utm_medium=email&elq2=8aeb62de527d4782bc147c8d6acab761
High-frequency MEMS and MMICs are key components in helping to miniaturize RF/microwave circuit designs, even though they function in completely different ways.
Miniaturization has allowed a growing number of electronic functions to be packed into pocket-sized designs and, in the case of microelectromechanical-systems (MEMS) devices, even mechanical functions can be included in those designs. MEMS devices are perhaps best known as miniature switches, although they are also gaining popularity when used as frequency sources, such as oscillators. They can be packaged in similarly small enclosures as purely electronic devices, but how do MEMS devices differ from similar-sized electronic circuits, such as monolithic-microwave integrated circuits (MMICs)?
The most essential difference between MEMS and MMICs is that MEMS are designed to function with moving parts, as electromechanical devices, while MMICs are meant to operate fully electronically. Because of the mechanical capabilities, MEMS devices are capable of producing high-frequency resonances (serving as resonators and oscillators), as well as the reverse function of detecting vibration (as in audio microphones).
Tomi Engdahl says:
High Current Power MOSFET with Current Mirror and Temperature Sense Diodes
https://www.eeweb.com/company-blog/ixys/high-current-power-mosfet-with-current-mirror-and-temperature-sense-diodes
This application note presents high current power MOSFET and illustration of voltage drop and drain/source current by Anatoliy Tsyrganovich, Leonid Neyman, and Abdus Sattar, IXYS Corporation. Application schematics are also provided with some recommendation in parameter setup and discussion of its possible operation. Equations related to the applications are also provided with constants and variables definition.
Using current mirror for current sensing in high current MOSFET applications significantly reduces power loss in current sensing circuit and lowers design cost by replacing expensive high power current sensors with inexpensive standard resistors. Two temperature-sensing diodes monolithically integrated in the MOSFET’s die monitor the junction temperature of the MOSFET, rather than that of the package or heat sink temperature. This significantly increases the precision of temperature measurement and reduces the protection gap for operating ambient temperature with minimal risk of damaging the device.
Tomi Engdahl says:
Samsung Details 11LPP Process Technology: 10 nm BEOL Meets 14 nm Elements
by Anton Shilov on September 29, 2017 12:00 PM EST
https://www.anandtech.com/show/11877/samsung-details-11lpp-process-technology-10-nm-beol-meets-14-nm-elements
Samsung has added a new manufacturing technology into its roadmap. The 11LPP fabrication process is designed for mainstream and higher-end smartphone SoCs. The technology will come online next year and will build upon the company’s 14- as well as 10 nm-branded process technologies.
The Samsung 11LPP process is another hybrid process technology designed to speed up migration from one node to another by Samsung Foundry. Notably, the new node is not another 14LPP-based offering featuring 20 nm BEOL (back end of line) interconnects. Instead 11LPP is based on Samsung’s 10 nm BEOL and therefore enables smaller chips than technologies based on Samsung’s 14 nm-branded offerings. Meanwhile, the 11LPP still uses some of the elements featured by Samsung’s 14LPP fabrication process.
Last October Samsung began to produce ICs using its 10LPE (10 nm low-power early) manufacturing tech and these days Samsung is getting ready to start producing semiconductors using its 10LPP (10 nm low power plus) process.
Tomi Engdahl says:
TSMC Aims to Build World’s First 3-nm Fab
http://www.eetimes.com/document.asp?doc_id=1332388&
Taiwan Semiconductor Manufacturing Co. (TSMC) will build the world’s first 3-nm fab in the Tainan Science Park in southern Taiwan, where the company does the bulk of its manufacturing.
The announcement lays to rest speculation that the company might build its next chip facility in the U.S., attracted by incentives offered by the administration of President Donald Trump to bring more manufacturing to America.
About a year ago, TSMC said it planned to build its next fab at the 5-nm to 3-nm technology node as early as 2022. The more recent one-paragraph announcement from TSMC on Sept. 29 didn’t provide a timeframe for the opening of the 3-nm fab.
TSMC previously estimated it would need 50 to 80 hectares (123 to 198 acres) of land for an investment worth about NT$500 billion ($15.7 billion). The company’s earlier 2022 timeframe for the fab takes into account potentially unanticipated delays in construction. Some of TSMC’s recent projects in Taiwan have been set back by as much as a year by public hearings on environmental impact.
Tomi Engdahl says:
Die Handling Critical in Flex Electronics
http://www.eetimes.com/author.asp?section_id=36&doc_id=1332383&
Wearables require flexible hybrid electronics with die thinned to less than 30mum, and handling these ultrathin die is turning out to be a critical part of the manufacturing process.
Ultrathin die (<50 µm) have been in production for years in stacked 3D ICs. Building on this experience, NextFlex is developing new manufacturing processes that integrate ultrathin die onto flexible substrates.
Availability of ultrathin die for development and prototyping is currently a major hurdle to creating flexible hybrid electronics for the wearables market. Working with Disco, a dicing and thinning equipment supplier, NextFlex has produced stress-free ultrathin wafers and die with thicknesses as low as 10 µm. This capability will enable ultrathin die to be made available both to the institute’s member base and to the commercial market.
Once wafers are thinned and the die singulated onto tape, it is necessary to develop a process for removing the die from the tape and placing them on flexible substrates. The Datacon die bonder from assembly equipment supplier Besi helped remove ultrathin die from the tape and enabled a high-accuracy placement onto flexible substrates.
Tomi Engdahl says:
The Week In Review: Manufacturing
https://semiengineering.com/the-week-in-review-manufacturing-174/
For some time, rumors have been running rampant that Samsung would spin off its foundry business into a separate company. That didn’t happen—yet. Recently, though, Samsung’s foundry unit became a division within its semi unit. Now, Samsung plans to form an advisory panel within its chip unit to “enhance its foundry business,” according to a report from BusinessKorea. Last year, TSMC had 50.6% market share, while Samsung had 7.9%, according to the report. Not long ago, Samsung gained steam when it won the Qualcomm foundry business from TSMC. That was for the 10nm node. However, TSMC won part of Qualcomm’s foundry business back from Samsung. That is for 7nm.
The MRAM market continues to heat up. Samsung Electronics has expanded its 28nm FD-SOI process technology by offering derivatives that include RF and embedded MRAM. Separately, Crocus, a developer of magnetic sensor technology and embedded MRAM, has announced volume manufacturing of its technology using TowerJazz’s 130nm CMOS process.