https://www.darrentoback.com/can-risc-v-linux-of-microprocessors-start-an-open-hardware-renaissance
RISC-V is an interesting open hardware CPU. It is the most promising open CPU design, but can it succeed in competitive CPU market?
https://www.darrentoback.com/can-risc-v-linux-of-microprocessors-start-an-open-hardware-renaissance
RISC-V is an interesting open hardware CPU. It is the most promising open CPU design, but can it succeed in competitive CPU market?
716 Comments
Tomi Engdahl says:
Other postings on RISC-V worth to read:
http://www.epanorama.net/newepa/2016/07/16/sifive-introduces-freedom-u500-and-e500-open-source-risc-v-socs/
http://www.epanorama.net/newepa/2016/11/29/hifive1-is-an-open-source-arduino-compatible-risc-v-dev-kit/
Tomi Engdahl says:
Over the past few months, we’ve seen a few new microcontrollers built around the RISC-V core. The first is the HiFive1, a RISC-V on an Arduino-shaped board. The Open-V is another RISC-V based microcontroller, and now it too supports the Arduino IDE. That may not seem like much, but trust me: setting up the HiFive1 toolchain takes at least half an hour.
Source: http://hackaday.com/2017/01/22/hackaday-links-january-22-2017/
Tomi Engdahl says:
risk-vee
An as-small-as-possible RISC-V implementation in Logisim.
https://hackaday.io/project/18859-risk-vee
Tomi Engdahl says:
System Bits: April 18
http://semiengineering.com/system-bits-april-18/
Princeton University researchers have discovered a series of errors in the RISC-V instruction specification that now are leading to changes in the new system, which seeks to facilitate open-source design for computer chips.
In testing a technique they created for analyzing computer memory use, the team found over 100 errors involving incorrect orderings in the storage and retrieval of information from memory in variations of the RISC-V processor architecture. The researchers warned that, if uncorrected, the problems could cause errors in software running on RISC-V chips. According to the researchers, officials at the RISC-V Foundation said the errors would not affect most versions of RISC-V but would have caused problems for higher-performance systems.
“Incorrect memory access orderings can result in software performing calculations using the wrong values. These in turn can lead to hard-to-debug software errors that either cause the software to crash or to be vulnerable to security exploits. With RISC-V processors often envisioned as control processors for real-world physical devices (i.e., internet of things devices) these errors can cause unreliability or security vulnerabilities affecting the overall safety of the systems.”
“RISC-V is in the fortunate position of being able to look back on decades’ worth of industry and academic experience,” he said. “It will be able to learn from all of the insights and mistakes made by previous attempts.”
The RISC-V project essentially offers specifications that guide the hardware and software design of RISC-V processors and software applications.
Martonosi’s team discovered the problems when testing their new system to check memory operations across any computer architecture. The system, called TriCheck, allows designers and others interested in working with a design, to detect memory ordering errors before they become a problem.
Tool checks computer architectures, reveals flaws in emerging design
http://www.princeton.edu/engineering/news/archive/?id=17707
The researchers, testing a technique they created for analyzing computer memory use, found over 100 errors involving incorrect orderings in the storage and retrieval of information from memory in variations of the RISC-V processor architecture. The researchers warned that, if uncorrected, the problems could cause errors in software running on RISC-V chips. Officials at the RISC-V Foundation said the errors would not affect most versions of RISC-V but would have caused problems for higher-performance systems.
Krste Asanović the chair of the RISC-V Foundation, welcomed the researchers’ contributions. He said the RISC-V Foundation has formed a working group, headed by Martonosi’s former graduate student and co-researcher Daniel Lustig, to solve the memory-ordering problems. Asanović, a professor of electrical engineering and computer science at the University of California-Berkeley, said the RISC-V project was looking for input from the design community to “fill the gaps and the holes and getting a spec that everyone can agree on.”
“The goal is to ratify the spec in 2017,” he said. “The memory model is part of that.”
“We call it TriCheck because it is making sure that the memory-ordering guarantees made by these three levels are in alignment,” Martonosi said.
In a paper presented April 10 at the ACM International Conference on Architectural Support for Programming Languages and Operating Systems, the researchers describe the TriCheck system.
Tomi Engdahl says:
RISC-V Cores Get Support, Fees
Silicon IP offered as try-and-buy online
http://www.eetimes.com/document.asp?doc_id=1331690&
Instruction sets may want to be free, but cores–maybe not so much. Startup SiFive announced a new embedded RISC-V core and a relatively simple way to access its processor cores on its Web site, however, they come with one-time licensing costs in the mid-six figures.
SiFive made its existing 32-bit E31 core and a new 64-bit E51 version available for one-time fees of about $300,000 and $600,000, respectively. An open source core called Rocket created by some of SiFive’s founders remains available for free online. It can be used to configure and generate 32- and 64-bit processor cores.
The SiFive news comes just before the sixth workshop of the RISC-V open instruction set group, its first in China.
SiFive will have to compete with a wide range of cores from Cadence, Cortus, Imagination, Synopsys and Andes–which rolls out its first 64-but core next week. The existing players have more mature ecosystems and cores that also sell for less than a million dollars, said Linley Gwennap, principal of the Linley Group (Mountain View, Calif.).
“A year ago there was quite a debate if people would license a core if there was a free version, [but now] we’ve seen significant demand for customers who don’t want an open-source version but one better documented with a company behind it,” said Jack Kang, vice president of product and business development at SiFive.
Tomi Engdahl says:
Agam Shah / PCWorld:
SiFive, creators of open RISC-V architecture, announce $8.5M Series B led by Spark Capital as company unveils two new chip designs
Open-source chip mimics Linux’s path to take on closed x86 and ARM CPUs
The RISC-V chip design can be licensed from SiFive
http://www.pcworld.com/article/3194357/internet-of-things/open-source-chip-mimics-linuxs-path-to-take-on-closed-x86-arm-cpus.html
Tomi Engdahl says:
Andes, First Mainstream CPU IP Provider to Adopt RISC-V, Expands Product Line with New 64bit Processor IP
http://www.digitaljournal.com/pr/3337445
Andes Technology Corporation, the leading Asia-based supplier of high performance, low-power, small embedded CPU cores serving 2-billion SoCs, today announced a new generation of the AndeStar™ architecture. In the process, Andes becomes the first mainstream CPU IP provider to adopt RISC-V, the open RISC Instruction Set Architecture (ISA) developed at the University of California Berkeley. Andes ISA, called AndeStar™ V5, supports 64-bits and the widely known RISC-V ISA as its subset and will bring the open, compact, and modular RISC-V into mainstream SoC applications.
Tomi Engdahl says:
Wednesday 11 00am Keynote Address Impedance Matching Expectations Between RISC V and the Open Hardware
https://www.youtube.com/watch?v=zXwy65d_tu8
Tomi Engdahl says:
Memory Model Verification at the Trisection of Software, Hardware, and ISA (Princeton)
https://semiengineering.com/memory-model-verification-at-the-trisection-of-software-hardware-and-isa-princeton/
Princeton University researchers have discovered a series of errors in the RISC-V instruction specification
Princeton University researchers have discovered a series of errors in the RISC-V instruction specification that now are leading to changes in the new system, which seeks to facilitate open-source design for computer chips. In testing a technique they created for analyzing computer memory use, the team found over 100 errors involving incorrect orderings in the storage and retrieval of information from memory in variations of the RISC-V processor architecture.
TriCheck: Memory Model Verification at the
Trisection of Software, Hardware, and ISA
http://mrmgroup.cs.princeton.edu/papers/ctrippel_ASPLOS17.pdf
Tomi Engdahl says:
VexRiscv: A Modular RISC-V Implementation for FPGA
http://hackaday.com/2017/07/21/vexriscv-a-modular-risc-v-implementation-for-fpga/
Since an FPGA is just a sea of digital logic components on a chip, it isn’t uncommon to build a CPU using at least part of the FPGA’s circuitry. VexRiscv is an implementation of the RISC-V CPU architecture using a language called SpinalHDL.
SpinalHDL is a high-level language conceptually similar to Verilog or VHDL and can compile to Verilog or VHDL, so it should be compatible with most tool chains. VexRiscv shows off well in this project since it is very modular. You can add instructions, an MMU, JTAG debugging, caches and more.
When you build a CPU in FPGA, you generally have to make one of three choices. You can roll your own, which is great fun but requires a lot of work both on the design and the associated tools, for example, a cross-compiler or operating system. You can “borrow” an existing architecture or design which may or may not be legal, depending on what you pick. You can also use a commercial offering. While some of these are free in some circumstances, you’ll pay for anything substantial.
This open implementation offers you an easy way to leverage some great tools. There’s a debugging interface for GDB and a FreeRTOS port. You have a 32-bit part that can achieve 1.16 Dhrystone MIPS/MHz even with all features turned on. This is comparable to commercial 32-bit processors.
A FPGA friendly 32 bit RISC-V CPU implementation
https://github.com/SpinalHDL/VexRiscv
Tomi Engdahl says:
RISC-V and The Birth of the New Computer Architecture Ecosystem
https://www.mentor.com/embedded-software/blog/post/risc-v-and-the-birth-of-the-new-computer-architecture-ecosystem-0e4acb6b-4f9f-4b2e-91a9-884d5e3f4e56?contactid=1&PC=L&c=2017_07_27_esd_newsletter_update_v7_july
It is not often you get to watch the birth of a new computer architecture ecosystem unfold. Announced in 2010, RISC-V has recently seen an increase in momentum as measured in the public development activity of software required to make RISC-V useful. This may seem like an odd way to measure momentum (sorry physicists!), but these are necessary steps for wider adoption of the new open instruction set architecture. As these tools mature they will form the basis for enabling more exotic variants and implementations of the RISC-V architecture. Note that there is already shipping RISC-V hardware in the form of a development kit from SiFive.
Hardware Enablement: Software Makes Hardware Useful
New hardware doesn’t do anything without software. The shortest path to making a new architecture useful is not to write new assemblers, compilers and related software tools but instead extend existing software tools like binutils and gcc so that they support the new architecture. Extending these tools to support a new architecture is called adding a backend port.
To add new hardware support to an existing toolchain or operating system simply pick a recent snapshot of the codebase, make a local development copy, make the required changes, and release a toolchain and OS. If you would like to follow along with the early RISC-V software you can see the work in progress here in the RISC-V git repos.
https://github.com/riscv/
Tomi Engdahl says:
RISC-V Pros And Cons
https://semiengineering.com/risc-v-pros-cons/
Proponents tout freedom for computing architectures, but is the semiconductor ecosystem ready for open-source hardware?
Simpler, faster, lower-power hardware with a free, open, simple instruction set architecture? While it sounds too good to be true, efforts are underway to do just that with RISC-V, the instruction-set architecture (ISA) developed by UC Berkeley engineers and now administered by a foundation.
“The money shouldn’t be going into the processors, necessarily,” said Ted Speers, senior technical director, product architecture and planning for Microsemi‘s SoC business unit, and board member of RISC-V Foundation. “The processor cost should come down, and then you innovate on top of that with accelerators, new architectures, and so forth.”
Technically, the ability to manage complexities has expanded to the point where a 32-bit RISC microprocessor is not considered a complex object anymore, noted Drew Wingard, CTO of Sonics.
“The barrier to entry as a microprocessor instruction set architecture is all about the software and the ecosystem,” he said. “There’s no magic in the underlying technology for microprocessors, in general. RISC-V essentially takes that to the next logical level to say, ‘Let’s try to capture an instruction set architecture together with enough structure and automation that allows us to build families of processors much more easily. And, we’ll choose to distribute it as an open source piece of IP so that the community can add on.’ It has aspects of the open source movement, it has aspects of the configurable processor movement, and it has the opportunity to restructure how we think about the costs of microprocessor IP.”
The business end of this market will likely the same model as Linux, where commercial vendors add in their own IP and support. Commercial suppliers of RISC-V cores include Nvidia, Andes Technology, Cortus, and Codasip.
The main ISAs used today are x86, ARM, ARC, MIPS and PowerPC, along with other ISAs used under the hood in GPUs and DSPs. But RISC-V is starting to make some inroads. Nvidia announced that its SoCs will contain a RISC-V control processor. Andes Technology, a softcore supplier, likewise adopted RISC-V in its 64-bit architecture.
RISC-V from an architecture standpoint, is both simple and elegant
“The key question is software ecosystems,” Mohandass said. “How are they going to develop? It’s the whole chicken-and-egg problem.”
Tomi Engdahl says:
Rambus Adds Security to RISC-V
Block is first in new SiFive IP program
http://www.eetimes.com/document.asp?doc_id=1332175&
Startup SiFive announced a new program providing third-party intellectual property blocks for its RISC-V processors. Its first partnership is for security hardware from Rambus.
Rambus will provide a crypto core optimized to connect to its IoT device management services and run on the SiFive Freedom chips. The Rambus core enables a secure connection, attestation and device monitoring, said Martin Scott, general manager of Rambus’s security group.
The core is the first member of what SiFive calls DesignShare. “SiFive welcomes everybody to join DesignShare — Rambus is the first of many partners we will be announcing soon,” said Jack Kang, vice president of product and business development at the startup.
The program aims to deliver IP “at a low or reduced up front cost,” he said. The blocks will not necessarily be based on open source code.
SiFive officially launched in May its first two cores available on its Web site. Although the RISC-V instruction set is open source, the cores require a one-time licensing fee. SiFive does not charge per-unit royalties.
Tomi Engdahl says:
The open processor got its own ecosystem
RISC-V is an open-source processor based on the popular ARM architecture. Microsemi now says it has set up a Mi-V ecosystem to promote the introduction of an open processor.
RISC-V is a command line for embedded processors managed by the RISC-V Foundation. Its advantages are explicitly based on the open source code, allowing cores to be developed faster than in a closed ecosystem such as ARM.
The Mi-V ecosystem has included, for example, RTOS embedded embedded Micrium and Express Logic, whose Thread OS is one of the most popular embedded device RTOSs.
Microsemi is one of the pioneers of the RISC-V project.
Source: http://etn.fi/index.php?option=com_content&view=article&id=7035&via=n&datum=2017-10-20_15:46:48&mottagare=31202
Tomi Engdahl says:
RISC-V Spins into Drives, AI
Western Digital, Esperanto tip plans for chips
https://www.eetimes.com/document.asp?doc_id=1332658&_mc=RSS_EET_EDT
Storage giant Western Digital announced that it will standardize on RISC-V processors and has invested in Esperanto Technologies, a startup designing high-end SoCs and cores using the open-source instruction set architecture. The two moves suggest that RISC-V has emerged as a viable — but not yet mature — alternative to ARM and the x86.
Long-term, WD expects that it could ship as many as 2 billion RISC-V chips a year inside its hard-disk and solid-state drives. Privately, the company also revealed that it is working on machine-learning accelerators for inference, probably related to its unspecified investment in Esperanto.
For its part, the startup tipped plans for a family of 64-bit RISC-V chips that will include:
An AI “supercomputer-on-a-chip” to be made in TSMC’s 7-nm process.
A 16-core “ET-Maxion” targeting highest single-thread performance
A 4,096-core “ET-Minion” targeting performance-per-watt with a vector floating-point unit in each core.
“Having a major company like WD bet on the architecture is a huge boost for the RISC-V ecosystem, and having a startup try to take it to high-end products is a big deal because to date, RISC-V has been mainly in low-end microcontrollers for the IoT,” said Linley Gwennap, principal of market watcher The Linley Group.
At a RISC-V workshop here, Esperanto will demonstrate RTL, presumably running in an FPGA, handling neural-networking jobs such as image recognition. The company’s general-purpose processors haven’t taped out yet but will target a range of applications.
“Top of our apps list is training and inference; we can do pretty good at graphics for high-end VR/AR … [the architecture] works best for problems with lots of parallelism,” said Ditzel.
Unlike training accelerators from rivals such as Nvidia, Intel, and startup Graphcore, “we’re not at a max reticle die size,” he said of the 7-nm chip.
The startup’s main business will be selling SoCs; however, it also may sell systems using them. In addition, it is open to licensing its cores “to make RISC-V more widespread.”
The relative immaturity of RISC-V and software for it is a chief challenge today.
“The GCC compiler is pretty stable and Linux ports are being upstreamed, but LLVM still has ways to go,” said Ditzel. “By the time we are selling chips, there will be a lot more maturity. There hasn’t been much silicon until recently with the SiFive parts, but once that’s there, the software will come along.”
Tomi Engdahl says:
RISC-V Spins into Drives, AI
Western Digital, Esperanto tip plans for chips
https://www.eetimes.com/document.asp?doc_id=1332658
Long-term, WD expects that it could ship as many as 2 billion RISC-V chips a year inside its hard-disk and solid-state drives. Privately, the company also revealed that it is working on machine-learning accelerators for inference, probably related to its unspecified investment in Esperanto.
For its part, the startup tipped plans for a family of 64-bit RISC-V chips that will include:
An AI “supercomputer-on-a-chip” to be made in TSMC’s 7-nm process.
A 16-core “ET-Maxion” targeting highest single-thread performance
A 4,096-core “ET-Minion” targeting performance-per-watt with a vector floating-point unit in each core.
“Having a major company like WD bet on the architecture is a huge boost for the RISC-V ecosystem,
Tomi Engdahl says:
RISC-V Processor Developer Suite Announced by Imperas
http://www.imperas.com/articles/risc-v-processor-developer-suite-announced-by-imperas
Oxford, United Kingdom, November 29th, 2017 – Imperas Software Ltd., the leader in high-performance software simulation and virtual platforms, today announced the release of its new RISC-V Processor Developer Suite™. The RISC-V Processor Developer Suite contains the models and tools necessary to validate and verify the functionality of a RISC-V processor. It also enables the early estimation of timing performance and power consumption for the processor.
The Imperas RISC-V Processor Developer Suite delivers commercially supported models, the fastest software simulator and a suite of tools:
Infrastructure to easily evaluate RISC-V conformance
Reference models for design verification
Standard software tool chains including compiler, linker, debugger, and Eclipse integration
Fast Processor Models, Instruction Set Simulator (ISS) and extendable virtual platforms
Processor model instruction code coverage and profiling
Timing performance and power estimation tools
Many test suites, with different goals, to measure and maintain processor quality
Tomi Engdahl says:
Western Digital Transitions to RISC-V Open-Source Architecture for Big Data, IoT
https://www.designnews.com/electronics-test/western-digital-transitions-risc-v-open-source-architecture-big-data-iot/96736693957917?ADTRK=UBM&elq_mid=2300&elq_cid=876648
Western Digital believes open-source architecture is the best solution for Big Data and Fast Data and has committed to transition all of its cores to RISC-V.
Tomi Engdahl says:
Ploughing 1 TB of RAM with Twenty x86 Oxen and 10,000 RISC-V Chickens
https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/risc-v-workshop-2
OK, that wins the prize for best title of a presentation in the recent RISC-V workshop, or pretty much any workshop.
Esperanto is a startup that came out of stealth mode during the workshop (it was founded 3 years ago in November 2014). The motivation for Esperanto is that there is no RISC-V alternative to high end ARM processors. Without that, it is hard for many companies to make an architectural switch, and business arrangements seem to become less favorable if a company doesn’t show complete loyalty to the Arm architecture. Dave feels that a high-end core in a leading edge process is the missing piece of the puzzle to be able to make the switch across the entire range.
So that’s what Esperanto is doing.
They are designing a high-performance RISC-V core comparable to the best IP alternatives (I guess that is a veiled way of saying they will have as good as performance as Arm but be a little behind Intel). They are not just doing one core, but two or three. The focus is companies with high teraflop computing needs. The aim is not just parity, but to make RISC-V more compelling than other high-end alternatives, with the best single-thread performance and the best TFLOPS per Watt. The first cores will be in 7nm, straight to the most advanced process available.
Customers he has talked to want to see it in a standard Verilog flow, not a Chisel flow. Dave likes Chisel but it takes total commitment since the Verilog it produces is not human comprehensible, and it is hard to make use of tools that manage Verilog, linters, formal verification, and so on.
This takes a very big physical design effort, but there is a big payoff. Energy efficiency needs careful tradeoff of architecture, circuit design, and physical design.
Dave was careful to point out that he wasn’t making any product introductions…but he pretty much did. They are building actual chips, that they will sell. Of the three chips that he talked about, the first is the ET-Maxion, which is obviously the big one. ET-Maxion will be the highest performance 64-bit RISC-V processor. There will no longer be a hole at the high end.
The second core is the ET-Minion. The goal of the Minion is to do all the floating point work. It will be full 64-bit but with an integrated vector floating point unit as well as specialized instructions for machine learning and tensors, some support for graphics operations
The third core is BOOM
It will be optimized for 7nm CMOS (currently it is an academic project) and made available as a licenseable core. Later he said that BOOM would continue to be free, so I’m not sure precisely what the business model is going to be.
He showed a simulation of an “AI supercomputer on a chip” with 16 Maxions and 4096 Minions, each with their own vector floating point unit. That is a lot of teraflops on a single chip.
BOOM is the Berkeley Out of Order Machine. No prizes for guessing that it is a RISC-V implementation that takes the Berkeley Rocket design and adds out-of-order execution. It consists of 16,000 lines of Chisel. The original BOOM was taped out but he couldn’t show a picture due to academic pre-publication rules. He mostly talked about BOOM v2, the second version, done in TSMC 28nm.
Why even do a second version? The first version was very academic. No commercial memory, no LVT-based standard cells.
In some ways the most impressive aspect of BOOM v2 is the subtitle: “taping out an out-of-order processor with a 2-person team in 4 months.”
The biggest challenge in this sort of agile development is that “I can write bugs faster than I can find them.” This is even more complicated in an out-of-order core since sometimes it is genuinely doing something wrong
Tomi Engdahl says:
UltraSoC released a RISC-V processor trace solution with options ranging from a lightweight package that combines simple run-control with USB as the debug interface to more sophisticated solutions with both run control and trace, and interfacing via either JTAG or UltraSoC’s non-intrusive, bare-metal USB. The trace encoder supports both 32 and 64-bit RISC-V designs.
https://www.ultrasoc.com/ultrasoc-delivers-industrys-first-risc-v-processor-trace-ip/
https://semiengineering.com/the-week-in-review-design-114/
Tomi Engdahl says:
Nvidia, Western Digital at Chips’ Frontier
https://www.barrons.com/articles/nvidia-western-digital-at-chips-frontier-1516640945?utm_content=66404605&utm_medium=social&utm_source=twitter
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Barron’s
TECH TRADER DAILY Nvidia, Western Digital at Chips’ Frontier
ByTiernan Ray Updated Jan. 22, 2018 12:08 p.m. ET
RISC-V’s Rick O’Connor poses questions about why the chip world is the way it is.
RISC-V’s Rick O’Connor poses questions about why the chip world is the way it is.
Gary Mobley, chip analyst with The Benchmark Company, this afternoon held a fascinating conference call concerning one of the most intriguing discussions going on in semiconductors today: RISC-V.
That is the name of a non-profit foundation founded by U.C. Berkeley professor David Patterson and his team to create one single “instruction set architecture” that can be used across all manner of chips, from the humblest embedded part on up to big server computers.
The man running the foundation, Rick O’Connor, a veteran of many chip companies, talked the audience through a series of slides, with some questions by Mobley at the end.
RISC-V has gained traction outside of academia.
Nvidia (NVDA) plans to put use ISA across all the “Falcon” CPUs that it puts in its various GPU chips, and Western Digital (WDC) has said it will use RISC-V across its processors.
As O’Connor describes it, RISC-V is a “dictionary” of all the words and phrases that can be used to make a chip run software. It is meant to replace the jumble of lexicons that run existing chips, such as Intel’s (INTC) “x86” instruction set, and ARM’s instruction set.
Bear in mind, RISC-V is just the dictionary; it’s copyrightable, but not patentable. The actual underlying circuit designs still have to come from a chip vendor, which means there’s plenty of design work for Intel and Nvidia and others to do.
Tomi Engdahl says:
HiFive Unleashed is the world’s first RISC-V-based, Linux-capable dev board.
HiFive Unleashed
https://www.crowdsupply.com/sifive/hifive-unleashed
just over a year ago when we introduced the open source, Arduino-compatible HiFive1 dev board based on our Freedom Everywhere line of 32-bit microcontrollers. Today, we’re proud to be doing the same thing with our Freedom Unleashed 64-bit, Linux-capable system-on-chip (SoC) platform. Meet the HiFive Unleashed, the world’s first RISC-V-based, Linux-capable development board.
Tomi Engdahl says:
Lesson. 0: Understanding the RISC-V Ecosystem & Booting Your First Kernel
https://sywtwaosir.wordpress.com/2018/02/01/lesson-0-understanding-the-risc-v-ecosystem-booting-your-first-kernel/
Today we are going to cover a brief introduction of the RISC-V instruction set architecture, and then dive into the process of booting a functioning Linux kernel upon our machine. By doing this, we will learn about how and why the RISC-V ISA was designed the way that it is, and also how we can get software to properly interface with it.
Tomi Engdahl says:
HiFive Unleashed
The world’s first RISC-V-based Linux development board
https://www.sifive.com/products/hifive-unleashed/
HiFive Unleashed is the ultimate RISC-V developer board. Featuring the world’s first and only Linux-capable, multi-core, RISC-V processor – the Freedom U540 – the HiFive Unleashed ushers in a brand new era for RISC-V.
The revolution has started. We can’t wait to see what the world unleashes.
The First Linux-ready RISC-V Chip
As you expect from SiFive, the Freedom U540 is bleeding-edge RISC-V silicon:
World’s fastest RISC-V Processor
World’s only Linux-capable RISC-V SoC
4+1 Multi-Core Coherent Configuration, up to 1.5 GHz
4x U54 RV64GC Application Cores with Sv39 Virtual Memory Support
1x E51 RV64IMAC Management Core
Coherent 2MB L2 Cache
64-bit DDR4 with ECC
1x Gigabit Ethernet
Built in 28nm
Tomi Engdahl says:
A RISC-V That The Rest Of Us Can Understand
https://hackaday.com/2018/02/09/a-risc-v-that-the-rest-of-us-can-understand/
There is great excitement in the world of microprocessors, surrounding the RISC-V architecture. This is an open source modular instruction set specification that has seen implementations on FPGAs, and is starting to emerge in dedicated silicon.
If you are not yet up to speed on what is probably going to be the most important microprocessor development of a generation, you should watch this video. As [Robert Baruch] sets out to demonstrate, the combination of RISC technology and a modular instruction set means that the simplest processor compliant with the RISC-V specification can be surprisingly accessible. And to demonstrate this he’s building one from LSI and MSI TTL chips, something we’d more usually expect to see in a recreation of a much older architecture.
LMARV-1: A RISC-V processor you can see. Part 1: 32-bit registers.
https://www.youtube.com/watch?v=yLs_NRwu1Y4
Tomi Engdahl says:
Is RISC-V Finally Taking Off?
https://blog.hackster.io/is-risc-v-finally-taking-off-e8849e8e0132
Created by researchers at Berkeley, the RISC-V architecture has been around since 2010, but had remained mostly theoretically until very recently. So the arrival of the first commercially-available open source system-on-chip (SoC) based on the architecture—the 32-bit Freedom Everywhere 310—along with the first Arduino-compatible development board called the HiFive1, from the Bay Area startup SiFive, was seen as a real milestone for the open hardware community.
However just over a year since the first commercial silicon arrived, the new SiFive 64-bit Linux-capable SoC platform—called the HiFive Unleashed—may well turn out to be a lot more important in the long run.
Tomi Engdahl says:
RISC-V Gains Its Footing
https://semiengineering.com/risc-v-gains-its-footing/
But working with this architecture has some not-so-obvious pitfalls, and new tools licensing options may be necessary.
The RISC-V instruction-set architecture, which started as a UC Berkeley project to improve energy efficiency, is gaining steam across the industry.
The RISC-V Foundation’s member roster gives an indication who is behind this effort. Members include Google, Nvidia, Qualcomm, Rambus, Samsung, NXP, Micron, IBM, GlobalFoundries, UltraSoC, Siemens, among many others.
One of the key markets for this technology involves storage controllers with multiple companies, said Krste Asanovic, co-founder and chief architect at SiFive, and chairman of the RISC-V Foundation. He described it as integration with memory, along with a PCIe slave that plugs into the back of a server, to provide very high performance flash storage.
Another active area is vector extensions for AI/machine learning. Asanovic has been leading this effort at the RISC-V Foundation, and SiFive is building cores to support vectors for AI machine learning.
“A lot of companies are interested in this space,”
Asanovic sees AI machine learning as one big injection point for RISC-V, particularly because there’s no incumbent in this space providing soft cores. “The vector extensions that we’re defining are significantly more advanced than the other ISAs. That’s one thing that’s leading people into RISC-V.”
A third area with a lot of activity involves minion, aka management, cores. “These days most SoCs need a 64-bit address space because they have very large DRAM attached memory, and customers are looking for embedded controllers that can do housekeeping chores on large SoCs,”
The openness of the RISC-V specification has prompted the development of a plethora of open-processor designs. These processors fit a wide range of applications, from heavy-duty Linux servers with the Berkeley Out-Of-Order Machine (BOOM) CPU, to tiny embedded microcontrollers with the 32-bit PicoRV32, said Allen Baker, lead software developer for ANSYS‘ Semiconductor Business Unit.
“Several implementations have been successfully taped out and are in active operation,
Implementation uses vary as well, Cadence’s Pursley said. “There are people that just want to use the ISA in one of the many vanilla flavors of it, and you can do that using IP from many sources, including open source. The companies that are pushing things a bit further really like the idea that its extensible and customizable. You can prune instructions out, you can add instructions in.
Asanovic pointed out there isn’t anything specific needed in design tools to implement RISC-V. “One advantage we have is we generate our Verilog from Chisel, so our Verilog is very clean so it’s very easily ingested by the tools.
License to innovate
Rupert Baines, CEO of UltraSoC, said one of the attractions of RISC-V is that companies can optimize core designs for their specific needs. “In effect, everyone who wants one has an architecture license.”
“The attraction with RISC-V is that you can change the instruction set, you can change the implementation, you can go and work with different vendors,” said Neil Hand, director of marketing for the Design Verification Technology Division at Mentor, a Siemens Business. “But when you do any of that, you have to make sure that it’s compliant. You’ve got to make sure the things actually still work, so the vast majority of our focus around RISC-V has been on that verification and validation. “
For a few years now, groups within Mentor and other EDA providers have fostered new or existing relationships with RISC-V vendors and looked at building validation environments together. “That’s really the single biggest challenge when you look at optimizing a RISC-V design for low power, or any design really, even if it’s high performance,” said Hand. “You’ve got to make sure that thing still works, and that’s not easy.”
One obvious question is how a RISC-V design and verification flow may look differently from, say, an Arm-based flow. Here, the biggest challenge is knowing what to check, and understanding how to grade the design, Hand said. “If you think of an Arm design, you take an off-the-shelf Arm design, you can be pretty certain you don’t have to worry about what’s inside the black box. If you take a standard RISC-V IP, if you’re choosing a good IP vendor, you don’t have to know what’s going on inside the black box.
Tomi Engdahl says:
SiFive Joins Microsemi’s New Mi-V Ecosystem to Accelerate Adoption of RISC-V Open Instruction Set Architecture
https://investor.microsemi.com/2017-12-07-SiFive-Joins-Microsemis-New-Mi-V-Ecosystem-to-Accelerate-Adoption-of-RISC-V-Open-Instruction-Set-Architecture
Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced SiFive, the first fabless provider of customized, open-source-enabled semiconductors, has joined Microsemi’s new Mi-V™ RISC-V ecosystem, further building out the growing ecosystem and expanding the number of RISC-V designs users can consider. Microsemi will leverage its strategic relationship with SiFive and other ecosystem participants to increase adoption of RISC-V open instruction set architecture (ISA) central processing units (CPUs) and maximize their leadership positions with this expanding design technology.
As part of their collaboration within the Mi-V ecosystem, SiFive and Microsemi are jointly creating the HiFive Unleashed, a hardware and software development platform based on SiFive’s Freedom Unleashed 500 (Freedom U500) system-on-chip (SoC) featuring the U54-MC RISC-V Core IP (intellectual property) as well as Microsemi’s lowest power, cost-optimized mid-range PolarFire® field programmable gate array (FPGA).
Tomi Engdahl says:
Open standards in processor innovation with RISC-V
https://opensource.com/article/18/3/risc-v-instruction-set-architecture?sc_cid=7016000000127ECAAY
As big data and fast data applications create more extreme workloads, purpose-built architectures must pick up where today’s architectures have reached their limit.
Tomi Engdahl says:
Rambus Taps RISC-V for Root of Trust
NXP cautions against integrating security
https://www.eetimes.com/document.asp?doc_id=1333187
Rambus announced a security block based on the RISC-V core aimed, in part, to plug the Meltdown/Spectre flaws revealed earlier this year. The CryptoManager Root of Trust targets use in a wide spectrum of ASICs, microcontrollers, and SoCs in embedded systems.
Rambus claims that the new block sports several advantages over root-of-trust functions already integrated in most existing embedded processors. It suggested that OEMs should move this fundamental hardware-security function out of mainstream x86 and ARM embedded processors that Spectre/Meltdown showed are vulnerable to side-channel attacks.
However, an NXP security expert said that the root-of-trust function ideally should be implemented in a standalone chip, a practice that high-security systems use. The trend of integrating the function into larger chips helped save costs, but it was a step backward in security, said Sami Nassar, vice president of cybersecurity solutions at NXP Semiconductors.
Tomi Engdahl says:
UltraSoC’s Rupert Baines considers the current state of RISC-V adoption, what it will take for it to become a commercial success and see industry-wide adoption, and one worrying trend.
RISC-V: Are we there yet…?
by Rupert Baines | 17 May 2018
…there’s a chasm, and more work is needed to bridge it
https://www.ultrasoc.com/risc-v-yet/
Why compare RISC-V with a technology like Bluetooth? Well, they are both open standards of course – but also the industry is again trying something new: to turn perceived thinking on its head, to see if a non-proprietary platform can attract the ecosystem, the development, the robust standard, security, and of course, more than anything the support of the industry. That backing includes R&D investment and trials
f done well, like Bluetooth or Linux, an open system can find its way into billions of devices and reshape industries. Virtually all of today’s Internet and the trillions of dollars of value that enables runs on open source LAMP (Linux, Apache, MySQL, Python) platforms.
But success is not guaranteed: like Zig-wanna-bees and WiMAXes – countless technologies end up consigned to the history books of brilliant, but sadly unrealized, ideas. There have been plenty of those in the hardware and processor space: even ones that had an opportunity, like OpenSPARC, died – for reasons that, in hindsight, are as clear as those which helped Bluetooth to triumph.
I don’t think RISC-V has quite crossed the chasm. Taking a step back from this Workshop, I would say there is still a feel of early adopters and evangelists, rather than pragmatists. We are getting there, and it is moving quickly. But the reality is we do need the industry to work harder to make it all happen.
There is another very important and slightly worrying trend I’m seeing: the companies driving this are in the USA and Asia (particularly China)… but sadly Europe is at serious risk of missing out. There are plenty of skills, technology and opportunities here in Europe to help take RISC-V across the chasm, but we’re just not witnessing the same level of engagement and interest in Europe – yet. Indeed, even Israel. I think this might be the first technology I have been involved in where Israeli firms were not on the leading edge. Few were present at the Barcelona Workshop.
The Barcelona RISC-V Workshop itself was impressive: last week saw the largest turnout (320 attendees) for a workshop outside of the Bay Area. Just look at the proceedings. People are travelling from all over the world to get involved with RISC-V and to be part of the community.
But it’s the growing breadth of the attendees and presenters which is more telling: companies from all parts of the industry – chip, design, system, even product level and some very big technology names including Western Digital, Facebook and Google (using RISC-V for its Pixel2 phone).
https://riscv.org/2018/05/risc-v-workshop-in-barcelona-proceedings/
Tomi Engdahl says:
India Startup Preps RISC-V, AI Cores
Berkeley-born ISA expands footprint
https://www.eetimes.com/document.asp?doc_id=1333565
A startup in India announced ambitious plans to design and license RISC-V-based processor cores as well as deep-learning accelerators and SoC design tools. InCore Semiconductors will make its first cores available before the end of the year.
The effort marks a small but significant addition to the RISC-V ecosystem. It shows that the initiative is gaining global interest for its open-source instruction set architecture as an alternative to offerings from Arm and other traditional suppliers.
InCore spun out of the Shakti processor research team at IIT-Madras, leveraging research in machine learning at its Robert Bosch AI Centre. So far, it is funding itself with revenues from providing commercial support for Shakti cores, according to G. S. Madhusudan, chief executive of InCore and a principal scientist at IIT-Madras.
Tomi Engdahl says:
The Rise of the Dark RISC-V?
DarkRISCV, an open source RISC-V core for FPGAs
https://blog.hackster.io/the-rise-of-the-dark-risc-v-ddb49764f392
After nearly a decade of neglect, the last year has seen a big uptick in the adoption of the the RISC-V standard. The arrival of the first commercially-available open source system-on-chip (SoC) based on the architecture — the 32-bit Freedom Everywhere 310 — along with the first Arduino-compatible development board called the HiFive1
Which doesn’t mean that keeping other independent implementations of the standard around isn’t still important, which is where DarkRISCV comes in.
the DarkRISCV stack is an experimental open source implementation of the RISC-V standard targeting the low-cost Xilinx Spartan-6 family of FPGAs. Following a week of debugging, Samsoniuk has released the implementation to GitHub under a BSD license.
https://github.com/darklife/darkriscv
Tomi Engdahl says:
SiFive Announces First Open-Source RISC-V-Based SoC Platform with Nvidia Deep Learning Accelerator Technology
https://www.sifive.com/posts/2018/08/20/sifive-announces-first-open-source-risc-v-based-soc-platform-with-nvidia-deep-learning-accelerator-technology/
Tomi Engdahl says:
Boffins trying to build a open source secure enclave on RISC-V
Open source trusted execution component expected this fall
https://www.theregister.co.uk/2018/08/31/keystone_secure_enclave/
At some point this fall, a team of researchers from MIT’s CSAIL and UC Berkeley’s EECS aim to deliver an initial version of an open source, formally verified, secure hardware enclave based on RISC-V architecture called Keystone.
“From a security community perspective, having trustworthy secure enclaves is really important for building secure systems,” said Dawn Song, a professor of computer science at UC Berkeley and founder and CEO of Oasis Labs, in a phone interview with The Register. “You can say it’s one of the holy grails in computer security.”
Keystone
Open-source Secure Hardware Enclave
https://keystone-enclave.org/
Keystone is an open-source project for building trusted execution environments (TEE) with secure hardware enclaves, based on the RISC-V architecture. Our goal is to build a secure and trustworthy open-source secure hardware enclave, accessible to everyone in industry and academia.
Tomi Engdahl says:
Freedom E310 (FE310 MCU)
https://groupgets.com/campaigns/462-freedom-e310-fe310-mcu
The Freedom E310 (FE310) is the first member of the Freedom Everywhere family of customizable SoCs. Designed for microcontroller, embedded, IoT, and wearable applications, the FE310 features SiFive’s E31 RISC-V Core, a high-performance, 32-bit RV32IMAC core. Running at 320+ MHz, the FE310 is among the fastest microcontrollers in the market.
Tomi Engdahl says:
RISC-V Inches Toward The Center
https://semiengineering.com/risc-v-inches-toward-the-center/
Access to source code makes it attractive for custom applications, but gaps remain in the tool flow and in software.
Tomi Engdahl says:
RISC-V: More Than a Core
https://semiengineering.com/risc-v-more-than-a-core/
Interest in the open-source ISA marks a significant shift among chipmakers, but it will require continued industry support to be successful.
The open-source RISC-V instruction set architecture (ISA) is attracting a lot of attention across the semiconductor industry, but its long-term success will depend on levels of cooperation never seen before in the semiconductor industry. The big question now is how committed the industry is to RISC-V’s success.
Tomi Engdahl says:
https://hackaday.com/2018/10/08/programming-a-risc-v-softcore-with-ada/
Tomi Engdahl says:
Kendryte’s KD233 Is a Dual-Core RISC-V SoC Designed for AI Applications
https://blog.hackster.io/kendrytes-kd233-is-a-dual-core-risc-v-soc-designed-for-ai-applications-2ed75199b4c4
Tomi Engdahl says:
https://venturebeat.com/2018/10/31/sifive-launches-risc-v-processor-cores-for-real-time-applications/
Tomi Engdahl says:
SiFive released a new line of high performance RISC-V cores. The SiFive Core IP 7 Series provides a heterogenous, customizable architecture that allows the different cores in the series to be combined in a single coherent core complex. The E7 Series comprises 32-bit cores with hard real-time capabilities, S7 has a high performance 64-bit architecture for embedded markets, and U7 is a Linux-capable 64-bit applications processor with a configurable memory architecture for domain-specific customization.
Source: https://semiengineering.com/the-week-in-review-design-138/
Tomi Engdahl says:
Two Views of RISC-V in China
https://www.eetimes.com/document.asp?doc_id=1333980
RISC-V Momentum Seen Growing in China
Vendors at a RISC-V event in Silicon Valley report that momentum is growing in China for RISC-V.
Why RISC-V Lags in China
China does appear to have many “buyers” interested in RISC-V cores. But a hunt for developers trying to leverage the RISC-V instruction set in Shanghai comes up short.
Tomi Engdahl says:
Why RISC-V Lags in China
https://www.eetimes.com/author.asp?section_id=36&doc_id=1333976
China does appear to have many “buyers” interested in RISC-V cores. But as I hunt for “developers” trying to leverage the RISC-V instruction set, I’m coming up short in Shanghai.
Asked to name one country where “free,” “open-source” RISC-V should find its natural home, I was pretty sure it ought to be China.
Consider China’s history. Although the government has invested in various CPUs in the past, China never invented a home-grown CPU. Logic dictates, hence, that the Chinese engineering community would jump on RISC-V. Right?
Not so fast. China does appear to have many “buyers” interested in RISC-V cores, as Rick Merritt reported in Silicon Valley. But as I hunt for “developers” trying to leverage the RISC-V instruction set, I’m coming up short in Shanghai.
Tomi Engdahl says:
http://www.etn.fi/index.php/13-news/8785-linux-ja-risc-v-arm-saa-kovan-haastajan
Tomi Engdahl says:
The Linux Foundation and RISC-V Foundation Announce Joint Collaboration to Enable a New Era of Open Architecture
https://www.linuxfoundation.org/the-linux-foundation/2018/11/the-linux-foundation-and-risc-v-foundation-announce-joint-collaboration-to-enable-a-new-era-of-open-architecture/
Tomi Engdahl says:
RISC-V Takes a Leap Forward
Event debuts cores, FPGA, AI chips, interconnect
https://www.eetimes.com/document.asp?doc_id=1334032
RISC-V is open for business, proponents will claim at the first annual summit for the open-source instruction set architecture today. The Silicon Valley event comes at a time when backers say that China is rallying around the architecture with perhaps hundreds of RISC-V SoCs and dozens of cores in the works.
Western Digital will detail a 32-bit embedded core that it will use in a controller for a consumer solid-state drive set to ship in 2020.
The Microsemi division of Microchip will describe a five-core complex that it will embed in its PolarFire FPGAs by early 2020. The chip marks its first step in a plan to standardize on use of RISC-V.
In the hot field of machine learning, startup SiFive will describe two RISC-V chips — an embedded inference device based on Nvidia’s Deep Learning Accelerator and a training chip using newly mined RISC-V vector extensions along with HBM2 memory and 56-Gbit/s SerDes.
Separately, Google, an early member of the RISC-V Foundation, will show its TensorFlow Lite software geared for embedded systems running on the Zephyr operating system on a RISC-V chip.
RISC-V has a negligible slice of the processor IP market that Arm dominates today, with 21.3 billion units shipped in 2017. However, it is gaining steam and is well-suited to embedded, automotive, and IoT apps that are tolerant of its lack of broad support from third-party software
To date, SiFive has delivered as many as 400 RISC-V systems running Linux.
Tomi Engdahl says:
https://semiengineering.com/week-in-review-design-low-power-21/
Western Digital announced big plans for RISC-V with a new open source RISC-V core, an open standard initiative for cache coherent memory over a network, and an open source RISC-V instruction set simulator. The SweRV Core features a 2-way superscalar design with a 32-bit, 9 stage pipeline core. It has clock speeds of up to 1.8Ghz on a 28mm CMOS process technology and will be used in various internal embedded designs. The SweRV ISS offers full test bench support for RISC-V cores and was used to simulate and validate the SweRV Core.
Western Digital Delivers New Innovations to Drive Open Standard Interfaces and RISC-V Processor Development
https://www.westerndigital.com/company/newsroom/press-releases/2018/2018-12-04-western-digital-delivers-new-innovations-to-drive-open-standard-interfaces-and-risc-v-processor-development
Company Announces Plans to Open Source New RISC-V SweRV Core™ to Accelerate Development of Purpose-Built Architectures from Core to Edge
Tomi Engdahl says:
Codasip uncorked the latest version of its tool suite for development and verification of RISC-V processors. The tools allow designers to write a high-level description of a processor in the architecture description language CodAL and then automatically synthesize the design’s RTL, test bench, virtual platform models, and processor SDK.
https://semiengineering.com/week-in-review-design-low-power-21/
https://www.codasip.com/2018/12/06/codasip-releases-studio-8-a-breakthrough-in-risc-v-automation-and-the-bk7-risc-v-processor-core-for-real-time-computing-applications/
Tomi Engdahl says:
Andes Technology uncorked Andes Custom Extension (ACE) for its recently-announced line of RISC-V cores, allowing embedded designers to add customized instructions to Andes V5 CPU cores.
http://www.andestech.com/news-d.php?cls=1&id=646