https://www.darrentoback.com/can-risc-v-linux-of-microprocessors-start-an-open-hardware-renaissance
RISC-V is an interesting open hardware CPU. It is the most promising open CPU design, but can it succeed in competitive CPU market?
https://www.darrentoback.com/can-risc-v-linux-of-microprocessors-start-an-open-hardware-renaissance
RISC-V is an interesting open hardware CPU. It is the most promising open CPU design, but can it succeed in competitive CPU market?
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Tomi Engdahl says:
The Increasingly Ordinary Task Of Verifying RISC-V
Integrating an open-source core into a complex SoC is looking very familiar.
https://semiengineering.com/the-increasingly-ordinary-task-of-verifying-risc-v/
As RISC-V processor development matures and its usage in SoCs and microcontrollers grows, engineering teams are starting to look beyond the challenges of the processor core itself.
So far, the majority of industry verification efforts have focused on ISA compliance to standardize the RISC-V core. Now the focus is shifting to be how to handle verification as the system grows, especially as this task scales up with multiple cores and the addition of off-the-shelf peripherals and custom hardware modules. And as with any processor core, it’s just as complex and time-consuming of a project.
“We can see two verification challenges here,” said Zibi Zalewski, general manager at Aldec’s Hardware Products Division. “First is the complexity of the core itself and how to make sure it is correct and ISA-compliant. Second is how to test the system using the core. In both cases, transaction-level hardware emulation is the perfect choice — particularly if the emulation is based on the Accellera SCE-MI standard, which allows for reusability between different platforms and vendors. Combined with automatic design partitioning and wide debugging capabilities, this makes a complete verification platform.”
Tomi Engdahl says:
The Increasingly Ordinary Task Of Verifying RISC-V
https://semiengineering.com/the-increasingly-ordinary-task-of-verifying-risc-v/
Integrating an open-source core into a complex SoC is looking very familiar.
Tomi Engdahl says:
Improving RISC-V Linux support in Rust
https://www.codethink.co.uk/articles/2020/improving-risc-v-linux-support-in-rust/
Tomi Engdahl says:
https://etn.fi/index.php/about/13-news/9864-kiinnostaako-avoin-risc-v-prosessori
Tomi Engdahl says:
Getting Started with the RISC-V Open Source GNU Toolchain
https://mindchasers.com/dev/rv-getting-started
Tomi Engdahl says:
Hands-On HiFive RISC-V
Technology Editor Bill Wong tries out SiFive’s HiFive1 RISC-V Arduino-compatible board.
https://www.electronicdesign.com/industrial-automation/article/21805570/handson-hifive-riscv
Tomi Engdahl says:
seL4 is verified on RISC-V!
https://microkerneldude.wordpress.com/2020/06/09/sel4-is-verified-on-risc-v/
seL4 (pronounced ess-e-ell-four) is arguably the world’s most secure operating system (OS) kernel.
The OS kernel is the lowest level of software running on a computer system. It is the code that executes in privileged mode (S-mode in RISC-V; M-mode is reserved for microcode/firmware). The kernel is ultimately responsible for the security of a computer system.
seL4 is a microkernel. The idea of a microkernel is to minimise the trusted computing base – the part of the system for which there is no Plan B if it fails. The Linux and Windows kernels consist of tens of millions of lines of code, and contain literally thousands (more likely tens of thousands) of bugs – a huge attack surface. A well-designed microkernel, such as seL4, has about ten thousand lines – inherently more trustworthy.
Tomi Engdahl says:
Open-Source Hardware Momentum Builds
RISC-V drives new attention to this market, but open-source’s cost/benefit equation differs for hardware versus software.
https://semiengineering.com/riding-the-risc-v-wave/
Tomi Engdahl says:
Heading to production later this year, the SAVVY-V cluster board packs in high-speed network connectivity and stacks six high.
FOSOH-V Unveils Cluster-Friendly SAVVY-V PolarFire RISC-V Development Board Design
https://www.hackster.io/news/fosoh-v-unveils-cluster-friendly-savvy-v-polarfire-risc-v-development-board-design-7e98b1dd949d
Heading to production later this year, the SAVVY-V cluster board packs in high-speed network connectivity and stacks six high
Tomi Engdahl says:
Microchip Technology Inc. has launched its PolarFire SoC Icicle, a dev board built around the company’s first Linux-capable RISC-V and FPGA SoC. Now on Crowd Supply!
Microchip Opens Orders for Its Linux-Capable PolarFire SoC Icicle Kit RISC-V FPGA Dev Board at $499
https://www.hackster.io/news/microchip-opens-orders-for-its-linux-capable-polarfire-soc-icicle-kit-risc-v-fpga-dev-board-at-499-4c4b0a052af1?d627f44819e0cdb235a1ba10dc32df2e
Now out of early access status, the PolarFire SoC is available in a dev board dubbed the Icicle — and shipment is scheduled for September.
Microchip has opened orders for its PolarFire SoC Icicle, a development board built around the company’s first Linux-capable RISC-V and field-programmable gate array (FPGA) system-on-chip (SoC).
Microchip launched an early-access program for its PolarFire SoC around seven months ago, promising a system-on-chip targeting FPGA developers and bundling two Linux-capable 64-bit RISC-V core implementations — one RV64IMAC monitor core plus four RV64GC general-purpose cores, both linked together in what the company describes as a “deterministic, coherent CPU cluster.”
“Delivering the industry’s first RISC-V based SoC FPGA along with our Mi-V ecosystem
Now, the company is ready for general availability — and has launched the Icicle Kit on Crowd Supply with shipping beginning in mid-September. Built around the PolarFire SoC, the Icicle includes the 64-bit Linux-capable RISC-V CPU cluster along with FPGA resources including a non-volatile fabric with 254l logic elements, 784-unit math block, and four 12.7Gb/s serialiser/deserialiser (SERDES) ports. There’s 2GB of LPDDR4 on-board, 1Gb of SPI flash storage, and an 8GB eMMC which can be overridden by an SD Card slot.
Tomi Engdahl says:
SparkFun Electronics, Inc.’s walkthrough covers porting FreeRTOS to the low-cost dev boards, bringing RISC-V experimentation to pocket-money pricing.
SparkFun’s Avra Saslow Showcases FreeRTOS on the RISC-V-Powered RED-V Dev Board Family
https://www.hackster.io/news/sparkfun-s-avra-saslow-showcases-freertos-on-the-risc-v-powered-red-v-dev-board-family-f59e2c2fc8ef?c3f99e62ef70deec7d934b2ea347e2c0inging
Video walkthrough covers porting FreeRTOS to the low-cost dev boards, bringing RISC-V experimentation to pocket-money pricing.
SparkFun’s Avra Saslow has published a video showcasing the installation and use of FreeRTOS, the free-software real-time operating system, on the SparkFun RED-V RISC-V development board family.
“The RISC-V ISA completely changes the computing business model,” claims Saslow. “Instead of traditionally having to buy a specific vendor’s ISA (which is locked under licenses, royalties and NDAs), the RISC-V architecture allows users to extend the core to fit their specific needs. No need to wait for a vendor to mitigate security flaws or for you to get support — you can customize, mitigate, and scale the core exactly how you want to.
Affordability, with the Arduino Uno form factor RED-V RedBoard costing just $39.95 and the smaller RED-V Thing Plus a mere $29.95. Both include SiFive’s Freedom E310 RISC-V microcontroller core, one of the first mass-produced RISC-V ICs.
Tomi Engdahl says:
Designed to connect to the Raspberry Pi-compatible GPIO header, Antmicro’s board gives the Microchip Technology Inc. Icicle Kit a video output while leaving the PCIe slot free.
Antmicro’s Open-Hardware HDMI Breakout Gives Microchip’s PolarFire SoC Icicle Kit an HDMI Output
https://www.hackster.io/news/antmicro-s-open-hardware-hdmi-breakout-gives-microchip-s-polarfire-soc-icicle-kit-an-hdmi-output-0ac7e59b90cf
Designed to connect to the Raspberry Pi-compatible GPIO header, the board gives the Icicle a video output while leaving the PCIe slot free.
Microchip’s PolarFire SoC Icicle Kit, a Linux-capable development board that combines processor cores based on the free and open source RISC-V instruction set architecture (ISA) with a highly-capable field-programmable gate array (FPGA), now has an open-hardware option for video output: Antmicro’s HDMI Board.
“Experimentation and architectural research aside, the PFSoC [PolarFire SoC] is just a great FPGA SoC with a powerful CPU and 23-461K LUTs. Video and sound processing, machine learning accelerators, extremely flexible smart interface bridges are the areas where it will really shine, especially with the current advances in the open FPGA IP core ecosystem that we are contributing to,” explains Antmicro. “The Icicle board will be of great use in prototyping products that require custom hardware and IP, which we can then turn into dedicated boards with a custom gateware design and BSP.”
Tomi Engdahl says:
RISC-V processor designed by five Chinese university students successfully fabricated
https://cntechpost.com/2020/07/25/risc-v-processor-designed-by-five-chinese-university-students-successfully-tape-out/
Tomi Engdahl says:
Heading to production later this year, the SAVVY-V cluster board packs in high-speed network connectivity and stacks six high.
FOSOH-V Unveils Cluster-Friendly SAVVY-V PolarFire RISC-V Development Board Design
https://www.hackster.io/news/fosoh-v-unveils-cluster-friendly-savvy-v-polarfire-risc-v-development-board-design-7e98b1dd949d
Heading to production later this year, the SAVVY-V cluster board packs in high-speed network connectivity and stacks six high.
Ali Uzel is preparing to launch a crowdfunding campaign to produce the SAVVY-V, a RISC-V development board designed with Linux support in mind and based around Microchip’s PolarFire SoC and FPGA combination.
Uzel has confirmed the specifications of the cluster-centric development board, pointing out it offers more memory, more storage, and faster interconnections than competition like the PolarBerry and Microchip’s own Icicle Development Kit.
Tomi Engdahl says:
India selects RISC-V for semiconductor self-sufficiency contest: Use these homegrown cores to build kit
https://www.theregister.com/2020/08/19/india_microprocessor_challenge_risc_v/
Startups encouraged to get busy with open-source 32-bit Shakti, 64-bit VEGA
India has announced a national competition to foster the use of the nation’s homegrown RISC-V microprocessor designs in the hope the tech will eventually replace imported parts, and be used to create products in demand around the world.
The contest’s organizers argue India needs its own silicon to power all manner of things, from “public utility services such as surveillance, transportation, and environmental-condition monitoring” to “commodity appliances like smart fans, locks, and washing machines.” India’s government also wants its own chip families for its aerospace, defense, and nuclear sectors, on the grounds it can only be satisfied security-wise if it uses homemade products.
Tomi Engdahl says:
http://www.nextplatform.com/2020/08/21/alibaba-on-the-bleeding-edge-of-risc-v-with-xt910/
Tomi Engdahl says:
With a 400MHz dual-core RISC-V core and a Kendryte deep learning accelerator, this low-cost handheld gadget targets edge AI projects.
Sipeed Maix Amigo Brings Two Cameras, Touchscreen, and More in a $39 RISC-V-Powered Handheld Dev Kit
https://www.hackster.io/news/sipeed-maix-amigo-brings-two-cameras-touchscreen-and-more-in-a-39-risc-v-powered-handheld-dev-kit-ac43db6331aa?6d1e481bdcf159961818823e652a7725
With a 400MHz dual-core RISC-V core and a Kendryte deep learning accelerator, this low-cost handheld gadget targets edge AI projects.
Seeed Studio has opened pre-order for a low-cost, all-in-one edge artificial intelligence (edge AI) and computer vision (CV) development unit, built atop the free and open source RISC-V instruction set architecture: the Sipeed Maix Amigo.
Sipeed has been releasing devices based on RISC-V cores at a rapid pace: Earlier this year the company launched the MaixCube all-in-one MicroPython development board, before that the MAIX Nano M.2-form-factor machine learning accelerator, and earlier still the Longan Nano and the original MAIX family. Its latest launch, though, really piles on the features by adding in not only a display but dual cameras, microphone, speaker, and on-board battery for truly untethered use.
Tomi Engdahl says:
https://semiengineering.com/where-risc-v-is-gaining-traction/
Tomi Engdahl says:
Components For Open-Source Verification
https://semiengineering.com/components-for-open-source-verification/
Building an open-source verification environment is not an easy or cheap task. It remains unclear who is willing to pay for it.
Defining an open-source verification methodology is a lot more difficult than just developing an open-source simulator. This is the reality facing open-source hardware such as RISC-V. Some people may be asking for the corresponding open-source verification, but that is a much tougher problem — and it is not going to be solved in the short term.
Part one examined the reasons why open-source verification may make sense and the large amount of commercial software that is needed to do this today. This article will examine the role that various organization can play in the creation or support of a verification flow and the progress being made towards pieces of that becoming open-source.
It is useful to consider this in the context of RISC-V, because the infrastructure surrounding that is layered. Each layer has a role to play and adds something to the final development of a solution. At the top is RISC-V International, which defines the ISA and the extensions that are considered to be standard. The organization has a specific set of needs for verification. In addition, a number of consortiums, including lowRISC, OpenHW, OpenTitan, and Chips Alliance, are building open-source extensions to RISC-V or implementations of them that satisfy certain sets of requirements.
Tomi Engdahl says:
Raspberry Pi saa avoimen haastajan
https://etn.fi/index.php?option=com_content&view=article&id=11125&via=n&datum=2020-09-08_15:15:21&mottagare=30929
Nyt se on saamassa kilpailijan, joka perustuu avoimeen RISC-V-prosessoriin.
Asialla on avoimen koodin ratkaisuja kehittävä Rios Lab. Ensimmäinen kortti eli PicoRio 1.0 perustuu 64-bittiseen Pygmy-järjestelmäpiiriin, jossa500 megahertsin ydintä tuo suorituskyvyn ja yksi 32-bittinen ydin, joka huolehtii perustehtävistä ja laskee järjestelmän tehonkulutuksen alas.
PicoRio-kortti perustuu lähes kokonaan avoimeen lähdekoodiin. Poikkeuksena ovat muistit, USB 3.0 sekä grafiikkaprosessointi.
https://etn.se/index.php/67151
Tomi Engdahl says:
RISC-V drives new attention to this market, but the cost/benefit equation is different for open-source hardware than software.
(With Nvidia buying ARM, RISC-V might get a big push and investments from parties who preferred the independence of the former ARM Ltd.)
Open-Source Hardware Momentum Builds
https://semiengineering.com/riding-the-risc-v-wave/
RISC-V drives new attention to this market, but the cost/benefit equation is different for open-source hardware than software.
Open-source hardware continues to gain ground, spearheaded by RISC-V — despite the fact that this processor technology is neither free nor simple to use.
Nevertheless, the open-source hardware movement has established a solid foothold after multiple prior forays that yielded only limited success, even for processors. With demand for more customized hardware, and a growing field of startups looking to build accelerators and solutions highly tailored to AI/ML algorithms, interest in open-source hardware has been rising.
Tomi Engdahl says:
SiFive has announced plans to release an off-the-shelf personal computer built around the free and open source RISC-V ISA, powered by its upcoming FU740 64-bit RISC-V application processor.
SiFive Unveils Plans for an Off-the-Shelf Linux-Capable Modern PC Built Around the FU740 RISC-V Chip
https://www.hackster.io/news/sifive-unveils-plans-for-an-off-the-shelf-linux-capable-modern-pc-built-around-the-fu740-risc-v-chip-63d43adf357c
Company hopes that having an off-the-shelf, ready-to-run platform for development will help grow the RISC-V ecosystem.
The idea: A product developers can purchase which allows them to developer RISC-V applications straight out-of-the-box, whether on top of an existing operating system like Linux or working straight at the bare metal. The company is also targeting those porting existing applications from other platforms — a key aspect of growing broader adoption of RISC-V.
Tomi Engdahl says:
https://etn.fi/index.php/13-news/11161-risc-v-kaskyt-paasivat-fpga-alustalle
Tomi Engdahl says:
Two months after launching a pre-order campaign, Microchip Makes’ PolarFire SoC Icicle is now shipping!
Microchip’s RISC-V-Powered PolarFire SoC Icicle Kit Launches as the Industry “Embraces RISC-V”
https://www.hackster.io/news/microchip-s-risc-v-powered-polarfire-soc-icicle-kit-launches-as-the-industry-embraces-risc-v-cf8378f37614
Two months after launching a pre-order campaign, the PolarFire SoC Icicle is shipping — though the FPGA SoC at its heart is still sampling.
Tomi Engdahl says:
SiFive hires Qualcomm exec as CEO for RISC-V alternatives to Nvidia-Arm
https://venturebeat.com/2020/09/17/sifive-hires-qualcomm-exec-as-ceo-for-risc-v-alternatives-to-nvidia-arm/
Tomi Engdahl says:
SiFive To Introduce New RISC-V Processor Architecture and RISC-V PC at Linley Fall Virtual Processor Conference
https://www.businesswire.com/news/home/20200914005108/en/SiFive-To-Introduce-New-RISC-V-Processor-Architecture-and-RISC-V-PC-at-Linley-Fall-Virtual-Processor-Conference
SiFive Founders and Inventors of RISC-V will deep dive new vector-based architecture, and debut new SoC for professional developers of RISC-V applications
Tomi Engdahl says:
“We believe a tie-up between Arm and NVIDIA could create an opening for competitors including SNPS (already #2 in semiconductor design IP mkt), CDNS, and SiFive, as well as CEVA & RMBS, to a lesser extent. Companies like MRVL may be left questioning future investments for Thunder X,” said Gary Mobley, senior analyst at Wells Fargo Securities, in a research note. “If Arm, the leading developer of licensable RISC processor IP, were to be acquired by one of hundreds of Arm’s existing licensees, this may cause some existing Arm licensees to re-evaluate long-term processor roadmaps. In particular, we believe the free and open RISC-V ISA would gain more wide-spread industry support. We could see more software (e.g. OS) support for RISC-V, and we could see hardware developers expand usage of RISC-V above and beyond current use cases (e.g. embedded control functions). Any company like SiFive, which specializes in developing specialized, licensable cores based on the RISC-V ISA, could benefit from a ground-swell of RISC-V industry support.”
https://semiengineering.com/week-in-review-manufacturing-test-114/
Tomi Engdahl says:
The Industry’s First SoC FPGA Development Kit Based on the RISC-V Instruction Set Architecture is Now Available
https://www.microchip.com/en/pressreleasepage/industry-s-first-soc-fpga-development-kit-for-risc-v
Microchip’s PolarFire SoC FPGA Icicle Kit enables the broad RISC-V-based Mi-V
ecosystem for the industry’s lowest-power FPGA
CHANDLER, Ariz., Sept. 16, 2020 — The rising adoption of the free and open RISC-V Instruction Set Architecture (ISA) is driving the need for an affordable, standardized development platform that embeds RISC-V technology and leverages the diverse RISC-V ecosystem. To meet this need, Microchip Technology Inc. (Nasdaq: MCHP) is offering the industry’s first RISC-V-based System-on-Chip (SoC) Field-Programmable Gate Array (FPGA) development kit for PolarFire® SoC FPGA—the industry-leading low-power, low-cost, RISC-V-based SoC FPGA. Microchip’s Icicle Development Kit for PolarFire (SoC) FPGAs brings together numerous Mi-V partners to accelerate customer design deployment and commercial adoption across a variety of industries.
Tomi Engdahl says:
SiFive Unveils Plans for an Off-the-Shelf Linux-Capable Modern PC Built Around the FU740 RISC-V Chip
Company hopes that having an off-the-shelf, ready-to-run platform for development will help grow the RISC-V ecosystem.
https://www.hackster.io/news/sifive-unveils-plans-for-an-off-the-shelf-linux-capable-modern-pc-built-around-the-fu740-risc-v-chip-63d43adf357c
Tomi Engdahl says:
RISC-V: What’s Missing And Who’s Competing
https://semiengineering.com/risc-v-whats-missing-and-whos-competing/
Experts at the Table: The open-source ISA is gaining ground in multiple markets, but the tool suite is incomplete and the business model is uncertain.
Tomi Engdahl says:
Creating Domain-Specific Processors Using Custom RISC-V ISA Instructions
How to improve power and area in RISC-V designs.
https://semiengineering.com/creating-domain-specific-processors-using-custom-risc-v-isa-instructions/
When System-on-Chip (SoC) developers include processors in their designs, they face choices in solving their computational challenges. Complex SoCs will usually have a variety of processor cores responsible for varied functions such as running the main application programs, communications, signal processing, security, and managing storage. Traditionally, such cores have been in distinct categories such as MCUs, DSPs, GPUs and application processors. Additionally, some unique architectures and instruction sets were developed for very specialized applications. However, a downside of unique instruction sets is the lack of a software ecosystem.
Today, the distinctions between classic core categories are blurring. This is because if a core is designed the right way, more than one usage can be covered by that processor. Furthermore, by creating a processor that is tuned to the needs of the SoC, the silicon efficiency in terms of area and power can be improved.
Tomi Engdahl says:
The SHAKTI free and open source silicon project has reached another milestone with the boot-up of the Moushik, an Arduino-compatible SoC.
SHAKTI Announces Third Silicon Success with the Arduino-Compatible Moushik
https://abopen.com/news/shakti-announces-third-silicon-success-with-the-arduino-compatible-moushik/
The SHAKTI free and open source silicon project has reached another milestone with the boot up of the Moushik, an Arduino-compatible system-on-chip (SoC) and the group’s third successful silicon tape-out.
The SHAKTI project first announced its success in booting Linux on a home-grown RISC-V based processor back in 2018, initially on a chip built by US semiconductor giant Intel on a 22nm process, then on a chip built natively in India on a 180nm node at the ISRO Semiconductor Laboratory in Chandigarh.
Now, the SHAKTI team has announced its third physical chip: Moushik. “Moushik is a processor-cum-system on chip that would cater to the rapidly growing Internet of Things IOT devices that are integral part of smart cities of our digital India,” the team explains of the new device. “Three steps are involved in the making of a microprocessor chip: the design, the fabrication, and the post-silicon boot-up – all these steps were done in India.
Tomi Engdahl says:
https://riscv.org/2020/09/picorio-for-risc-v-like-raspberry-pi-for-arm/
Tomi Engdahl says:
Is RISC-V Processor Hardware or Software?
Some professionals still misunderstand if RISC-V refers to processor hardware and software, and whether it’s free or not.
https://www.designnews.com/design-software/risc-v-processor-hardware-or-software
RISC-V technology is used in the development of chip hardware, software, and the creation of intellectual property (IP). Recently, the open standard has gained increased interest with the potential US-based Nvidia acquisition of UK-based Arm processor systems. Arm processors dominate the global embedded and chip IP markets.
Many have noted that the acquisition by Nvidia will spur the growth of RISC-V technology as current Arm customers may now see NVidia as either a direct competitor or at least a quasi-competitor. For example, Chinese companies including Alibaba and Huawei – members of the open-source RISC-V foundation – may be one of the many potential beneficiaries of any retreat from Arm processor technology.
Tomi Engdahl says:
Ensimmäinen suuri asiakas avoimelle RISC-V:lle
https://etn.fi/index.php/13-news/11226-ensimmainen-suuri-asiakas-avoimelle-risc-v-lle
RISC-V on avoin RISC-arkkitehtuuri, joka haluaa haastaa englantilaisen Arm:n miljoonien, jopa miljardien sulautettujen laitteiden prosessorina. Nyt RISC-V ottaa merkittävän askeleen eteenpäin, kun yksi suurista mikro-ohjainvalmistajista kertoo ensi vuonna tuovansa siihen perustuvan tuotteen markkinoille.
Asialla on japanilainen Renesas, joka on kolmanneksi suurin MCU-valmistaja XNP:n ja Microchipin jälkeen. Renesas aikoo käyttää Andes Technologyn 32-bittistä AndesCore-ydintä yhdessä sovelluskohtaisessa ohjainperheessä, jonka näytetoimituksen alkavat ensi vuoden jälkimmäisellä puoliskolla.
- Tämä on merkittävä virstanpylväs Andes Technologylle, mutta myös avoimen lähdekoodin RISC-V-käskykannalle, sanoo Andesin toimitusjohtaja Frankwell Lin
Tomi Engdahl says:
RISC-V: Will There Be Other Open-Source Cores?
Experts at the Table: The current state of open-source tools, and what the RISC-V landscape will look like by 2025.
https://semiengineering.com/risc-v-will-there-be-other-open-source-cores/
SE: Is there room for other open-source ISAs?
De Luna: No, and the momentum is actually toward a single ISA in any given SoC rather than multiple ISAs. On average today there are five ISAs in any given SoC. The industry wants that to be just one because it simplifies the hardware-software interfaces and the business contract between the hardware and software groups. A single ISA would simplify a lot of issues between different teams. Multiple ISAs also would mean multiple IC groups, and right now the RISC-V Foundation is doing a great job in terms of managing and promoting RISC-V. Their objectives are clear.
Prikryl: I do not think there’s any need for another open-source ISA. RISC-V is not the first attempt to have an open ISA, but it is the first that actually has succeeded. One of the reasons is there is a massive community behind it. It is not only about academia or hobbyists. Commercial companies are driving it, as well, and that’s really important. That didn’t happen in the past. So right now, it wouldn’t be wise to introduce more fragmentation. Instead of starting a new ISA we need to think how to further improve the current one, how to add new extensions and so on to make it competitive in all market segments.
Roy Choudhury: Inside of large chip companies there have been different ISAs, but they are quickly moving on to RISC-V. It’s pretty saturated. So if somebody wants to add a new ISA, it’s better if they join RISC-V.
Talukdar: One reason for that is the challenge of interpreting the spec. That’s the design intent, so what’s the final goal? It’s not like in a standard ISA flow, and once these things are well understood everyone can go and develop their own. You need to tell your customer this is proven IP and verification IP, and you need to produce information about benchmarks and show it has been used in this many products.
Tomi Engdahl says:
RISC-V: Standing on the Shoulders of Giants
RISC-V is officially a decade old. Here’s a look at what the organization has accomplished and how it’s moving forward with extensions targeting specific computing environments and the industry abroad.
https://www.electronicdesign.com/technologies/embedded-revolution/article/21143171/riscv-standing-on-the-shoulders-of-giants?utm_source=EG+ED+IoT+for+Engineers&utm_medium=email&utm_campaign=CPS201002056&o_eid=7211D2691390C9R&rdx.ident%5Bpull%5D=omeda%7C7211D2691390C9R&oly_enc_id=7211D2691390C9R
RISC-V recently celebrated its 10-year anniversary. Our community is now in a unique position to take advantage of the history of all that came before us in open-source software and hardware.
RISC-V is a ground-up open source architecture embodying the principles of RISC computers. It’s a flexible platform that’s appropriate for solutions targeting industry needs ranging from the Internet of Things (IoT) to supercomputers and everything in between.
We initially developed a compact instruction set architecture (ISA) with the ability to include common, optional, and custom extensions. Not surprisingly, the bar is much higher now than when the first commercial RISC chips showed up in products in the 1980s. This means that there are more requirements for ISA features as well as the need for a growing ecosystem to produce a deployable product.
Of course, the ISA is only the tip of the iceberg. By itself, it’s not useful, so we have and are continuing to develop a rich software ecosystem, ensuring that tools and features (e.g., simulators, verification tools, operating systems, hypervisors, debuggers, compilers, etc.) are in place. In turn, RISC-V members can benefit from sharing common efforts with the community and accelerate innovation.
Tomi Engdahl says:
Launched with the claim of performing edge AI tasks in one percent of the power envelope required by rivals, Maxim Integrated’s MAX78000 impresses.
Maxim Launches Edge AI MAX78000 SoC with Neural Network Accelerator, RISC-V Coprocessor
https://www.hackster.io/news/maxim-launches-edge-ai-max78000-soc-with-neural-network-accelerator-risc-v-coprocessor-6781b3e72c0d
Launched with the claim of performing edge AI tasks in one percent of the power envelope required by rivals, the MAX78000 impresses.
Maxim Integrated has announced the launch of a new chip for the IoT, the MAX78000, claiming to accelerate edge AI tasks for a hundredth of the power required by rival platforms.
“We’ve cut the power cord for AI at the edge,”
The MAX78000 system-on-chip (SoC) is built around a dual-core Arm Cortex-M4 processor, with floating-point unit, running at up to 100MHz, with 512kB of flash memory and 128kB of static RAM (SRAM) plus a performance-boosting 16kB instruction cache. It also includes a low-power 60MHz coprocessor based on the free and open source RISC-V instruction set architecture – the same approach as taken by rival Espressif for its recently-launched ESP32-S2.
Full details on the part are available on the Maxim website, though pricing is only “on request;” an evaluation kit is also available, priced at $168.
https://www.maximintegrated.com/en/products/microcontrollers/MAX78000.html?utm_source=Maxim&utm_medium=press-rels&utm_content=MAX78000&utm_campaign=FY21_Q2_2020_OCT_MSS-LPMicros_WW_AICampaign_EN&utm_term=WF7093
MAX78000
Ultra-Low-Power Arm Cortex-M4 Processor with FPU-Based Microcontroller with Convolutional Neural Network Accelerator
A New Breed of AI Micro Built to Enable Neural Networks to Execute at Ultra-Low Power
Tomi Engdahl says:
Scalable from four to 64 cores, the RISC-V-based NEOX platform aims to offer 3D and AI acceleration at the edge.
Think Silicon Unveils NEOX, a RISC-V-Based “Micro-GPU” Architecture for Graphics and Deep Learning
https://www.hackster.io/news/think-silicon-unveils-neox-a-risc-v-based-micro-gpu-architecture-for-graphics-and-deep-learning-896da67f5efb
Scalable from four to 64 cores, the RISC-V-based NEOX platform aims to offer 3D and AI acceleration at the edge.
Tomi Engdahl says:
OneSpin is contributing security to German government-funded project to build a secure and scalable ecosystem for a RISC-V-based systems for AI edge systems more straightforward and secure. As a contributing partner in the Scalable Infrastructure for Edge Computing (Scale4Edge) project, OneSpin is contributing verification tools.
OneSpin Contributes Processor Integrity Solution for ZuSE-Scale4Edge Government-Funded Project to Assure Integrity of Edge Computing Processors
https://www.onespin.com/press-events/press-releases/details/onespin-contributes-processor-integrity-solution-for-zuse-scale4edge-government-funded-project-to-assure-integrity-of-edge-computing-processors
Tomi Engdahl says:
Avoin RISC-V-ydin kiihtyi jo 4,25 gigahertsiin
https://etn.fi/index.php/13-news/11317-avoin-risc-v-ydin-kiihtyi-jo-4-25-gigahertsiin
RISC-V on Berkeleyn yliopistossa kehitetty avoin RISC-arkkitehtuuri, jonka suosio on kasvanut tasaisesti usean vuoden ajan. Nyt piilaaksolainen suunnittelutyökaluja ja IP-ytimiä kehittävä Micro Magic uutisoi maailman nopeimmasta RISC-V-ytimestä.
Yhtiön mukaan 64-bittinen ydin yltää 5 gigahertsin kellotaajuuteen. 1,1 voltin käyttöjännitteellä se saa CoreMarks-testissä tuloksen 13 000. 0,8 voltilla ydin yltää 4,25 gigahertsin kellotaajuudella CoreMarks-tulokseen 11 000 ja kuluttaa tehoa vain 200 milliwattia.
RISC-V-toteutukset kehittyvät nyt nopeaa tahtia. Niistä alkaa pian tulla varteenotettava vaihtoehto Arm-ytimille sulautetuissa sovelluksissa.
Tomi Engdahl says:
SiFive Unveils “the World’s Fastest” RISC-V Development Board, and the Heart of Its RISC-V PC
https://www.hackster.io/news/sifive-unveils-the-world-s-fastest-risc-v-development-board-and-the-heart-of-its-risc-v-pc-1ad248f026af
HiFive Unmatched aims for ITX compatibility and high performance with four application processors, one real-time processor, and 8GB of RAM.
RISC-V pioneer SiFive has revealed more details about its upcoming RISC-V personal computer, which will be based around the freshly-unveiled HiFive Unmatched development board powered by its FU740 five-core system-on-chip (SoC) hardware.
SiFive unveiled its plan to offer an affordable personal computer built around a 64-bit implementation of the free and open source RISC-V instruction set architecture (ISA) last month, as a means of encouraging software developers to begin porting their software to the platform. Now, the company has unveiled the board at the heart of the effort: the HiFive Unmatched.
SiFive Unveils Plans for an Off-the-Shelf Linux-Capable Modern PC Built Around the FU740 RISC-V Chip
https://www.hackster.io/news/sifive-unveils-plans-for-an-off-the-shelf-linux-capable-modern-pc-built-around-the-fu740-risc-v-chip-63d43adf357c
Company hopes that having an off-the-shelf, ready-to-run platform for development will help grow the RISC-V ecosystem.
Tomi Engdahl says:
SiFive unveils plan for Linux PCs with RISC-V processors
https://venturebeat.com/2020/10/29/sifive-unveils-plan-for-linux-pcs-based-on-risc-v-processors/
SiFive today announced it is creating a platform for Linux-based personal computers based on RISC-V processors. Assuming customers adopt the processors and use them in PCs, the move might be part of a plan to create Linux-based PCs that use royalty-free processors. This could be seen as a challenge to computers based on designs from Intel, Advanced Micro Devices, Apple, or Arm, but giants of the industry don’t have to cower just yet.
The San Mateo, California-based company unveiled HiFive Unmatched, a development design for a Linux-based PC that uses its RISC-V processors. At the moment, these development PCs are early alternatives, most likely targeted at hobbyists and engineers who may snap them up when they become available in the fourth quarter for $665.
If Little is also looking to challenge Intel and AMD in PCs, he’ll have his work cut out for him. For starters, SiFive is currently focused on Linux-based PCs, not Microsoft Windows PCs. Secondly, SiFive wouldn’t build these processors or computers on its own. Its customers — anyone brave enough to take on the PC giants — would have to do that.
“It would be hard to imagine anybody overtly [taking on Intel and other PC makers],” Linkley Group senior analyst Aakash Jani said in an interview with VentureBeat. “You may see companies in stealth mode try to do this. But the biggest [impediment] is the software ecosystem. It took a long time for anybody to even develop for Arm’s architecture, and now they have an x86 emulator. But the same software support doesn’t exist for the RISC-V platform currently. If anyone were to take on the giants of x86 and Arm, they would have to really go develop the software ecosystem.”
Tomi Engdahl says:
SiFive inches closer to offering a true RISC-V PC: Latest five-core dev board includes PCIe, SSD interfaces
Plus 8GB RAM, USB, gigabit Ethernet, mini-ITX form, etc… and competition from Microchip
https://www.theregister.com/2020/10/29/sifive_riscv_pc/
Tomi Engdahl says:
RISC-V is trying to launch an open-hardware revolution
RISC-V is an open-source processor design built to open up CPU design to all companies
https://www.engadget.com/risc-v-upscaled-120000950.html
Tomi Engdahl says:
https://www.hpcwire.com/2020/10/26/nvidia-arm-deal-a-boon-for-risc-v/
Tomi Engdahl says:
SiFive reminds everyone you don’t always need to offload vector math: Here’s a RISC-V CPU that can process it, too
VIU75 core is 64-bit, runs Linux, supports RV vector extension
https://www.theregister.com/2020/10/21/sifive_vector_cpu_core/
Tomi Engdahl says:
RISC-V boom from edge AI says Facebook’s chief AI scientist
https://www.eenewseurope.com/news/risc-v-boom-edge-ai-says-facebooks-chief-ai-scientist
Tomi Engdahl says:
SiFive Unveils “the World’s Fastest” RISC-V Development Board, and the Heart of Its RISC-V PC
https://www.hackster.io/news/sifive-unveils-the-world-s-fastest-risc-v-development-board-and-the-heart-of-its-risc-v-pc-1ad248f026af
HiFive Unmatched aims for ITX compatibility and high performance with four application processors, one real-time processor, and 8GB of RAM
SiFive has now officially opened orders for the HiFive Unmatched, an ITX format single-board computer powered by the company’s most powerful RISC-V processor yet and targeting developers looking for a personal computer-like platform on which to develop for and port to the free and open source RISC-V architecture.
As promised, the HiFive Unmatched is available on Crowd Supply for $665, which includes the board with Freedom U740 processor, offering four application-class U74 RISC-V cores and a fifth real-time S7 RISC-V core, and 8GB DDR4 memory.
SiFive unveiled its plan to offer an affordable personal computer built around a 64-bit implementation of the free and open source RISC-V instruction set architecture (ISA) last month, as a means of encouraging software developers to begin porting their software to the platform. Now, the company has unveiled the board at the heart of the effort: the HiFive Unmatched.
“The HiFive Unmatched enables developers to create the RISC-V-based software they need for RISC-V platforms,”
The board is built around SiFive’s latest FU740 SoC, which packs four high-performance SiFive U74 application processor cores and an S7 core for real-time processing.
Tomi Engdahl says:
RISC-V based Allwinner chip to debut on $13 Linux hacker board
http://linuxgizmos.com/risc-v-based-allwinner-chip-to-debut-on-13-linux-hacker-board/
Alibaba’s T-head subsidiary amd Allwinner have produced a single-core, RISC-V-based XuanTie C906 processor with MMU that will appear on a sandwich-style, Linux-driven, $12.50 Sipeed SBC due in two months.
In July, 2019, Chinese tech giant Alibaba Group surprised the industry with the most powerful RISC-V architecture SoC design to date: a 16-core, 2.5GHz XuanTie 910 (XT 910). Now Alibaba’s RISC-V-focused T-Head subsidiary is collaborating with Allwinner to introduce a single-core, 1GHz XuanTie C906 (RV64GCV) RISC-V processor designed to run Debian Linux. A Sipeed dev kit will arrive in the coming months for $12.50 that incorporates an Allwinner compute module built around the XuanTie C906.