https://www.darrentoback.com/can-risc-v-linux-of-microprocessors-start-an-open-hardware-renaissance
RISC-V is an interesting open hardware CPU. It is the most promising open CPU design, but can it succeed in competitive CPU market?
https://www.darrentoback.com/can-risc-v-linux-of-microprocessors-start-an-open-hardware-renaissance
RISC-V is an interesting open hardware CPU. It is the most promising open CPU design, but can it succeed in competitive CPU market?
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Tomi Engdahl says:
RISC-V International Offers Academics, Individuals Free Development Boards with Up to 16GB of RAM
Early adopters, developers, and others invited to receive a free RISC-V dev board — and if you’re not a member, that’s free too.
https://www.hackster.io/news/risc-v-international-offers-academics-individuals-free-development-boards-with-up-to-16gb-of-ram-e46c7b15b4ac
Tomi Engdahl says:
Englantilainen Picocom on saanut piille pienten avoimeen O-RAN-arkkitehtuuriin perstuvien 5G-solujen tukiaseman ohjainpiirin. Prosessori perustuu taiwanilaisen Andes Technologyn toimittamaan RISC-V-ytimeen.
https://etn.fi/index.php/13-news/12150-o-ran-ohjainpiiri-avoimella-kaskykannalla
Tomi Engdahl says:
https://www.eetimes.com/allwinner-launches-the-first-risc-v-application-processor/
Tomi Engdahl says:
Huawei’s HiSilicon Develops First RISC-V Design to Overcome Arm Restrictions
https://www.tomshardware.com/news/huaweis-hisilicon-develops-first-risc-v-design-to-overcome-arm-restrictions?utm_medium=social&utm_source=twitter.com&utm_campaign=socialflow
In a bid to overcome US restrictions on its Arm designs, Huawei’s HiSilicon has turned to the open-source RISC-V architecture and has even released its first RISC-V board for Harmony OS developers. Due to being blacklisted by the U.S. government, Huawei and its chip division HiSilicon do not have access to development and production technologies designed in America. The restrictions include many Arm processor architectures, including those used in various microcontrollers that Huawei uses widely.
HiSilicon’s HiSilicon Hi3861 development board is based on the company’s own Hi3861 controller. Huawei’s documentation doesn’t disclose exactly what the chip does, but it describes it as a main controller chip. The Hi3861 chip is accompanied by a serial port controller as well as a USB-C port.
Overall, the HiSilicon Hi3861 development board has rather vast (at least Raspberry Pi-like) capabilities, but not for a world that Huawei’s HiSilicon is used to, at least in terms of public opinion.
The Hi3861 is aimed mostly at the IoT market, whereas HiSilicon’s development efforts were historically aimed at high-margin smartphones, tablets, PCs, and embedded systems. But Huawei needs computing platforms to use for its other devices, so the HiSilicon Hi3861 is just what the doctor ordered at this time.
When it comes to high-volume products made by Huawei, a non-Arm-based chip makes exceptional sense and also gives the company experience working with an open-source architecture. Only time will tell if the company uses its RISC-V experience to develop other, more powerful devices.
Tomi Engdahl says:
Home-brew CPUs made out of basic logic chips are fun to build, but they’re rarely more than toys. Filip Szkandera built a 32-bit CPU that’s RISC-V compliant.
Build a RISC-V CPU From Scratch
https://spectrum.ieee.org/geek-life/hands-on/build-a-riscv-cpu-from-scratch
It’s a certain kind of itch that drives people to voluntarily build their own CPU. We start thinking about the papered-over gap in our understanding, the one that lurks between how logic gates and flip-flops work individually and how machine code controls a fully assembled processor. What exactly happens in the magic zone where hardwired circuits start dancing to software’s ever-changing tune?
It turns out this itch afflicts enough people that there are commercial kits for makers who want to put a CPU together
Could I build my own CPU featuring some of the latest technology? Could I design my own fully compliant 32-bit RISC-V central processing unit?
RISC-V is an open-source architecture that’s about 11 years old, and is now starting to make inroads in a world dominated by the x86 and ARM CPU architectures.
The modular nature of the RISC-V design let me build the Pineapple One as a stack of individually testable 10-by-10-centimeter PCBs with different functions [clockwise, from top left]: VGA driver; RAM; transport layer; shifter; ALU; register file; control unit; program counter; ROM.
Instead, I started out by building my complete design—which I dubbed Pineapple One—in Logisim Evolution, a logic-circuit simulator. After consulting the official RISC-V manual and the first edition of David Patterson and John Hennessy’s book Computer Organization and Design, RISC-V Edition (Elsevier, 2017), and pushing Logisim to its outer limits, I had a working simulation of Pineapple One that met the requirements of a basic RISC-V CPU in six months.
Physically, the Pineapple One is distributed over a vertical stack of eight square printed circuit boards that are about 10 centimeters on a side, plus a card that handles a VGA display interface. It uses over 230 integrated circuits, mostly from the 74HCT series of logic chips. My biggest challenge was implementing a barrel shifter—a circuit that can shift around the bits in a register by a controllable amount.
My friend Jan Vykydal helped me set up a RISC-V-compliant compiler to work properly, so I wrote some system software and demo programs in C. The compiler produces machine code, and I use a Python script that takes the code and flashes it to the CPU’s memory. Even though Pineapple One runs at only 500 kilohertz, that’s still fast enough to play a simple computer game like Snake in real time, and the 512 kilobytes of program memory and 512 kB of RAM are ample.
Tomi Engdahl says:
https://etn.fi/index.php/13-news/12223-avointa-ohjainkoodia-pienempaan-tilaan
https://www.segger.com/products/development-tools/runtime-library/
Tomi Engdahl says:
China’s ISCAS to build 2,000 RISC-V laptops by the end of 2022 as nation seeks to cut reliance on Arm, Intel chips
Software porting efforts aim to make sure Android, Linux, Firefox, and Chrome work well ahead of time
https://www.theregister.com/2021/06/08/iscas_2000_riscv_laptops/?utm_source=dlvr.it&utm_medium=facebook
Tomi Engdahl says:
Intel Licenses SiFive’s Portfolio for Intel Foundry Services on 7nm https://trib.al/9Jq8SO7
https://www.anandtech.com/show/16777/intel-licenses-sifives-portfolio-for-intel-foundry-services-on-7nm?utm_medium=social&utm_source=facebook.com&utm_campaign=socialflow&utm_content=anandtech
Today’s announcement from SiFive comes in two parts; this part is significant as it recognizes that Intel will be enabling SiFive’s IP portfolio on its 7nm manufacturing process for upcoming foundry customers. We are expecting Intel to offer a wide variety of its own IP, such as some of the x86 cores, memory controllers, PCIe controllers, and accelerators, however the depth of its third party IP support has not been fully established at this point. SiFive’s IP is the first (we believe) official confirmation of specific IP that will be supported.
Tomi Engdahl says:
SiFive RISC-V Proven in 5nm Silicon
https://www.sifive.com/blog/sifive-risc-v-proven-in-5nm-silicon
OpenFive Tapes Out SoC for Advanced AI/HPC Solutions on TSMC 5nm Technology
Today, I am pleased to see OpenFive, a SiFive business unit that is the leading provider of customizable, silicon-focused solutions with differentiated IP, is continuing to make progress with AI design solutions with the creation of a reference design chiplet architecture using OpenFive Die-to-Die interface, OpenFive HBM3 IP subsystem, and SiFive 7-Series processor IP, for 2.5D-based SoCs. More details on the full announcement can be found on OpenFive’s announcement here, but today I want to call out the SiFive milestone of our first RISC-V processor core in 5nm.
Tomi Engdahl says:
Bluetrum has announced the launch of a RISC-V development board built around the Arduino Uno form factor, designed for use with the RT-Thread RTOS.
Bluetrum Launches RT-Thread-Based Arduino Uno-Like RISC-V Development Board, the AB32VG1
https://www.hackster.io/news/bluetrum-launches-rt-thread-based-arduino-uno-like-risc-v-development-board-the-ab32vg1-8d532d3612d7
Sub-$13 system comes with RT-Thread Studio IDE support, audio capabilities, and even an infrared receiver.
Tomi Engdahl says:
Will We Soon Be Running Linux On SiFive Cores Made By Intel?
https://hackaday.com/2021/06/25/will-we-soon-be-running-linux-on-sifive-cores-made-by-intel/
There’s an understandably high level of interest in RISC-V processors among our community, but while we’ve devoured the various microcontroller offerings containing the open-source core it’s fair to say we’re still waiting on the promise of more capable hardware for anything like an affordable price. This could however change, as the last week or so has seen a flurry of interest surrounding SiFive, the fabless semiconductor company that has pioneered RISC-V technology. Amid speculation of a $2 billion buyout offer from the chip giant Intel it has been revealed that the company best known for the x86 line of processors has licensed the SiFive portfolio for its 7nm process. This includes their latest and fastest P550 64-bit core, bringing forward the prospect of readily available high-power RISC-V computing. Your GNU/Linux box could soon have a processor implementing an open-source ISA, without compromising too much on speed and, we hope, price.
Tomi Engdahl says:
Canonical Launches Its First Official Ubuntu RISC-V Builds, for SiFive’s Unleashed and Unmatched
Partnership with SiFive aims to make Ubuntu the “reference OS for early adopters” of Linux on desktop-class RISC-V.
https://www.hackster.io/news/canonical-launches-its-first-official-ubuntu-risc-v-builds-for-sifive-s-unleashed-and-unmatched-bafd04270204
Tomi Engdahl says:
“Intel to put SiFive’s latest CPU cores into 7nm dev system to woo customers to RISC-V” reports Chris Williams for The Register
https://hubs.la/H0RpV9f0
#sifive #riscv #performance
Intel to put SiFive’s latest CPU cores into 7nm dev system to woo customers to RISC-V
Horse Creek platform to ‘showcase’ new 64-bit P550 processor engine
https://www.theregister.com/2021/06/22/sifive_performance_p550_intel/?utm_campaign=SiFivePerformance&utm_content=171588393&utm_medium=social&utm_source=facebook&hss_channel=fbp-209592736092144
SiFive says it has designed its most powerful RISC-V CPU core yet, and Intel is going to put it under the noses of customers to gauge their interest.
The 64-bit P550 core will be aimed at application processors in data center infrastructure and networking equipment, and higher-end consumer kit. Intel says it will put one or more of the CPUs into a 7nm chipset code-named Horse Creek to show to developers and manufacturers, the idea being that said customers can see this silicon to evaluate SiFive’s RISC-V designs for future products.
“We are pleased to be a lead development partner with SiFive to showcase to mutual customers the impressive performance of their P550 on our 7nm Horse Creek platform,”
“By combining Intel’s leading-edge interface IP such as DDR and PCIe with SiFive’s highest performance processor, Horse Creek will provide a valuable and expandable development vehicle for cutting-edge RISC-V applications.”
We asked Intel for more info on the chipset, and a spokesperson told us: “Horse Creek is an Intel platform that we’re developing for early software development for RISC-V. We’re not sharing configuration details at this time,” added that it is “internal-only” to Intel.
A SiFive spokesperson, meanwhile, told us: “Intel is using the SiFive Performance P550 as part of their Horse Creek platform alongside their leading-edge interface IP, on the Intel 7nm platform, as part of their support of RISC-V.”
Tomi Engdahl says:
SiFive’s brand-new P550 is one of the world’s fastest RISC-V CPUs
Today’s RISC-V microcontrollers may lead to future RISC-V phones and laptops.
https://arstechnica.com/gadgets/2021/06/sifives-brand-new-p550-is-one-of-the-worlds-fastest-risc-v-cpus/
Tomi Engdahl says:
Mathias Claussen’s Guide Puts Quake on Your RISC-V Microcontroller — on the Game’s 25th Birthday
What brought gaming PCs to their knees back in 1996 can now run on a microcontroller — albeit a surprisingly powerful one.
https://www.hackster.io/news/mathias-claussen-s-guide-puts-quake-on-your-risc-v-microcontroller-on-the-game-s-25th-birthday-56d05bfd0783
Tomi Engdahl says:
Canaan Announces Kendryte K510 Edge AI Chip as a Triple-Core RISC-V Part with 3 TOPS NPU
https://www.hackster.io/news/canaan-announces-kendryte-k510-edge-ai-chip-as-a-triple-core-risc-v-part-with-3-tops-npu-748e95cc7f12
The successor to the K210, the new K510 promises twice the clock speed, three times the NPU performance, and an extra core for DSP work.
Tomi Engdahl says:
NodeMCU Launches Sub-$5 Espressif ESP32-C3 RISC-V Development Boards
NodeMCU first out of the gate with a pair of board designs, now available, built around AI Thinker ESP32-C3 modules.
https://www.hackster.io/news/nodemcu-launches-sub-5-espressif-esp32-c3-risc-v-development-boards-f4db43876850
The first commercial development boards featuring Espressif’s RISC-V-based ESP32-C3, a drop-in replacement for the popular ESP8266, have appeared on the market — costing as little as $4 a piece.
Tomi Engdahl says:
RISC-V based XiangShan processor poses another threat to Intel
https://www.redsharknews.com/intel-vs-everyone-enter-the-xiangshan-risc-v-processor
Intel is facing an onslaught from all angles with the development of fast Arm based chips and new competition from the Chinese developed XiangShan processor.
Later this year, Intel is to release the Alder Lake incarnation of its Core CPU series. Concerns about the general availability of electronics aside, it would be easy to see this as a reaction to things like the Arm DynamIQ, with its combination of high-performance and low-power-consumption cores, and of course Apple’s somewhat similar M1 design. In the meantime, designers in China have announced the XiangShan CPU design based on the RISC-V CPU instruction set architecture, which was itself made open source by UC Berkeley in 2010.
Given all this new work from Arm, Intel and the Institute of Computing Technology in China, it’d be easy for designers of more traditional CPUs to feel a little nervous.
Probably the most obvious attractive thing is that many of these new designs have, or promise, dramatically lower power consumption than Intel or Intel-compatible CPUs of similar performance. The absolute highest performance per CPU socket still comes from Intel
Either way, with Apple, Arm, Intel and now others vying for the top spot, there’s a healthy amount of development going on. CPU performance has, compared to the late 90s, been in something of a rut for the last many years, and if the solution to that malaise comes from a move to an entirely new design, fine.
Tomi Engdahl says:
World’s First Desktop PC RISC-V Board Meets AMD Radeon RX 6700 XT
By Anton Shilov 9 days ago
Gaming on RISC-V?
https://www.tomshardware.com/news/radeon-rx-6700-xt-works-with-risc-v
Tomi Engdahl says:
“In a bid to overcome US restrictions on its Arm designs, Huawei’s HiSilicon has turned to the open-source RISC-V architecture and has even released its first RISC-V board for Harmony OS developers. Due to being blacklisted by the U.S. government, Huawei and its chip division HiSilicon do not have access to development and production technologies designed in America. The restrictions include many Arm processor architectures, including those used in various microcontrollers that Huawei uses widely.
HiSilicon’s HiSilicon Hi3861 development board is based on the company’s own Hi3861 controller. Huawei’s documentation doesn’t disclose exactly what the chip does, but it describes it as a main controller chip. The Hi3861 chip is accompanied by a serial port controller as well as a USB-C port. Among the more important aspects, the Hi3861 seems to have all the logic that enables USB-C functionality (e.g., synchronization and port alignment) and GPIO (general-purpose) pins.
Overall, the HiSilicon Hi3861 development board has rather vast (at least Raspberry Pi-like) capabilities, but not for a world that Huawei’s HiSilicon is used to, at least in terms of public opinion.
The Hi3861 is aimed mostly at the IoT market, whereas HiSilicon’s development efforts were historically aimed at high-margin smartphones, tablets, PCs, and embedded systems. But Huawei needs computing platforms to use for its other devices, so the HiSilicon Hi3861 is just what the doctor ordered at this time.
When it comes to high-volume products made by Huawei, a non-Arm-based chip makes exceptional sense and also gives the company experience working with an open-source architecture. Only time will tell if the company uses its RISC-V experience to develop other, more powerful devices. ”
https://www.tomshardware.com/news/huaweis-hisilicon-develops-first-risc-v-design-to-overcome-arm-restrictions
Tomi Engdahl says:
The BeagleV Starlight Board Is Canceled, But StarFive Partners with Radxa for a Replacement Design
https://www.hackster.io/news/the-beaglev-starlight-board-is-canceled-but-starfive-partners-with-radxa-for-a-replacement-design-454a55982dd0
Initial prototypes not heading to production, with a replacement RISC-V design to be unveiled early next year — after Radxa’s replacement.
Tomi Engdahl says:
https://etn.fi/index.php/13-news/12449-risc-v-piirin-tehonkulutus-putosi-pikowattiluokkaan
Tomi Engdahl says:
https://etn.fi/index.php/13-news/12461-5g-tukiasema-yhdella-piirilla
Piilaaksolainen EdgeQ on esitellyt ensimmäisen tuotteensa, joka lupaa mullistaa mobiiliverkkojen tukiasemien suunnittelun ja toteutuksen. Kyse on RISC-V-pohjaisesta piiristä, joka on täysin ohjelmoitava. Yhtiö itse kutsuu sitä ”5G-tukiasemaksi yhdellä sirulla”.
täysin C- ja C++-kielisesti ohjelmoitava piiri, jossa myös RAN-pino on ohjelmoitava. Joustava arkkitehtuuri ja softaohjelmoitava radio takaavat sen, että asiakas maksaa vain niistä ominaisuuksista, jotka vastaavat heidän todellisia tarpeitaan.
https://edgeq.io/technology/
Tomi Engdahl says:
https://etn.fi/index.php/13-news/12470-supertietokone-yhdella-sirulla#ETNartikel
Miltä kuulostaa tuhat koneoppimismalleja prosessoivaa räätälöityä ydintä yhdellä ja samalla piirillä? Avoimeen RISC-V-arkkitehtuuriin pohjautuen? Esperanto Technologiesin toimitusjohtaja Dave Ditzel esitteli tällaisen piirin Piilaakson Hot Chips -tapahtumassa ja kutsui sitä ”supertietokoneeksi yhdellä sirulla”.
Esperanto on startup-yritys, joka on kehittänyt tekniikkaansa julkisuudelta piilossa pidemmän aikaa. Yhtiön tavoitteena oli kehittää RISC-V-suoritin, joka olisi tehokkain kaupallinen RISC-V-toteutus.
Tomi Engdahl says:
Esperanto Emerges From Stealth With 1,000-Core RISC-V AI Accelerator
https://www.eetimes.com/esperanto-emerges-from-stealth-with-1000-core-risc-v-ai-accelerator/
Tomi Engdahl says:
Imagination Technologies Enters the CPU Space With RISC-V Architecture
https://www.tomshardware.com/news/imagination-technologies-risc-v-cpu
Tomi Engdahl says:
Pilot Shows Off Entire Server Room That Exists In Passenger Aircraft Right Below Our Feet
https://www.cnx-software.com/2021/08/22/ultra-low-power-risc-v-system-on-chip-features-adaptive-body-biasing-technology/
Tomi Engdahl says:
Apple Exploring RISC-V, Hiring RISC-V ‘High Performance’ Programmers
By Anton Shilov 1 day ago
RISC-V gets interest from a major player
https://www.tomshardware.com/news/apple-looking-for-risc-v-programmers
Apple is in the process of switching its PCs to Arm-based SoCs, but the company might not be putting all its eggs into one basket, as it is also exploring the emerging open-source RISC-V architecture. This week the company posted a job alert for RISC-V high-performance programmer(s).
Tomi Engdahl says:
Secure FPGA RISC-V SoC Forgoes Heatsink
Aug. 25, 2021
Microchip’s cool, low-power, mid-range PolarFire FPGA family now includes a RISC-V SoC version.
https://www.electronicdesign.com/technologies/embedded-revolution/article/21172262/electronic-design-secure-fpga-riscv-soc-forgoes-heatsink?utm_source=EG%20ED%20Auto%20Electronics&utm_medium=email&utm_campaign=CPS210909013&o_eid=7211D2691390C9R&rdx.ident%5Bpull%5D=omeda%7C7211D2691390C9R&oly_enc_id=7211D2691390C9R
Tomi Engdahl says:
RISC-V can be implemented in an FPGA; Microchip’s development software supports soft-core RISC-V configurations (Fig. 3). Even the smallest PolarFire SoC can handle a RISC-V core with space left for additional logic.
https://www.electronicdesign.com/technologies/embedded-revolution/article/21172262/electronic-design-secure-fpga-riscv-soc-forgoes-heatsink?utm_source=EG%20ED%20Auto%20Electronics&utm_medium=email&utm_campaign=CPS210909013&o_eid=7211D2691390C9R&rdx.ident%5Bpull%5D=omeda%7C7211D2691390C9R&oly_enc_id=7211D2691390C9R
Tomi Engdahl says:
First RISC-V Computer Chip Lands At the European Processor Initiative
https://m.slashdot.org/story/390587
from the rapid-turnaround dept.
An anonymous reader quotes a report from The Register:
The European Processor Initiative (EPI) has run the successful first test of its RISC-V-based European Processor Accelerator (EPAC), touting it as the initial step towards homegrown supercomputing hardware. EPI, launched back in 2018, aims to increase the independence of Europe’s supercomputing industry from foreign technology companies.
Tomi Engdahl says:
https://www.tomshardware.com/uk/news/russian-risc-v-microcontroller
Tomi Engdahl says:
Nvidia CUDA Software Gets Ported to Open-Source RISC-V GPGPU Project
By Aleksandar Kostovic 18 days ago
A hint at a RISC-V GPU future?
https://www.tomshardware.com/news/risc-v-runs-cuda
Tomi Engdahl says:
https://www.tomshardware.com/news/russian-risc-v-microcontroller
Tomi Engdahl says:
6,000 RISC-V Cores on a Xilinx FPGA Break the CoreScore World Record
By Francisco Pires 4 days ago
The 6,000 SERV cores demonstrate Xilinx’s FPGA flexibility
https://www.tomshardware.com/news/6000-risc-v-cores-on-a-xilinx-fpga-break-the-corescore-world-record
Tomi Engdahl says:
Huawei: RISC-V ei vielä valmis älypuhelimiin
https://etn.fi/index.php/13-news/12639-huawei-risc-v-ei-vielae-valmis-aelypuhelimiin
Tomi Engdahl says:
New CoreScore World Record Crams 6,000 SERV RISC-V Cores Into a Single FPGA
A single high-end Xilinx FPGA has played host to an impressive 6,000 individual SERV cores — a new CoreScore world record.
https://www.hackster.io/news/new-corescore-world-record-crams-6-000-serv-risc-v-cores-into-a-single-fpga-2fc6022247e0
Tomi Engdahl says:
Huawei: RISC-V ei vielä valmis älypuhelimiin
https://etn.fi/index.php/13-news/12639-huawei-risc-v-ei-vielae-valmis-aelypuhelimiin
Jan-Erik Ekberg johtaa Huawein järjestelmäturvallisuuden laboratoriota eli HSSL:ää (Helsinki System Security Lab) Helsingissä. ETN tapasi hänet eilen Helsingissä, jossa puheeksi tuli myös uusi avoin RISC-V-prosessoriarkkitehtuuri. Se ei Ekbergin mukaan ole vielä valmis älypuhelimiin.
- Mikro-ohjaimissa RISC-V:tä nähdään jo. Myös tutkimuspuolella arkkitehtuuria katsotaan erityisesti ohjainpuolelta. Arkkitehtuurina se on vasta tulossa. Nyt on nähty ensimmäiset julkistukset, joissa RISC-V-piiri on lähellä mobiililaitevahvuutta. En näe, että RISC-V voisi ihan vielä kompensoida mobiililaitepuolella Arm:n dominanssia. Ajan myötä siitä saattaa tulla vaihtoehto, Ekberg muotoilee.
Sitä hän ei halua ennustaa, milloin tämä voisi olla ajankohtaista. – Nämä ovat valmistajien bisnesratkaisuja.
Ohjainten lisäksi RISC-V-ytimiä nähdään isojen ASIC-piirien sivuprosessoreina. Ekberg muistuttaa, että arkkitehtuurin käytössä kyse ei ole pelkästään itse ytimen suorituskyvystä. – Coren lisäksi tulevat välimuistit, välimuistien koherenssit ja liukuhihnan optimoinnit, jotka kaikki yhdessä tekevät moniydinprosessorista tehokkaan. RISC-V:n kohdalla koko muu ympäristö on vielä kehityksessä jäljessä esimerkiksi Intelin tai Arm:n prosessoreihin verrattuna.
Tomi Engdahl says:
Intel käyttää RISC-V-softaprosessoria!
https://etn.fi/index.php/13-news/12674-intel-kaeyttaeae-risc-v-softaprosessoria
Intel on esitellyt viidennen sukupolven NiOS-prosessorin, joka on ohjelmallinen FPGA-järjestelmäpiireille integroitava suoritin. Uutta NiOS V -prosessorissa on se, että siinä käytetään avointa RISC-V-käskykantaa. Softaprosessori on joustava tapa toteuttaa dedikoitua logiikkaa ohjelmoitavalla FPGA-piirillä.
NiOS on prosessori, joka on tullut Intelille kuusi vuotta sitten, kun prosessorijätti osti FPGA-valmistaja Alteran. Alteran tuotelinjoilla softaprosessoreita on käytetty pitkään ja sen FPGA-piireillä hyödynnettiin myös kovakoodattuja Arm-ytimiä.
Lisätietoja löytyy täältä. Kyse on softaprosessorista, jonka suorituskyky on 0,46 MIPSiä megahertsiä kohti. Sen suorituskyky on noin puolet Arm M0+-ytimeen verrattuna.
Nios® V/m
Microcontroller
https://www.intel.com/content/www/us/en/products/details/fpga/nios-processor/v.html
Based on RISC-V: RV32IA, designed for performance, with atomic extensions, 5-stage pipeline, and AXI4 interfaces. Read the Nios® V Processor Reference Manual to learn more about features and performance benchmarks.
Tomi Engdahl says:
Proposed RISC-V vector instructions crank up computing power on small devices
When you need to do audio, voice or image processing at the network edge or on a battery budget
https://www.theregister.com/2021/10/08/riscv_vector_instructions/
Tomi Engdahl says:
Avoimen RISC-V-arkkitehtuurin suosion kasvu näkyy nyt laajasti eri rintamilla. Uusin merkki arkkitehtuurin aseman noususta tulee Green Hills Softwarelta, joka tunnetaan RTOS-käyttöjärjestelmästään. INTEGRITY-käyttöjärjestelmä on nyt portattu RISC-V:lle.
Käytännössä tämä tarkoittaa, että laitevalmistajat voivat hyödyntää RISC-V-laitteissaan samaa käyttöjärjestelmää, joka kelpaa ohjaamaan lentokoneiden järjestelmiä. INTEGRITY käytetään ja suojataan miljoonia nykypäivän kriittisiä järjestelmiä, joita löytyy autoista, lentokoneista, junista, suojatuista puhelimista ja lääketieteen laitteista.
https://etn.fi/index.php/13-news/12685-lentokoneista-tuttu-rtos-tukee-nyt-risc-v-arkkitehtuuria
Tomi Engdahl says:
An Introduction to the RISC-V Architecture
June 29, 2021
This webinar introduces the RISC-V Architecture, providing an overview of RISC-V Modes, Instructions and Extensions, Control and Status Registers, and Interrupts.
https://www.electronicdesign.com/technologies/embedded-revolution/video/21168472/riscv-international-an-introduction-to-the-riscv-architecture?utm_source=EG%20ED%20Connected%20Solutions&utm_medium=email&utm_campaign=CPS211004016&o_eid=7211D2691390C9R&rdx.ident%5Bpull%5D=omeda%7C7211D2691390C9R&oly_enc_id=7211D2691390C9R
Part I: An Introduction to the RISC-V Architecture
https://www.youtube.com/watch?v=m8DqCTogb8w
Tomi Engdahl says:
LILYGO’s New TTGO T-32C3 Is a Compact, Sub-$3 Espressif ESP32-C3 RISC-V Microcontroller Module
https://www.hackster.io/news/lilygo-s-new-ttgo-t-32c3-is-a-compact-sub-3-espressif-esp32-c3-risc-v-microcontroller-module-38023ccbfed5
Featuring castellated pin headers for surface-mount or partial breadboard compatibility, this low-cost module is a great entry to RISC-V.
Tomi Engdahl says:
RISC-V In… Typescript?
https://hackaday.com/2021/10/14/risc-v-in-typescript/
We are accustomed to seeing RISC-V implementations in Verilog or VHDL, but [Low Level JavaScript] has one in TypeScript. Before you dismiss it as a mere emulator, know that the project relies on gateware-ts, a conversion between TypeScript and Verilog. From there, you can actually put the CPU on an FPGA. You can see the launch video below and there is one development video as well as, presumably, more to come.
Building The Worlds First CPU in TypeScript? (No Really!)
https://www.youtube.com/watch?v=ER7h4ZTe19A
Tomi Engdahl says:
Edullinen kortti HarmonyOS-kehitykseen
https://etn.fi/index.php/new-products/12716-edullinen-kortti-harmonyos-kehitykseen
Kiinnostaako sovellusten kehittäminen Huawein omalle HarmonyOS-alustalle? Nyt se onnistuu edullisella RISC-V-pohjaisella kehityskortilla. Hintaa on vain 10,99 dollaria eli nykykurssilla alle 10 euroa. Kortti perustuu HiSiliconin 32-bittiseen prosessoriin.
Hi3861-kortin ominaisuudet ovat edullisesta hinnasta huolimatta varsin monipuolisia. Hi3681V100-prosessori operoi 160 megahertsin kellotaajuudella ja sillä on 352 kilotavua SRAM-muistia ja 288 kilotavua ROM-muistia. Sovelluksilla on tilaa 2 megatavun flashilla. Itse prosessori on pakattu 5×5-milliseen QFN-koteloon.
https://www.banggood.com/Hi3861-Development-Board-Support-Hongmeng-HarmonyOS-for-Hongmeng-System-Hi3861V100-Chip-Tool-Accessories-p-1903688.html?cur_warehouse=CN&admitad_uid=264f90cd94ecd9acc34adf541b4bca2a&utm_content=608494&tagtag_uid=264f90cd94ecd9acc34adf541b4bca2a
Tomi Engdahl says:
Running at up to 160MHz and with 802.11b/g/n Wi-Fi and Bluetooth 5.0, M5Stack’s compact module costs just $6 — or less in five-unit packs.
M5Stack Launches RISC-V-Based Stamp-C3 Bluetooth Microcontroller Module
https://www.hackster.io/news/m5stack-launches-risc-v-based-stamp-c3-bluetooth-microcontroller-module-b9385c7d2835
M5Stack has announced the launch of the M5 Stamp-C3, a RISC-V Bluetooth module built around the Espressif ESP32-C3 system-on-chip — and it boasts the option to run as a contained unit, surface-mount module, fly-wire module, or breadboard-friendly dual in-line package.
The compact M5 Stamp-C3, M5Stack explains, offers 802.11b/g/n Wi-Fi, Bluetooth 5.0, and Bluetooth Low Energy (BLE) connectivity alongside a single 32-bit RISC-V processor core running at up to 160MHz. There’s 400kB of static RAM (SRAM) and 4MB of flash, and an on-board 3D antenna — plus a few bonus features, like 13 general-purpose input/output (GPIO) pins, a user-accessible button, a physical reset button, and a user-programmable RGB LED.
M5Stack is also keen to point out the module’s security features, combining RSA-3072-based secure boot and AES-128-XTS-based flash encryption to protect devices built around the part from attack.
Tomi Engdahl says:
Small, nimble and quick, this CPU is called Snitch.
Meet Snitch: the Small and Agile RISC-V Processor Tests suggest it is six times faster than other comparable processors
https://spectrum.ieee.org/snitch-riscv-processor-6x-faster?utm_campaign=RebelMouse&socialux=facebook&share_id=6737011&utm_medium=social&utm_content=IEEE+Spectrum&utm_source=facebook
this efficient computing approach, Snitch—built around the streamlined, RISC-V chip architecture—can perform most basic instructions within a single clock cycle. As well, it was designed to execute longer latency instructions without stalling and waiting for their completion. “This leads to a very compact and high-performance design compared to conventional processors that achieve high performance,”
Tomi Engdahl says:
ETH Zurich Team Unveils RISC-V-Based Snitch Processor, Boasts of Sixfold Performance Gains
Designed with two RISC-V ISA extensions, the Snitch chip is up to 6.45 times faster than comparable processors — and more efficient, too.
https://www.hackster.io/news/eth-zurich-team-unveils-risc-v-based-snitch-processor-boasts-of-sixfold-performance-gains-a7d354622888
Tomi Engdahl says:
SiFive Envisions 128-Core RISC-V SoCs as Gap With x86 and Arm Closes
By Anton Shilov about 20 hours ago
SiFive: RISC-V has no limits.
https://www.tomshardware.com/news/sifive-develops-ultra-high-performance-risc-v-core
SiFive emerged from stealth mode as a developer of small, low-power cores for microcontrollers in 2016. By late 2020, the company had a chip that could run Linux and this week said that it developed a CPU core that is comparable to modern offerings designed by Intel and Arm. The company believes that such high-performance designs could be used for a wide variety of applications, including server-grade system-on-chips with 128-cores.
Tomi Engdahl says:
M5Stamp C3 RISC-V board supports WiFI 4, Bluetooth 5.0 Long Range and 2 Mbps bitrate
https://www.cnx-software.com/2021/10/21/m5stamp-c3-risc-v-board-supports-wifi-4-bluetooth-5-0-long-range-and-2-mbps-bitrate/