Here are some of my collection of newest trends and predictions for year 2018. I have not invented those ideas what will happen next year completely myself. I have gone through many articles that have given predictions for year 2018. Then I have picked and mixed here the best part from those articles (sources listed on the end of posting) with some of my own additions to make this posting.This article contains very many quotations from those source articles (hopefully all acknowledged with link to source).
The general trend in electronics industry is that the industry growth have been driven by mobile industry. Silicon content in smartphones and other mobile devices is increasing as vendors add greater functionality. Layering on top of that are several emerging trends such as IoT, big data, AI and smart vehicles that are creating demand for greater computing power and expanding storage capacity.
Manufacturing trends
According to Foundry Challenges in 2018 article the silicon foundry business is expected to see steady growth in 2018. The growth in semiconductor manufacturing will remain steady, but there will be challenges in the manufacturing capacity and expenses to move to the next nodes. For most applications, unless you must have highest levels of performance, there may not be as compelling a business case to focus on the bleeding-edge nodes. Over the last two years, the IC industry has experienced an acute shortage of 200mm fab capacity (legacy MCU, power, sensors, 6-micron to 65nm). In 2018, 200mm capacity will remain tight. An explosion in 200mm demand has set off a frenzied search for used semiconductor manufacturing equipment that can be used at older process nodes. The problem is there is not enough used equipment available. The profit margins in manufacturing are so thin in markets served by those fabs that it’s hard to justify paying current rising equipment prices, and newcomers may have a tough time making inroads. Foundries with fully depreciated 200mm equipment and capacity already are seeing increased revenues in their 200mm business.The specialty foundry business is undergoing a renaissance, thanks to the emergence of 5G and automotive.
300mm is expected to follow a similar path for lack of capacity because 300mm fabs already produce leading-edge chips and more mainstream 300mm demand is driven by MCUs, wireless communications and storage applications. Early predictions are for solid growth in 2018, fueled by demand for memory and logic at advanced 10/7nm.
In 2017, marking the first time that the semiconductor equipment market has exceeded the previous market high of US$47.7 billion set in 2000. Fab tool vendors found themselves in the midst of an unexpected boom cycle in 2017, thanks to enormous demand for equipment in 3D NAND and, to a lesser degree, DRAM. In 2018, equipment demand looks robust, although the industry will be hard-pressed to surpass the record growth figures in 2017. In 2018, 7.5 percent growth is expected to result in sales of US$60.1 billion for the global semiconductor equipment market – another record-breaking year. Demand looks solid across the three main growth drivers for fab tool vendors—DRAM, NAND and foundry/logic.
Rising demand for chips is hitting the IC packaging supply chain, causing shortages of select manufacturing capacity, various package types, leadframes and even some equipment. Spot shortages for some IC packages began showing up in 2017, but the problem has been growing and spreading since then, so packaging customers may encounter select shortages well into 2018. Apple Watch 3 shipment growth to benefit Taiwan IC packagers in 2018.
Market for advanced packaging begins to diverge based on performance and price. Advanced Packaging is now viewed as the best way to handle large amounts of data at blazing speeds.
Moore’s law
Many recent publications say Moore’s Law is dead. Though Moore’s Law is dead may be experiencing some health challenges, it’s not time to start digging the grave for the semiconductor and electronics market yet.
Even smaller nodes are still being taken to use in high end chips. The node names are confusing. Intel’s 10nm technology is roughly equivalent to the foundry 7nm node.In 2018, Intel is expected to finally ramp up 10nm finally in the first half of 2018. In addition, GlobalFoundries, Samsung and TSMC will begin to ship their respective 7nm finFET processes. On the leading edge, GlobalFoundries, Intel, Samsung and TSMC start migrating from the 16nm/14nm to the 10nm/7nm logic nodes. It is expected that some chip-makers face some challenges on the road. Time will tell if GlobalFoundries, Samsung and TSMC will struggle at 7nm. Early predictions are for solid growth in 2018, fueled by demand for memory and logic at advanced 10/7nm. 7nm is projected to generate sales from $2.5 billion to $3.0 billion in 2018. Over time 10nm/7nm is expected to be a big and long-running node. Suppliers of FPGAs and processors are expected to jump on 10nm/7nm.
South Korea’s Samsung Electronics said it has commenced production of the second generation of its 10nm-class 8-Gb DDR4 DRAM. Devices labeled 10nm-class have feature sizes as small as 10 to 19 nanometers. With the continued need for shrinking pattern dimensions, semiconductor manufacturers continue to implement more complex patterning techniques, such as advanced multi-patterning, for the 10nm design node and beyond. They also are investing significant development effort in readying EUV lithography for production at the 7/5nm design nodes. Samsung is planning to begin transitioning to EUV for logic chips next year at the 7nm node, although it is unclear when the technology will be put into production for DRAM.
There will be talk on even smaller nodes. FinFETs will get extended to at least to 5nm, and possibly 3nm in next 5 years. The path to 5nm loks pretty clear. FinFETs will get extended at least to 5nm. It’s possible they will get extended to 3nm. EUV will be used at new nodes, followed by High NA Lithography. New smaller nodes challenges the chip design as abstractions become more difficult at 7nm and beyond. Models are becoming more difficult to develop, integrate and utilize effectively at 10/7nm and beyond as design complexity, process variation and physical effects add to the number of variables that need to be taken into account. Materials and basic structures may diverge by supplier, at 7 nm and beyond. Engineering and scientific teams at 3nm and beyond will require completely different mixes of skills than today.
Silicon is still going strong, but the hard fact is that CMOS has been running out of steam for several nodes, and that becomes more obvious at each new node. To extend into new markets and new process nodes Chipmakers Look To New Materials. There are a number of compounds in use already (generally are being confined to specific niche applications), such as gallium arsenide, gallium nitride, and silicon carbide. Silicon will be supplemented by 2D materials to extend Moore’s Law. Transition metal dichalcogenides (TMDCs), a class of 2D materials derived from basic elements—principally tellurium, selenium, sulfur, and oxygen—are being widely explored by researchers. TMDCs are functioning as semiconductors in conjunction with graphene. Graphene, the wonder material rediscovered in 2004, and a host of other two-dimensional materials are gaining ground in manufacturing semiconductors as silicon’s usefulness begins to fade. Wide-bandgap semiconductor materials like gallium nitride (GaN) and silicon carbide (SiC) are anticipated to be used in many more applications in 2018. Future progress increasingly will require a mix of different materials and disciplines, but silicon will remain a key component.
Interconnect Materials need to to be improved. For decades, aluminum interconnects were the industry standard. In the late 1990s, chipmakers switched to copper. Over the years, transistors have decreased dramatically in size, so interconnects also have had to scale in size leading to roadblock known as the RC challenge. Industry is investing significant effort in developing new approaches to extend copper use and finding new metals. There’s also some investigation into improvements on the dielectric side. The era of all-silicon substrates and copper wires may be coming to an end.
Application markets
Wearables are a question mark. Demand for wearables slowed down in 2017 so much that smart speakers likely outsold wearable devices in 2017 holiday season. eMarketer is estimating that usage of wearable will grow just 11.9 percent in 2018, rising from 44.7 million adult wearable users in 2017 to 50.1 million in 2018. On the other hand market research firm IDC estimates that the shipments of wearable electronics devices are projected to more than double over the next five years as watches displace fitness trackers as the biggest sellers. IDC forecasts that wearables shipments will increase at a compound annual growth rate of 18.4 percent between 2017 and 2021, rising from 113.2 million this year to 222.3 million in 2021. At the same time fitness trackers are expected to become commodity product. Tomorrow’s wearables will become more fully featured and multi-functional.
The automotive market for semiconductors is shifting into high gear in 2018. Right now the average car has about $350 worth of semiconductor content, but that is projected to grow another 50% by 2023 as the overall automotive market for semiconductors grows from $35 billion to $54 billion. The explosion of drive-by-wire technology, combined with government mandates toward fully electric powertrains, has changed this paradigm—and it impacts more than just the automotive industry. Consider implications beyond the increasingly complex vehicle itself, including new demands on supporting infrastructure. The average car today contains up to 100 million lines of code. Self-driving car will have considerably more code in it. Software controls everything from safety critical systems like brakes and power steering, to basic vehicle controls like doors and windows. Meeting ISO 26262 Software Standards is needed but it will not make the code bug free. It’s quickly becoming common practice for embedded system developers to isolate both safety and security features on the same SoC. The shift to autonomous vehicles marks a major shift in the supply chain—and a major opportunity.
Many applications have need for a long service life — for example those deployed within industrial, scientific and military industries. In these applications, the service life may exceed that of component availability. Replacing an advanced, obsolete components in a design can be very costly, potentially requiring an entire redesign of the electronic hardware and software. The use of programmable devices helps designers not only to address component obsolescence, but also to reduce the cost and complexity of the solution. Programmable logic devices are provided in a range of devices of different types, capabilities and sizes, from FPGAs to System on Chips (SoC) and Complex Programmable Logic Devices (CPLD). The obsolete function can be emulated within the device, whether it is a logic function implemented in programmable logic in a CPLD, FPGA or SoC, or a processor system implemented in an FPGA or SoC.
Become familiar with USB type C connector. USB type C connector is becoming quickly more commonplace than any other earlier interface. In the end of 2016 there were 300 million devices using a USBC connection – a big part was smartphones, but the interface was also widespread on laptops. With growth, the USBC becomes soon the most common PC and peripheral interface. Thunderbolt™ 3 on USBC connector promises to fulfill the promise of USB-C for single-cable docking and so much more.
Power electronics
The power electronics market continues to grow and gain more presence across a variety of markets. 2017 was a good year for electric vehicles and the future of this market looks very promising. In 2017, we saw also how wireless charging technology has been adopted by many consumer electronic devices- including Apple smart phones. Today’s power supplies do more than deliver clean and stable dc power on daily basis—they provide advanced capabilities that can save you time and money.
Wide-bandgap semiconductor materials like gallium nitride (GaN) and silicon carbide (SiC) are anticipated to be used in many more applications in 2018. At the moment, the number of applications for those materials is steadily increasing in the automotive and military industry. Expect to see more adoption of SiC and GaN materials in automotive market.
According to Battery Market Goes Bigger and Better in 2018 article advances in battery technologies hold the keys to continuing progress in portable electronics, robotics, military, and telecommunication applications, as well as distributed power grids. It is difficult to see lithium-ion based batteries being replaced anytime soon, so the advances in battery technology are primarily through the application of lithium-ion battery chemistries. New battery protection for portable electronics cuts manufacturing steps and costs for Lithium-ion.
Transparency Market Research analysts predict that the global lithium-ion battery market is poised to rise from $29.67 billion in 2015 to $77.42 billion in 2024 with a compound annual growth rate of 11.6 %. That growth has already spread from the now ubiquitous consumer electronics segment to automotive, grid energy, and industrial applications. Dramatic increase is expected for battery power for the transportation, consumer electronic, and stationary segments. According to Bloomberg New Energy Finance (BNEF), the global energy-storage market will double six times between 2016 and 2030, rising to a total of 125 G/305 gigawatt-hours. In 2018, energy-storage systems will continue proliferating to provide backup power to the electric grid.
Memory
Memory business boomed in 2017 for both NAND and DRAM. The drivers for DRAM are smartphones and servers. Solid-state drives (SSDs) and smartphones are fueling the demand for NAND. Both the DRAM and NAND content in smartphones continues to grow, so memory business will do well in 2018.Fab tool vendors found themselves in the midst of an unexpected boom cycle in 2017, thanks to enormous demand for equipment in 3D NAND and, to a lesser degree, DRAM. In 2018, equipment demand looks robust, although the industry will be hard-pressed to surpass the record growth figures in 2017.
NAND Market Expected to Cool in Q1 from the crazy year 2017, but it is still growing well because there is increasing demand. The average NAND content in smartphones has been growing by roughly 50% recently, going from approximately 24 gigabytes in 2016 to approximately 38 gigabytes today.3D NAND will do the heavy memory lifting that smartphone users demand. Contract prices for NAND flash memory chips are expected to decline in during the first quarter of 2018 as a traditional lull in demand following the year-end quarter.
Lots of 3D NAND will go to solid state drives in 2018. IDC forecasts strong growth for the solid-state drive (SSD) industry as it transitions to 3D NAND. SSD industry revenue is expected to reach $33.6 billion in 2021, growing at a CAGR of 14.8%. Sizes of memory chips increase as number of layer in 3D NAND are added. We’ve already scaled up to 48 layers. Does this just keep scaling up, or are there physical limits here? Maybe we could see a path to 256 layers in few years.
Memory — particular DRAM — was largely considered a commodity business. Though that it’s really not true in 2017. DRAM memory marked had boomed in 2017 at the highest rate of expansion in 23 years, according to IC Insights. Skyrocketing prices drove the DRAM market to generate a record $72 billion in revenue, and it drove total revenue for the IC market up 22%. Though the outlook for the immediate future appears strong, a downturn in DRAM more than likely looms in the not-too-distant future. It will be seen when there are new players on the market. It is a largely unchallenged assertion that Chinese firms will in the not so distant future become a force in semiconductor memory market. Chinese government is committed to pumping more than $160 billion into the industry over a decade, with much of that ticketed for memory startups.
There is search for faster memory because modern computers, especially data-center servers that skew heavily toward in-memory databases, data-intensive analytics, and increasingly toward machine-learning and deep-neural-network training functions, depend on large amounts of high-speed, high capacity memory to keep the wheels turning. The memory speed has not increased as fast as the capacity. The access bandwidth of DRAM-based computer memory has improved by a factor of 20x over the past two decades. Capacity increased 128x during the same period. For year 2018 DRAM remains a near-universal choice when performance is the priority. There has been some attempts to very fast memory interfaces. Intel the company has introduced the market’s first FPGA chip with integrated high-speed EMBED (Embedded Multi-Die Interconnect Bridge): The Stratix 10 MX interfaces to HMB2 memory (High Memory Bandwidth) that offers about 10 times faster speed than standard DDR-type DIMM.
There is search going on for a viable replacement for DRAM. Whether it’s STT-RAM or phase-change memory or resistive RAM, none of them can match the speed or endurance of DRAM. Necessity is the mother of invention, and we see at least two more generations after 1x. XPoint is also coming up as another viable memory solution that could be inserted into the current memory architecture. It will be interesting to see how that plays out versus DRAM.
5G and IoT
5G something in it for everyone. 5G is big. 5G New Radio (NR) wireless technology will ultimately impact everyone in the electronics and telecommunications industries. Most estimates say 2020 is when we will ultimately see some real 5G deployments on a scale. In the meantime, companies are firming up their plans for whatever 5G products and services they will offer. Though test and measurement solutions will be key in the commercialization cycle. 5G is set to disrupt test processes. If 5G takes off, the technology will propel the development of new chips in both the infrastructure and the handset. Data centers require specialty semiconductors from power management to high-speed optical fiber front-ends. 5G systems will drive more complexity in RF front-ends .5G will offer increased capacity and decreased latency for some critical applications such as vehicle-to-vehicle (V2V) or vehicle-to-infrastructure (V2I) communications for advanced driver assistance systems (ADAS) and self-driving vehicles. The big question is whether 5G will disrupt the landscape or fall short of its promises.
Electronics manufacturers expect a lot from Internet of Thing. The evolution of intelligent electronic sensors is creating a revolution for IoT and Industrial IoT as companies bring new sensor-based, intelligent systems to market. The business promise is that the proliferation of smart and connected “things” in the Industrial Internet of Things (IIoT) provides tremendous opportunities for increased performance and lower costs. Industrial Internet of Things (IIoT) has a market forecast approaching $100 billion by 2020. Turning volumes of factory data into actionable information that has value is essential. Predictive maintenance and asset tracking are two big IoT markets to watch in 2018 because they will provide real efficiencies and improved safety. It will be about instrumenting our existing infrastructures with sensors that improve their reliability and help predict failures. It will be about tracking important assets through their lifecycles.
A new breed of designers has arrived that is leveraging inexpensive sensors to build the intelligent systems at the edge of the Internet of Things (IoT). They work in small teams, collaborate online, and they expect affordable design tools that are easy to use in order to quickly produce results. Their goal is to deliver a functioning device or a proof-of-concept to their stakeholders while spending as little money as possible to get there. We need to become multi-functional engineers who can comfortably work in the digital, RF, and system domains.
The Io edge sensor device usually needs to be cheap. Simple mathematical reasoning suggests that the average production cost per node must be small, otherwise the economics of the IoT simply are not viable. Most suppliers to the electronics industry are today working under the assumption that the bill-of-materials (BoM) cost of a node cannot exceed $5 on average. While the sensor market continues to garner billions of dollars, the average selling price of a MEMS sensor, for example, is only 60 cents.
Designing a well working and secure IoT system is still hard. IoT platforms are very complex distributed systems and managing these distributed systems is often an overlooked challenge. When designing for the IoT, security needs to be addressed from the Cloud down to each and every edge device. Protecting data is both a hardware and a software requirement, as more data is being stored and analyzed in edge devices and gateways.
The continued evolution of powerful embedded processors is enabling more functionality to be consolidated into single heterogeneous multicore devices. You will see more mixed criticality designs – those designs which contain both safety-critical and non-safety critical processes running on the same chip. It’s quickly becoming common practice for embedded system developers to isolate both safety and security features on the same SoC.
AI
There is clearly a lot of hype surrounding machine learning (ML) and artificial intelligence (AI) fields. Over the past few years, machine learning (ML) has evolved from an interesting new approach that allows computers to beat champions at chess and Go, into one that is touted as a panacea for almost everything. Machine learning already has delivered beneficial results in certain niches, but it has potential for a bigger and longer lasting impact because of the demand for broad insights and efficiencies across industries. Also EDA companies have been investing in this technology and some results are expected to be announced.
The Battle of AI Processors Begins in 2018. Machine learning applications have a voracious appetite for compute cycles, consuming as much compute power as they can possibly scrounge up. As a result, they are invariably run on parallel hardware – often parallel heterogeneous hardware—which creates development challenges of its own. 2018 will be the start of what could be a longstanding battle between chipmakers to determine who creates the hardware that artificial intelligence lives on. Main contenders on the field at the moment are CPUs, GPUs, TPUs (tensor processing units), and FPGAs. Analysts at both Research and Markets and TechNavio have predicted the global AI chip market to grow at a compound annual growth rate of about 54% between 2017 and 2021.
Sources:
Battery Market Goes Bigger and Better in 2018
Smart speakers to outsell wearables during U.S. holidays, as demand for wearables slows
Wearables Shipments Expected to Double by 2021
The Week In Review: Manufacturing #186
Five technology trends for 2018
NI Trend Watch 2018 explores trends driving the future faster
Creating Software Separation for Mixed Criticality Systems
Isolating Safety and Security Features on the Xilinx UltraScale+ MPSoC
Meeting ISO 26262 Software Standards
DRAM Growth Projected to be Highest Since ’94
NAND Market Expected to Cool in Q1
Memory Market Forecast 2018 … with Jim Handy
3D NAND Storage Fuels New Age of Smartphone Apps
$55.9 Billion Semiconductor Equipment Forecast – New Record with Korea at Top
Advanced Packaging Is Suddenly Very Cool
Apple Watch 3 shipment growth to benefit Taiwan IC packagers in 2018
Rapid SoC Proof-of-Concept for Zero Cost
EDA Challenges Machine Learning
What Can You Expect from the New Generation of Power Supplies?
Optimizing Machine Learning Applications for Parallel Hardware
FPGA-dataa 10 kertaa nopeammin
Chipmakers Look To New Materials
What the Experts Think: Delivering the next 5 years of semiconductor technology
Programmable Logic Holds the Key to Addressing Device Obsolescence
The Battle of AI Processors Begins in 2018
For China’s Memory Firms, Legal Tests May Loom
Predictions for the New Year in Analog & Power Electronics
Lithium-ion Overcomes Limitations
Will Fab Tool Boom Cycle Last?
The Next 5 Years Of Chip Technology
Chipmakers Look To New Materials
Process Window Discovery And Control
Sensors are Fundamental to New Intelligent Systems
Industrial IoT (IIoT) – Where is Silicon Valley
Internet of things (IoT) design considerations for embedded connected devices
How efficient memory solutions can help designers of IoT nodes meet tight BoM cost targets
1,325 Comments
Tomi Engdahl says:
Six Tips for Developing Your Next Test System
http://www.mwrf.com/test-measurement/six-tips-developing-your-next-test-system?NL=MWRF-001&Issue=MWRF-001_20180315_MWRF-001_347&sfvc4enews=42&cl=article_1_b&utm_rid=CPG05000002750211&utm_campaign=15913&utm_medium=email&elq2=732567f6d2d24a039a8653655eab64c7
This application note offers a framework for developing test systems, addressing tradeoffs and common problems.
RF/microwave test systems are each associated with specific circumstances, requirements, and challenges. Three universal factors come into play when defining any test system: performance, speed, and repeatability. Achieving the test system’s required level of measurement integrity involves making tradeoffs between the three factors mentioned. In the application note “6 Hints for Enhancing Measurement Integrity in RF/Microwave Test Systems,” Keysight Technologies discusses these tradeoffs and offers suggestions on how to address common problems.
Tomi Engdahl says:
CMOS-Embedded STT-MRAM Arrays In 2xnm Nodes For GP-MCU Applications
A look at robust STT-MRAM technology, including full array functionality with low bit-error rate.
https://semiengineering.com/cmos-embedded-stt-mram-arrays-in-2xnm-nodes-for-gp-mcu-applications/
Perpendicular Spin-Transfer Torque (STT) MRAM is a promising technology in terms of read/write speed, low power consumption and non-volatility, but there has not been a demonstration of high density manufacturability at small geometries. In this paper we present an unprecedented demonstration of a robust STT-MRAM technology designed in a 2x nm CMOS- embedded 40 Mb array.
https://www.globalfoundries.com/sites/default/files/technicalpaper/tp-cmos-embedded_stt-mram_arrays_in_2x_nm_nodes_for_gp-mcu_applications.pdf
Tomi Engdahl says:
New Applications, Multiple Approaches
Increasing density in chips is no longer the only path forward.
https://semiengineering.com/new-applications-multiple-approaches/
Tomi Engdahl says:
Trump Wants Critical Metals
https://semiengineering.com/trump-wants-critical-metals/
U.S. wants to reduce its dependence of critical metals/minerals.
Tomi Engdahl says:
More Lithography/Mask Challenges
https://semiengineering.com/more-lithography-mask-challenges/
Experts at the Table, part 1: EUV ramps up, but high-volume manufacturing isn’t likely to begin until at least the end of the year, maybe later.
Tomi Engdahl says:
DSA Re-Enters Litho Picture
https://semiengineering.com/dsa-re-enters-litho-picture/
Why this technology is getting a serious look at 5/3nm and beyond, and who’s driving it.
Directed self-assembly (DSA) is moving back onto the patterning radar screen amid ongoing challenges in lithography.
Intel continues to have a keen interest in DSA, while other chipmakers are taking another hard look at the technology, according to multiple industry sources. DSA isn’t like a traditional lithography technology, though. It’s a complementary patterning approach that enables fine pitches using block copolymers. In DSA, a lithography system forms a pre-defined pattern on a structure. The structure is coated with block copolymers, which then self-assemble in tiny patterns, such as contacts and lines/spaces, with dimensions at 12nm and below.
DSA resembles a multiple patterning scheme, but in theory it is less expensive than traditional techniques. Up until about three years ago, the industry was gung-ho about DSA, with plans to insert the technology anywhere from 14nm to 7nm.
That never happened. Roughly two years ago, DSA lost some momentum as the industry ran into defect issues and other challenges, preventing it from moving into high-volume manufacturing. At the same time, the industry put more resources behind extreme ultraviolet (EUV) lithography.
Today, though, DSA is making noticeable progress with some intriguing possibilities entering the picture.
Tomi Engdahl says:
Non-Traditional Chips Gaining Steam
https://semiengineering.com/non-traditional-chips-gaining-steam/
Flexible hybrid electronics are showing up in a variety of markets where electronics never existed before.
Flexible hybrid electronics are beginning to roll out in the form of medical devices, wearable electronics and even near-field communications tags in retail, setting the stage for a whole new wave of circuit design, manufacturing and packaging that reaches well beyond traditional chips.
FHE devices begin with substrates made of ceramics, glass, plastic, polyimide, polymers, polysilicon, stainless steel, textiles, and other materials. They can be anything from flexible chips to conductive ink printed onto fabrics.
Tomi Engdahl says:
Installing Open-Frame and U-Channel AC-DC Power Supplies
http://www.electronicdesign.com/power/installing-open-frame-and-u-channel-ac-dc-power-supplies?NL=ED-003&Issue=ED-003_20180315_ED-003_959&sfvc4enews=42&cl=article_1_b&utm_rid=CPG05000002750211&utm_campaign=15940&utm_medium=email&elq2=4382cbd6eb314083bf92faffa07ae4a9
Engineers must be wary of safety, electromagnetic-compatibility, and thermal-management factors when installing open-frame and U-channel power supplies.
Typically, power supplies are supplied in what is known by the industry as an open-frame format. Open frame generally describes a PCB-only-construction, component power supply designed to be installed into an end-equipment application that provides the enclosure for the entire product
Another common format for power supplies for integration into end equipment is the U channel, where the power-supply PCB is installed in a U-shaped, usually aluminum, chassis that’s often used as a part of the thermal management of the power semiconductors (Fig. 2). It also provides multiple fixing options for the equipment manufacturer to install the supply into the final assembly.
There are several considerations when installing open-frame and U-channel power supplies. Principally, they’re related to safety, electromagnetic compatibility (EMC), and thermal management, all of which are discussed in this article.
Tomi Engdahl says:
Broadcom Eyes New Acquisition Targets
https://www.eetimes.com/document.asp?doc_id=1333084
Broadcom executives said the company is eyeing fresh potential targets for acquisition, just days after U.S. President Donald Trump quashed the company’s proposed $117 billion hostile takeover attempt of rival Qualcomm.
“We do see potential [acquisition] targets that are consistent with our proven business model and that also can drive returns well in excess of what we would otherwise achieve buying our own stock and/or paying down debt,” said Tom Krause, Broadcom’s chief financial officer, in a conference call with analysts to discuss the company’s fiscal first quarter financial results.
Tomi Engdahl says:
New Applications, Multiple Approaches
Increasing density in chips is no longer the only path forward.
https://semiengineering.com/new-applications-multiple-approaches/
It may be tempting to view the strong demand for semiconductors as just one more up-cycle in our traditionally cyclical industry, but what’s really driving things right now is the opening of entirely new horizons, made possible by the increased capabilities of today’s chips.
Chip demand is no longer only being driven by the needs of computer and smartphone manufacturers. Now, a mushrooming number of new and varied applications within many different industries is both creating demand and pushing chip technology in new directions. Therefore, while the traditional goal of developing faster, denser semiconductors remains very important, it is no longer the only path forward.
We see the following sectors as major drivers of semiconductor demand going forward, in addition to traditional computing and smartphone applications: sophisticated Internet of Things (IoT) applications; 5G and wireless networking; automotive; and artificial intelligence/machine learning (AI/ML).
Tomi Engdahl says:
Startup Aims to Make Swallowed Batteries Safer For Kids
https://spectrum.ieee.org/the-human-os/biomedical/devices/startup-wants-to-make-swallowed-batteries-safer-for-kids
Button batteries are the lifeblood of modern portable electronics, but they can also be death traps for small children. A startup called Landsdowne Labs is developing a new kind of pressure-sensitive coating to make them safer.
The company’s ‘battery armor’ is made of silicon laced through with metal microparticles. In the low-pressure environment of a child’s esophagus, it renders inert these squat cylindrical batteries found inside remote controls, flashlights, musical greeting cards and toys of all kinds.
“It’s essentially a waterproof insulating coating that, when you apply force to it, converts into a conductor,” explains Jeff Karp, a bioengineer at Brigham Women’s Hospital in Boston.
Tomi Engdahl says:
CMOS Depletion-mode technology holds many advantages
https://www.edn.com/design/integrated-circuit-design/4460423/CMOS-Depletion-mode-technology-holds-many-advantages?utm_source=Aspencore&utm_medium=EDN&utm_campaign=social
Traditionally, the depletion MOSFET was classified as a linear device because the conduction channel between source and drain could not be pinched off and was thus unqualified for digital switching. The seed of this misconception was planted by Dr. Dawon Kahng, who invented the first depletion MOSFET – with only three terminals – in 1959.
When Frank Wanlass invented CMOS technology by using a complementary pair of four-terminal enhancement MOSFETs in 1963, Dr. Kahng had already moved on and ended his research work with depletion MOSFETs.
The bias against depletion MOSFETs was finally discovered and rectified by this author in 2007 with the introduction of the four-terminal depletion MOSFET.
allowing depletion MOSFETs to be used as digital switches, and CMOS positive logic technology was finally born.
The discovery of positive logic operation from depletion MOSFETs was significant in three respects. Firstly, CMOS products can become intrinsically safe from damage caused by ESD events, even when they are handled without ESD protection. Secondly, the non-inverting buffer and 1T memory cell can save half of the cost for SRAM and DRAM. And lastly, since the gate control voltage always has the same potential as the conduction channel when the depletion MOSFET is conducting current, the gate leakage current of enhancement MOSFETs that stymied Moore’s Law between 2004 and 2009 suddenly disappears, regardless of how thin the insulator between gate and conduction channel has become. Moore’s Law is back again!
For an enhancement MOSFET, the potential at the gate is always opposite to the potential of the conduction channel when it is conducting currents; consequently, the insulator under the gate has to withstand a large potential difference.
The implementation of a depletion MOSFET is very much the same as an enhancement MOSFET, except the additional requirement to implant a shallow conduction channel below the insulator
SPICE can only simulate the depletion MOSFET as a linear device to be operated in the enhancement mode
Once we establish the four fundamental switching circuits shown in the previous section, we can build the following two CMOS circuits naturally
It is possible to use a single MOSFET as the memory cell to store data; however, since a single MOSFET can only lock in a logic state, it would require refreshment mechanism to maintain the unlocked state as is commonly used in the DRAM applications
All traditional MOSFET products are subject to damage caused by electrostatic discharge, especially when they are not powered up.
It was very difficult to design a low impedance circuit that protected the enhancement MOSFET when the system was not powered up and at the same time, did not consume power when the system was powered up.
But ESD protection is never a problem for depletion MOSFETs since the low impedance conduction channel always exists before the system is powered. A simple ESD protection circuit as in Figure 11 can protect the high impedance gate input from ESD events
I hope to see depletion-based CMOS devices implemented soon so experience can be gained with them.
Tomi Engdahl says:
Qualcomm’s war may be over, but the casualties are just starting to be calculated
https://techcrunch.com/2018/03/17/qualcomms-casualties/?utm_source=tcfbpage&utm_medium=feed&utm_campaign=Feed%3A+Techcrunch+%28TechCrunch%29&utm_content=FaceBook&sr_share=facebook
Following a bruising merger fight, the company faces battles on four fronts
It may be all quiet on the semiconductor front, but Qualcomm and Broadcom will now need to find a path forward to win the peace and secure access to the coming 5G wireless market. Qualcomm faces a daunting number of challenges, including a potential takeover battle waged by the spurned son of its founder. Broadcom will have to find a new path to use acquisitions to continue its growth.
Tomi Engdahl says:
Control ICs Modulate Power in an Explicit Way
http://www.powerelectronics.com/pmics/control-ics-modulate-power-explicit-way
Power Integrations introduces a family of ICs designed to dynamically control the power and voltage of a power supply.
Tomi Engdahl says:
Top 30 Companies
http://www.powerelectronics.com/community/top-30-companies?PK=UM_Classics03118&utm_rid=CPG05000002750211&utm_campaign=15953&utm_medium=email&elq2=51e2b85249664656ae7a85e4a4f57f8c
Manufacturers of power semiconductors, motorcontrols and power supplies have shaped thedevelopment of power electronics technologywhile building a multibillion dollar industry thatsupports the rest of the electronics industry.
Tomi Engdahl says:
Step-Down dc-dc Converter Eliminates Ferrite Cores at 50kHz Enabling Power Supply on Chip with One-Cycle Transient
http://www.powerelectronics.com/power-management/step-down-dc-dc-converter-eliminates-ferrite-cores-50khz-enabling-power-supply-chip?PK=UM_Classics03118&utm_rid=CPG05000002750211&utm_campaign=15953&utm_medium=email&elq2=51e2b85249664656ae7a85e4a4f57f8c
Virtually all present-day DC-DC converters store DC energy in magnetic devices with ferrite cores, such as inductors with DC bias. A new topology for non-isolated step-down dc-dc converters discards ferrite cores completely. The new Resonance Scaling Method results in use of 10nH resonant inductors even at 50kHz switching frequency and an effective factor of 1,000 times reduction of the magnetic size and weight of comparable buck converter at 50kHz.This opens a new power electronics era with the first true Power-Supply-on-a-Chip.
Tomi Engdahl says:
DRAM stocks soar on forecast of higher product prices
http://focustaiwan.tw/news/aeco/201803160008.aspx
Taipei, March 16 (CNA) Shares of dynamic random access memory (DRAM) chip makers in Taiwan soared Friday on expected higher product prices this year, dealers said.
Tomi Engdahl says:
Non-Traditional Chips Gaining Steam
https://semiengineering.com/non-traditional-chips-gaining-steam/
Flexible hybrid electronics are showing up in a variety of markets where electronics never existed before.
Flexible hybrid electronics are beginning to roll out in the form of medical devices, wearable electronics and even near-field communications tags in retail, setting the stage for a whole new wave of circuit design, manufacturing and packaging that reaches well beyond traditional chips.
FHE devices begin with substrates made of ceramics, glass, plastic, polyimide, polymers, polysilicon, stainless steel, textiles, and other materials. They can be anything from flexible chips to conductive ink printed onto fabrics.
Brewer Science, Molex, and Thin Film Electronics (Thinfilm) are among the companies making products with flexible substrates. NXP Semiconductors and STMicroelectronics are fabricating flexible NFC tags encasing their silicon-based microchips.
Tomi Engdahl says:
Opinion: How a SoftBank buyout of Qualcomm could change the world of technology
https://www.marketwatch.com/story/how-a-softbank-buyout-of-qualcomm-could-change-the-world-of-technology-2018-03-16
Former Qualcomm CEO Paul Jacobs, who’s now a board member, is in talks with “several global investors” to buy out the San Diego-based chip maker, according to media reports including the Wall Street Journal.
A potential partner in this deal is SoftBank SFTBY, -0.17% a Japan-based holding company with stakes in companies including semiconductor and software design company Arm, wireless provider Sprint S, -0.65% and e-commerce giant Alibaba BABA, -1.72%
A buyout of Qualcomm QCOM, -2.05% could drastically shift the landscape of the technology market, maybe even more so than an acquisition by Broadcom AVGO, -1.54% would have. (The U.S. government scuttled an attempted takeover.)
The company with the most to lose in this rumored buyout would be Intel, as a combined Qualcomm and Arm technology house would add pressure to the many markets in which the three are competitive, including mobile PCs, the internet of things (IoT), automotive systems, data centers and more.
Tomi Engdahl says:
AI, 5G may drive global IC revenues to US$500 billion, says SEMI president
http://www.digitimes.com/news/a20180319PD210.html
After soaring 22.3% on year to hit a 7-year annual high of US$420 billion in 2017, the global semiconductor revenues will enter a new round of growth mainly driven by AI and 5G technologies and applications and may challenge US$500 billion in the foreseeable future. And revenues from diverse semiconductor segments are expected to see a more balanced growth in 2018 although a double-digit overall growth would be a little hard to achieve, according to Ajit Manocha, president and CEO of SEMI.
Tomi Engdahl says:
AI: The Next Big Thing
https://semiengineering.com/ai-the-next-big-thing/
And it’s going to push the limit on semiconductor design, manufacturing and packaging.
The next big thing isn’t actually a thing. It’s a set of finely tuned statistical models. But developing, optimizing and utilizing those models, which collectively fit under the umbrella of artificial intelligence, will require some of the most advanced semiconductors ever developed.
The demand for artificial intelligence is almost ubiquitous. As with all “next big things,” it is a horizontal technology that plays across many vertical market segments. Specialized chips are being developed for the cloud, for mid-range devices, and for edge devices in order to enable AI and its building blocks—machine learning, deep learning, neural networks. Many of these components are being designed for the advanced nodes using the most advanced manufacturing processes, which collectively will propel Moore’s Law, “More Than Moore,” and just about everything connected to semiconductors well into the future.
Tomi Engdahl says:
Charge Pump DC/DC Controller IC Eliminates Magnetics, Configures Bus Converter
http://www.powerelectronics.com/power-management/charge-pump-dcdc-controller-ic-eliminates-magnetics-configures-bus-converter?code=UM_AT17TIPwr8&utm_rid=CPG05000002750211&utm_campaign=14073&utm_medium=email&elq2=8a2617b0fdd341d49b6636f22cee46cc
A charge pump DC/DC controller IC and four external MOSFETS eliminate magnetic components in a non-isolated intermediate bus converter (IBC). The combination provides 2:1 step-down ratio,1:2 step-up ratio, or 1: –1 ratio as an inverter.
Linear Technology’s LTC7820 is a high-power fixed-ratio charge pump dc/dc controller IC that eliminates the need for any magnetic component in a non-isolated intermediate bus converter (IBC). This provides up to a 50% reduction in circuit size and up to 4000W/in.3 power density
Tomi Engdahl says:
EUV’s New Problem Areas
https://semiengineering.com/euvs-new-problem-areas/
Random variations will require new methodologies, tools and cooperation among different companies.
Extreme ultraviolet (EUV) lithography is moving closer to production, but problematic variations—also known as stochastic effects—are resurfacing and creating more challenges for the long-overdue technology.
GlobalFoundries, Intel, Samsung and TSMC hope to insert EUV lithography into production at 7nm and/or 5nm. But as before, EUV consists of several components that must come together before chipmakers can insert it. These include the scanner, power source, resists and masks. And more recently, the industry has begun sounding the alarm about stochastics, a phenomenon that involves random variations.
Tomi Engdahl says:
Xilinx to bust ACAP in the dome of data centres all over with uber FPGA
That’s an Adaptive Compute Acceleration Platform btw
https://www.theregister.co.uk/2018/03/19/xilinx_everest_acap_super_fpga/
Xilinx is developing a monstrous FPGA that can be dynamically changed at the hardware level.
The biz’s “Everest” project is the development of what Xilinx termed an Adaptive Compute Acceleration Platform (ACAP), an integrated multi-core heterogeneous design that goes way beyond your bog-standard FPGA, apparently. It is being built with TSMC’s 7nm process technology and tapes out later this year.
Xilinx Unveils Revolutionary Adaptable Computing Product Category
https://www.xilinx.com/news/press/2018/xilinx-unveils-revolutionary-adaptable-computing-product-category.html
ACAP TECHNICAL DETAILS
An ACAP has – at its core – a new generation of FPGA fabric with distributed memory and hardware-programmable DSP blocks, a multicore SoC, and one or more software programmable, yet hardware adaptable, compute engines, all connected through a network on chip (NoC). An ACAP also has highly integrated programmable I/O functionality, ranging from integrated hardware programmable memory controllers, advanced SerDes technology and leading edge RF-ADC/DACs, to integrated High Bandwidth Memory (HBM) depending on the device variant.
Software developers will be able to target ACAP-based systems using tools like C/C++, OpenCL and Python. An ACAP can also be programmable at the RTL level using FPGA tools.
“This is what the future of computing looks like,” says Patrick Moorhead, founder, Moor Insights & Strategy. “We are talking about the ability to do genomic sequencing in a matter of a couple of minutes, versus a couple of days. We are talking about data centers being able to program their servers to change workloads depending upon compute demands, like video transcoding during the day and then image recognition at night. This is significant.”
ACAP has been under development for four years at an accumulated R&D investment of over one billion dollars (USD). There are currently more than 1,500 hardware and software engineers at Xilinx designing “ACAP and Everest.” Software tools have been delivered to key customers. “Everest” will tape out in 2018 with customer shipments in 2019.
Tomi Engdahl says:
TSMC to enter 7nm chip shipments for new Xilinx ACAP in 2019
https://www.digitimes.com/news/a20180320PD215.html
Xilinx has introduced a new product category called adaptive compute acceleration platform (ACAP) – a highly integrated multi-core heterogeneous compute platform – for big data and AI applications. The new product family will be developed using 7nm process technology at Taiwan Semiconductor Manufacturing Company (TSMC) and will tape out later this year, with customer shipments set to kick off in 2019, according to the FPGA chip vendor.
Xilinx said ACAP goes far beyond the capabilities of an FPGA. An ACAP is a highly integrated multi-core heterogeneous compute platform that can be changed at the hardware level to adapt to the needs of a wide range of applications and workloads. An ACAP’s adaptability, which can be done dynamically during operation, delivers levels of performance and performance per-watt that is unmatched by CPUs or GPUs, th evendor claimed.
An ACAP is suited to accelerate a broad set of applications in the emerging era of big data and AI, said Xilinx. These include: video transcoding, database, data compression, search, AI inference, genomics, machine vision, computational storage and network acceleration.
Tomi Engdahl says:
Buffered Octal ADC Inputs Simplify Sensor Interfaces
https://www.youtube.com/watch?v=mqGXe1BioNw&index=1&list=PL40wCgbP6rqF3Mfr57d2CSN9B7wYY7wv8
Many systems using a precision analog-to- digital converter to digitize signals need some signal conditioning circuitry between the signal source and the ADC. In addition to its other functions, that circuitry must accurately drive the input of the ADC. The combined demands of performance and high speed to handle the ADC input currents can present a substantial additional design challenge.
Tomi Engdahl says:
Why build a custom chip?
https://www.youtube.com/watch?v=GIuf5w73Ufw&t=31s&list=PLDglzuv1g_h9_TdwOGDnQLorJ6gtOGz7W&index=
Reduce BOM by 80%, power consumption by 75% and add new product features. Find out how
Tomi Engdahl says:
Anyside™ Isolated Switch Controller with I²C Command and Telemetry
https://www.youtube.com/watch?v=r2dT-OQKACI&list=PLDglzuv1g_h-Ch5QlzRzj_cRTY-zWnNr1&index=1
Hot swap integrated circuits are used to limit inrush current in either low-side or high-side DC applications. The application operating voltage is generally limited by the integrated circuits operating voltage, typically less than 100 volts. The LTM9100 allows the control of inrush current in both low-side and high-side applications operating up to 1000 VDC.
Tomi Engdahl says:
Supercapacitors: Past, Present, and Future
http://www.powerelectronics.com/alternative-energy/supercapacitors-past-present-and-future?NL=ED-003&Issue=ED-003_20180320_ED-003_437&sfvc4enews=42&cl=article_1_b&utm_rid=CPG05000002750211&utm_campaign=16029&utm_medium=email&elq2=d0c66712a149476f8fd139ad2b30eb76
Though the idea of supercapacitors has been around since the 19th century, current technologies are finally realizing the advanced energy storage that was always deemed possible.
Tomi Engdahl says:
The world’s smallest regulator
Toshiba Electronics Europe has begun to provide its customers with a new LDO regulator that it boasts of the smallest market. The TCR15AG series regulators produce a 1.5 amp current from a WCSP6F enclosure of 1.2 x 0.8 x 0.3 millimeters.
The regulator family has 47 different voltage alternatives. It is suitable for power supply in all RF applications, such as wifi chipsets or IoT modules.
Source: http://www.etn.fi/index.php/13-news/7737-maailman-pienin-regulaattori
Tomi Engdahl says:
STMicroelectronics Delivers Next-Generation FlightSense™ Time-of-Flight Sensor
https://www.eeweb.com/profile/eeweb/news/stmicroelectronics-delivers-next-generation-flightsense-time-of-flight-sensor
The VL53L1X time-of-flight sensor from STMicroelectronics extends the detection range of ST’s FlightSense* technology to four meters, bringing high-accuracy, low-power distance measurement, and proximity detection to an even wider variety of applications.
Unlike other proximity sensors that use simple IR (Infra-Red) technology, which only measure signal strength and can be affected by the object’s reflectivity, FlightSense sensors directly measure distance to the object based on the time for emitted photons to be reflected, enabling accurate distance-ranging regardless of the object’s surface characteristics.
With low power consumption and fast ranging performance, the VL53L1X is ideal for mobile robotics for wall following, cliff detection, collision avoidance and hover/landing assistance for drones or unmanned aerial vehicles (UAVs). The power-saving presence-detection mode enables innovative auto-sleep/wake-on-approach use cases for PCs, notebooks and IoT devices, in addition to camera auto-focus assist, and gesture recognition.
Tomi Engdahl says:
Foundry Pursues Custom Path
https://www.eetimes.com/author.asp?section_id=36&doc_id=1333078
The SkyWater 200mm foundry in an office park outside the Mall of America in Bloomington, Minnesota, shows avenues for growth making semiconductors at 90nm and larger nodes, far from the bleeding-edge pursuit of Moore’s law.
Built in 1986 by Control Data and purchased by Cypress in 1991, the facility first opened to outside work under the Cypress name in 2008. A year ago, the fab was sold for $30 million to a private equity firm, creating the independent foundry.
Tomi Engdahl says:
SoftBank could relist British chip designer ARM: FT
https://www.reuters.com/article/us-arm-holdings-ipo/softbank-could-relist-british-chip-designer-arm-ft-idUSKBN1GV1G8
SoftBank Group Corp could relist ARM Holdings, the British chip designer it bought two years ago, according to a senior executive at the Japanese conglomerate, the Financial Times reported on Monday.
Yoshimitsu Goto, a senior corporate officer at SoftBank, suggested to investors that an initial public offering could be a potential exit strategy
The $93 billion Vision Fund, backed by Saudi Arabia’s main sovereign wealth fund and companies including Apple and Qualcomm, is set to acquire a 25 percent stake in ARM, the report added.
Tomi Engdahl says:
Semiconductors are the latest fashion in China
Foreign and local chipmakers eye big opportunities as Beijing champions sector
https://asia.nikkei.com/Politics-Economy/Economy/Semiconductors-are-the-latest-fashion-in-China
If China’s burgeoning semiconductor industry was a nation, its gross domestic product would have grown at an average rate of some 20% in recent years, faster than any country on the planet.
For many investors, involvement in the sector in China represents a once-in-a-lifetime business opportunity, while for some existing semiconductor players the country’s chip ambitions could be seen as a threat. For local ventures, the semiconductor sector is the place to be. For government officials, it is a top priority, as highlighted by Premier Li Keqiang in his report during the recent National People’s Congress.
Tomi Engdahl says:
Carbon Allotrope Claims Edge Over GaN, Graphene
https://www.eetimes.com/document.asp?doc_id=1333099
An Abu Dhabi based company claims to have identified an allotrope of carbon that may be more suitable than gallium nitride (GaN) for opto-electronic components and applicable to more semiconductor device applications than carbon nanotubes (CNT) and graphene.
A paper on the topic, published in the scientific journal Carbon, shows the structure of a new carbon allotrope, protomene, which researchers say offers promise of tremendous advancements in the electronics industry as a single material.
Tomi Engdahl says:
Fab Tool Spending Projected to Rise for 3rd Straight Year
https://www.eetimes.com/document.asp?doc_id=1333093
Tomi Engdahl says:
EDA Chief Calls AI the New Driver
https://www.eetimes.com/document.asp?doc_id=1333101
It’s the age of AI, Moore’s Law is not dead, and technology is changing everything, according to Aart de Geus, co-chief executive of Synopsys, in a talk at the company’s annual user group conference here.
The advent of AI is a mile marker on par with the invention of the printing press and the steam engine, De Geus said.
“It will drive the semiconductor industry for the next few decades because Big Data needs machine learning and machine learning needs more computation, which generates more data. This will impact health, transportation and other vertical markets as they go digital,” he said.
Tomi Engdahl says:
Applying Machine Learning To Chips
https://semiengineering.com/applying-machine-learning-to-chips/
Goal is to improve quality while reducing time to revenue, but it’s not always so clear-cut.
Tomi Engdahl says:
Can Big Data Help Coverage Closure?
https://semiengineering.com/can-big-data-help-coverage-closure/
When does a large amount of data become Big Data, and could system-level verification benefit from it?
Tomi Engdahl says:
Merging Verification With Validation
https://semiengineering.com/merging-verification-with-validation/
Are these really separate tasks, or just a limitation of tools and flows?
Verification and validation are two important steps in the creations of electronic systems and over time their roles, but how they play together is changing. In fact, today we are seeing a major opportunity for rethinking this aspect of the flow, which could mean the end of them as separate tasks for many of the chips being created.
As with many things in this industry, however, squeezing it out of one part of the flow may just make it pop up in a different place, making it someone else’s responsibility.
First, we must define the terms. “If we define verification as the pre-silicon checking of an ASIC’s functionality against design intent, and validation as the post-silicon checking of a system’s functionality against market requirements, then we can understand why verification and validation have been treated as different tasks in the past,” says Michael Thompson, verification architect for Oski Technology. “Both technical and organizational reasons exist for this.”
Let’s start with verification. “Verification is a finite logical problem,” says Doug Amos, product marketing manager for Mentor, a Siemens Business. “We are asking the question, ‘What is the chance that my hardware has bugs?’ Modern coverage-driven techniques can give us a logical metric-based answer to that question, with the aim of getting as close to ‘no chance’ as possible. Our agony in verification is that we never reach ‘no chance,’ so we are left to decide when we are ‘close enough,’ and the tradeoff between conscience and pragmatism begins.”
Tomi Engdahl says:
Backup controller protects supercapacitors
https://www.edn.com/electronics-products/other/4460432/Backup-controller-protects-supercapacitors
The LTC3351 35-V hot-swap power controller IC from Analog Devices charges and monitors a series stack of one to four supercapacitors. It uses N-channel MOSFETs to provide a low-loss power path from the input to the output, plus foldback current limiting to reduce inrush current. The device enables reliable short-term uninterrupted power in the event of a main power failure for applications such as solid-state drives and nonvolatile DIMMs.
Tomi Engdahl says:
Analyze post-equalization ISI with pulse response
https://www.edn.com/electronics-blogs/eye-on-standards/4460406/Analyze-post-equalization-ISI-with-pulse-response
Any signal-integrity engineer will tell you that analyzing closed eye diagrams has never been easy. A transmission channel’s frequency response (or lack of bandwidth) causes inter-symbol interference (ISI), the primary eye-closing culprit. While I’ve written about closed eye analysis techniques before, this time we’ll measure the ISI left over after equalization, the so-called residual ISI. In the process, we’ll see the simple guts of decision feedback equalization (DFE).
The pulse response is gaining popularity in technology standards that define high-speed serial buses. You can produce a pulse with a pattern generator by transmitting a long string of zeros, a one, and then another long string of zeros, that is, a pulse is a non-return-to zero (NRZ) bit and the pulse response is the same as the SBR (single bit response).
Like the impulse response, the pulse response includes everything there is to know about the circuit, the impedances of every trace, connector, cable, pin, ball, and so on. It’s all built in, both magnitude and phase.
Analyzing closed eyes: CRJ and CDJ
https://www.edn.com/electronics-blogs/eye-on-standards/4441189/Analyzing-closed-eyes–CRJ-and-CDJ?utm_source=AspenCore&utm_medium=EDN
Tomi Engdahl says:
How Automotive ICs Are Reshaping Semiconductor Test
New manufacturing and in-system test strategies are required to meet safety requirements.
https://semiengineering.com/how-automotive-ics-are-reshaping-semiconductor-test/
Tomi Engdahl says:
Path to 2 nm May Not Be Worth It
Diminishing returns may evaporate at 5 nm
https://www.eetimes.com/document.asp?doc_id=1333109
Engineers see many options to create 5-, 3- and even 2-nm semiconductor process technologies, but some are not sure that they will be able to squeeze commercial advantages from them even at 5 nm.
The increasing complexity and cost of making ever-smaller chips is leading to diminishing returns. Data rates are peaking at 3 GHz for mobile processors, and power and area gains will narrow at 7 nm, said a Qualcomm engineer in a panel at a Synopsys user group event here.
Speed gains of 16% at 10 nm may dry up at 7 nm due to resistance in metal lines. Power savings will shrink from 30% at 10 nm to 10–25% at 7 nm, and area shrinks may decline from 37% at 10 nm to 20–30% at 7 nm, said Paul Penzes, a senior director of engineering on Qualcomm’s design technology team.
For decades, the electronics industry followed a roadmap codified by Moore’s law of doubling the number of transistors on a chip roughly every two years. The result was a fast pace of ever-smaller, faster, cheaper products from PCs to smartphones.
“Area still scales in strong double digits, but the hidden cost increases in masks means the actual cost advantages and other improvements are starting to slow down … It’s not clear what will remain at 5 nm,” said Penzes, suggesting that 5-nm nodes may only be extensions of 7 nm.
Versions of today’s FinFET transistors will be used down to the 5-nm node, said technologists from Synopsys and Samsung on the panel. Below a width of about 3.5 nm, FinFETs will hit a hard limit.
Panelists agreed that success depends on increasingly tight collaboration among foundry, EDA, and design engineers. Toward that goal, Qualcomm found that, to get optimal yields, it needs to tweak its leading-edge designs just before production starts, when the process node is more clearly defined.
“Because mobile processors are so competitive, foundries are putting in front of us less and less mature nodes,”
For example, Samsung has committed to specs for a 7-nm process with EUV and plans to make wafers this year, although it is still waiting on steppers
Tomi Engdahl says:
Researchers find a new material for quantum computing
https://techcrunch.com/2018/03/23/researchers-find-a-new-material-for-quantum-computing/?utm_source=tcfbpage&utm_medium=feed&utm_campaign=Feed%3A+Techcrunch+%28TechCrunch%29&utm_content=FaceBook&sr_share=facebook
Tomi Engdahl says:
5 Questions for HEMT Inventor Takashi Mimura
https://spectrum.ieee.org/tech-talk/semiconductors/devices/5-questions-for-hemt-inventor-takashi-mimura
Takashi Mimura invented something wonderful in 1979. The high-electron-mobility transistor was intended as a device that can operate at microwave frequencies with ease. HEMTs are capable of fast switching because they confine the flow of current through a very-thin, high conductance layer called a two-dimensional electron gas. But it’s the lack of noise in these transistors that really made their mark. They were integral to picking up the faint radio waves that carried Voyager 2’s photos of Neptune 1.3 billion kilometers to Earth in 1989, and now they’re in every satellite receiver you see. Mimura, a Fellow of the IEEE, won the coveted Kyoto Prize in 2017 for his efforts. He spoke to IEEE Spectrum through an interpreter on 21 March 2018.
Tomi Engdahl says:
Path to 2 nm May Not Be Worth It
Diminishing returns may evaporate at 5 nm
https://www.eetimes.com/document.asp?doc_id=1333109
ngineers see many options to create 5-, 3- and even 2-nm semiconductor process technologies, but some are not sure that they will be able to squeeze commercial advantages from them even at 5 nm.
The increasing complexity and cost of making ever-smaller chips is leading to diminishing returns. Data rates are peaking at 3 GHz for mobile processors, and power and area gains will narrow at 7 nm, said a Qualcomm engineer in a panel at a Synopsys user group event here.
Speed gains of 16% at 10 nm may dry up at 7 nm due to resistance in metal lines. Power savings will shrink from 30% at 10 nm to 10–25% at 7 nm, and area shrinks may decline from 37% at 10 nm to 20–30% at 7 nm, said Paul Penzes, a senior director of engineering on Qualcomm’s design technology team.
For decades, the electronics industry followed a roadmap codified by Moore’s law of doubling the number of transistors on a chip roughly every two years. The result was a fast pace of ever-smaller, faster, cheaper products from PCs to smartphones.
“Area still scales in strong double digits, but the hidden cost increases in masks means the actual cost advantages and other improvements are starting to slow down … It’s not clear what will remain at 5 nm,” said Penzes, suggesting that 5-nm nodes may only be extensions of 7 nm.
Tomi Engdahl says:
EDA Chief Calls AI the New Driver
https://www.eetimes.com/document.asp?doc_id=1333101
It’s the age of AI, Moore’s Law is not dead, and technology is changing everything, according to Aart de Geus, co-chief executive of Synopsys, in a talk at the company’s annual user group conference here.
The advent of AI is a mile marker on par with the invention of the printing press and the steam engine, De Geus said.
“It will drive the semiconductor industry for the next few decades because Big Data needs machine learning and machine learning needs more computation, which generates more data. This will impact health, transportation and other vertical markets as they go digital,” he said.
Tomi Engdahl says:
Step-Down dc-dc Converter Eliminates Ferrite Cores at 50kHz Enabling Power Supply on Chip with One-Cycle Transient
http://www.powerelectronics.com/power-management/step-down-dc-dc-converter-eliminates-ferrite-cores-50khz-enabling-power-supply-chip?code=UM_NN8DCDC2&utm_rid=CPG05000002750211&utm_campaign=14796&utm_medium=email&elq2=9f25c6b2cbc346bc99e40696c70c2c72
Virtually all present-day DC-DC converters store DC energy in magnetic devices with ferrite cores, such as inductors with DC bias. A new topology for non-isolated step-down dc-dc converters discards ferrite cores completely. The new Resonance Scaling Method results in use of 10nH resonant inductors even at 50kHz switching frequency and an effective factor of 1,000 times reduction of the magnetic size and weight of comparable buck converter at 50kHz.This opens a new power electronics era with the first true Power-Supply-on-a-Chip.
The groundbreaking PWM-Resonant Ćuk topology could revolutionize the design of non-isolated, step-down dc-dc converters. This new topology provides much higher-efficiency, fast-transient response settling in one cycle, with much smaller size and lower weight than its ferrite core cousins. This converter is ideal for 12V to 1V applications for supplying microprocessors, as it replaces four to eight modules of a multiphase buck converter with a single converter.
Obviously, it is equally beneficial in all step-down voltage applications. This topology reduces 10 nH resonant inductors to copper traces on the board at even 50kHz and enables high-power, ultra-high efficiency, and unprecedented power density at reduced cost.
New Switching Method and Topology with Two Resonant Inductors
Obviously, there was all along a need to eliminate this DC inductor of buck converter and replace it with one or more resonant inductors which would in a single stroke eliminate both DC current and power limitations of the buck converter. To achieve this required several complementary groundbreaking inventions:
New switching method with two resonant inductors, defining two switching subintervals, each consisting of separately controlled resonances.
Appropriate switching devices topology limiting each resonant current to only its positive current in order to establish voltage regulation using conventional duty ratio control and constant switching frequency.
Resonances Scaling Method to reduce inductances to ultra-low values even at moderate to low switching frequencies of 50kHz or less.
This is accomplished in the PWM-Resonant Ćuk converter
This new converter topology uses two air-core ac inductors that do not need coil windings. Based on new and general Resonance Scaling Method, the two inductances can be as low as 10nH, even at low 50kHz switching frequency. The resonant inductors can be implemented with only 5mm long or shorter copper wire or as a short trace on a circuit board.
An early experimental prototype of a 200W, 48V to 24V, step-down converter was built (Fig. 8). Efficiency measurements shown in Fig. 9 demonstrate ultra-high efficiency over 99% over wide current range from 3A to 12A and nearly 99% at the full load of 15A.
Tomi Engdahl says:
Abstracting Abstracter Abstractions In Functional Verification
https://semiengineering.com/abstracting-abstracter-abstractions-in-functional-verification/
With the upcoming Portable Stimulus standard, we need to consider whether abstraction is really the answer to everything.
I heard a clear three-part message during DVCon at the end of February:
verification engineers must abstractly embrace the abstract idea of abstracting abstract abstraction through higher levels of abstraction;
we overuse the word abstract to emphasize the value of whatever verification technique we happen to be talking about; and
the key to new abstractions is using Portable Stimulus as abstractly as possible.
Hopefully we can agree those first two points aren’t all that new. The third is definitely new’ish… at least it is to me.
Seems Portable Stimulus is the newest next big thing and it comes with the promise of abstraction-induced productivity. I don’t know much about Portable Stimulus yet, but I’m pretty comfortable with the idea of abstraction so I thought it’d be interesting to take a look back at how successful we’ve been at creating new design abstractions and give people the chance to ponder how it may turn out with Portable Stimulus.
To review: we nailed abstraction with RTL and IP; design capture in higher level software languages for the mainstream is too abstract; TLM isn’t abstract enough.
Which brings us to the next big thing. One of the selling points of Portable Stimulus is that it offers modeling and test at a level of abstraction more productive than where we are now. Given our history of mixed results, I think it’s only natural to question whether or not that’ll end up being the case.