https://www.darrentoback.com/can-risc-v-linux-of-microprocessors-start-an-open-hardware-renaissance
RISC-V is an interesting open hardware CPU. It is the most promising open CPU design, but can it succeed in competitive CPU market?
https://www.darrentoback.com/can-risc-v-linux-of-microprocessors-start-an-open-hardware-renaissance
RISC-V is an interesting open hardware CPU. It is the most promising open CPU design, but can it succeed in competitive CPU market?
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Tomi Engdahl says:
https://www.embedded.com/lauterbach-adds-debug-and-trace-support-for-renesas-32-bit-risc-v-microcontrollers
Tomi Engdahl says:
RISC-V Builds the Backbone of Three New Consumer Devices
https://www.allaboutcircuits.com/news/risc-v-builds-backbone-three-new-consumer-devices/
RISC-V, the open-standard ISA, has inspired a host of innovative designs in tablets, cameras, and laptops.
In the past few years, RISC-V has transitioned from a project relegated to academia to a mainstay in the consumer marketplace. Devices ranging from smartphones to laptops are now built around a RISC-V architecture. DeepComputing, Seeed Studio, and Milk-V recently released new electronics—mobile devices, cameras, and laptops—based on the RISC-V. Here are a few creative ways the companies have leveraged the ISA.
Tomi Engdahl says:
Ruotsissa kehitettiin maailman ensimmäinen painettu RISC-V-prosessori
https://etn.fi/index.php/13-news/16648-ruotsissa-kehitettiin-maailman-ensimmaeinen-painettu-risc-v-prosessori
Maailman ensimmäinen painettu Risc-V-piiri on ruotsalainen. Olof Kindgrenin Flex IC -suunnittelu on julkistettu arvostetussa Nature-tiedelehdessä.
Yksi Olof Kindgrenin saavutuksista on se, että hän on suunnitellut Servin (SERV), joka on maailman pienin RISC V -suoritin porteilla mitattuna. Ja kun brittiläinen Pragmatic halusi puristaa prosessorin painettuun elektroniikkaan – jossa portin koko on jättimäinen piiprosesseihin verrattuna – Serv oli luonnollinen valinta.
Prosessin Flex IC (FlexIC) viivan leveys on 0,6 µm. Se on kustannustehokas, ja sen läpimenoaika suunnittelusta valmiiseen piiriin on neljä viikkoa verrattuna useisiin kuukausiin piiprosesseihin.
Tieteellinen projekti toteutettiin yhteistyössä Pragmaticin, amerikkalaisen Harvardin yliopiston ja Olof Kindgrenin työnantajan Qamcomin kanssa
Koko piiri on mikroprosessori nimeltä Flex-RV. Flex-RV:n pinta-ala on 17,5 mm² ja se koostuu 12 596 NAND-tyyppisestä IGZO-TFT-transistoreista. Piirin tehonkulutus on 6 milliwattia ja sisältää Servin lisäksi tekoälykiihdyttimen.
Tomi Engdahl says:
https://www.uusiteknologia.fi/2024/10/14/suomalainen-risc-v-piiri-paasi-testeihin-330-miljoonaa-transistoria/
Tomi Engdahl says:
https://etn.fi/index.php/13-news/16708-tampereen-soc-hubin-monimutkaisin-risc-v-piiri-on-testattava
Tomi Engdahl says:
https://hackaday.com/2024/10/14/a-risc-v-lisp-compiler-written-in-lisp/
Tomi Engdahl says:
Suomalaistekniikka tekee RISC-V-prosessoreista sata kertaa tehokkaampia
https://etn.fi/index.php/13-news/16723-suomalaistekniikka-tekee-risc-v-prosessoreista-sata-kertaa-tehokkaampia
Suomalainen Flow Computing kohahdutti viime kesänä väittämällä, että sen rinnakkaisen laskennan PPU-arkkitehtuuri parantaa kaikkien nykyaikaisten prosessorien suorituskykyä merkittävästi. Nyt Flow on liittynyt RISC-V Internationaliin ja lupaa 100-kertaisen tehonlisäyksen jopa kaikissa nykyisissä RISC-V-suunnitteluissa.
RISC-V on näin ensimmäinen Flow Computingin PPU-tekniikan virallisesti tukemana CPU-arkkitehtuuri. Yhtiön mukaan PPU-parannetut RISC-V-suunnittelut ovat täysin yhteensopivia kaikkien olemassa olevien RISC-V-suoritinarkkitehtuurin ohjelmistosovellusten kanssa.
Flown IP voidaan helposti integroida mihin tahansa suorittimen suunnitteluarkkitehtuuriin, käskysarjaan tai prosessigeometriaan. Mitä enemmän PPU-ytimiä integroitu prosessorisirulle, , sitä suurempi suorituskyvyn lisäys myöhemmin saavutetaan. PPU-yksiköt voidaan optimoida CPU-markkinoiden eri tasoille ja käyttötapauksille – mobiililaitteisiin, PC-tietokoneisiin ja supertietokoneisiin.
PPU-arkkktehtuuri ei parannan vain laitteen isäntäprosessorin suorituskykyä, vaan Flow’n tekniikka täydentää myös laitteen emolevyä ja oheiskortteja.
Tomi Engdahl says:
David Johnson-Davies Builds a Lisp Compiler for the RP2350′s RISC-V Cores — in Lisp, Naturally
From seconds to milliseconds, this Lisp-based Lisp compiler shows just how efficient uLisp can be.
https://www.hackster.io/news/david-johnson-davies-builds-a-lisp-compiler-for-the-rp2350-s-risc-v-cores-in-lisp-naturally-11f8f2062087
Tomi Engdahl says:
Miksi RISC-V, Flow Computing?
https://etn.fi/index.php/13-news/16729-miksi-risc-v-flow-computing
Suomalainen Flow Computing ilmoitti eilen, että se on liittynyt RISC-V Internationaliin ja yhtiön PPU-arkkitehtuuria tullaan ensimmäiseksi käyttämään nimenomaan RISC-V-pohjaisissa suunnitteluissa. Mutta miksi ensiksi avoimeen RISC-V-leiriin?
Toimitusjohtajan ja toisen perustajan Timo Valtosen mukaan siksi, koska RISC-V on avoin käskykanta, mikä nopeuttaa kehitystä. RISC-V tarjoaa myös valmiita kirjastoja sekä muita komponentteja. Teknologialle on kiinnostusta markkinoilla ja käynnissä on jo positiivisia keskusteluja eri RISC-V CPU valmistajien kanssa.
Flow´n PPU-tekniikka lupaa merkittäviä, jopa satakertaisia parannuksia prosessorien suorituskykyyn laitearkkitehtuurista riippumatta. Tämän ansiosta voisi RISC-V-prosessori olla heti nopeampi kuin tehokkain x86-prosessori. Onko näin?
- Tätä pitää kysyä Inteliltä ja AMD:ltä, Valtonen nauraa. RISC-V PPU ei poissulje x86 PPUta ja meillä on valmius aloittaa yhteistyö heidän kanssaan x86-version kehittämiseksi, hän lisää.
Tomi Engdahl says:
SiFive Opens Orders for the High-Performance RISC-V HiFive Premier P550 “Early Access Edition”
Finalized hardware comes with an Imagination GPU and faster neural coprocessor — but software support is lagging behind.
https://www.hackster.io/news/sifive-opens-orders-for-the-high-performance-risc-v-hifive-premier-p550-early-access-edition-f548f59562ba?fbclid=IwY2xjawGEwjlleHRuA2FlbQIxMQABHR00I0Zefc4XERQlj5xZD-CxWSV8JlLxapo_BucifCd4zGhzSzxldUFn9w_aem_FlR_mfLSZBj9k4y7CeGIYg
SiFive has opened orders for its high-performance quad-core HiFive Premier P550 RISC-V board, though in limited quantities — as it looks to let a select few get hands-on with the hardware ahead of software finalization and a December full launch.
Tomi Engdahl says:
Microchip Unveils the High-Performance Eight-Core RISC-V PIC64HX Processor Family
Eight 1GHz 64-bit RISC-V cores, support for up to 64GB of DDR4 memory, and vector extensions for edge-AI: the PIC64HX is a beast.
https://www.hackster.io/news/microchip-unveils-the-high-performance-eight-core-risc-v-pic64hx-processor-family-91346e3e3039?fbclid=IwY2xjawGEw6BleHRuA2FlbQIxMQABHf9oNN5xV88GQvIWCL1y511JPPHV0DuVsOHe8IYI2GEUKjS4tJWNJTkL8w_aem_BHBa_0FZ8Il5J7UBur5ciw
Tomi Engdahl says:
RVA23 Profile ratification bolsters RISC-V software ecosystem
https://www.edn.com/rva23-profile-ratification-bolsters-risc-v-software-ecosystem/
RVA23 Profile, a major release for the RISC-V software ecosystem, has been ratified, and it’s expected to help accelerate widespread implementation among toolchains and operating systems. Before ratification, it underwent a lengthy development, review, and approval process across numerous working groups. RVA23 Profile has now received the final ratification vote by the RISC-V Board of Directors.
RISC-V has more than 80 technical working groups that collectively advance the RISC-V ISA capabilities. They aim is to address the need for portability across vendors with standard ISA Profiles for applications and systems software.
Tomi Engdahl says:
Microchipin uusimmat RISC-V-mikroprosessorit tukevat kvanttiluokan salausta
https://etn.fi/index.php/13-news/16754-microchipin-uusimmat-risc-v-mikroprosessorit-tukevat-kvanttiluokan-salausta
Kvanttitietokoneiden odotettu saapuminen aiheuttaa merkittävän uhan, sillä ne saavat nykyiset tietoturvamenetelmät tehottomiksi. Microchipin RISC-V-pohjainen PIC64HX on yksi markkinoiden ensimmäisistä mikroprosessoreista, joka tukee äskettäin standardoituja kvanttitason salausalgoritmeja.
Kyse on NIST-järjestön standardoimista FIPS 203- ja FIPS 204-algoritmeista. FIPS 203 (ML-KEM) on avainten vaihtoon tarkoitettu kryptografinen algoritmi, joka tarjoaa suojan kvanttitietokoneiden laskentatehoa vastaan. FIPS 204 (ML-DSA) puolestaan on digitaalinen allekirjoitusalgoritmi, joka varmistaa tiedon eheyden ja autentikoinnin kvanttiturvallisella tavalla.
PIC64HX on korkean suorituskyvyn moniytiminen 64-bittinen RISC-V -mikroprosessori, joka kykenee kehittyneeseen tekoälyn (AI) ja koneoppimisen (ML) prosessointiin. Se on varustettu aikakriittistä verkotusta tukevalla TSN Ethernet -yhteys sekä puolustusluokan tietoturvalla.
Prosessorille integroitu Ethernet-kytkin sisältää TSN-ominaisuuksia
Tomi Engdahl says:
Designed to be pin-compatible with the earlier ESP32-C6-Bug, this cheaper board design lacks radios but includes software USB and STEMMA QT.
Prokyber’s Ch32-Ant Is a Sub-$5 RISC-V Dev Board Built Around the WCH CH32V003 Microcontroller
Designed to be pin-compatible with the earlier ESP32-C6-Bug, this cheaper board design lacks radios but includes software USB and STEMMA QT.
https://www.hackster.io/news/prokyber-s-ch32-ant-is-a-sub-5-risc-v-dev-board-built-around-the-wch-ch32v003-microcontroller-5a0cdb3a6bfc?fbclid=IwY2xjawGIrYxleHRuA2FlbQIxMQABHWBEpCbDzGllL6twwgsPqdGWTjsQtJ1zcfmSX3tUQaTvFLakl-Ffo3Kw6w_aem_pLpP1H9qzrSSzeG8kzf16Q
Tomi Engdahl says:
https://etn.fi/index.php/13-news/16763-turvallisempaa-linux-koodia-risc-v-prosessorille
Tomi Engdahl says:
https://etn.fi/index.php/13-news/16811-avoimella-laehdekoodilla-voi-ohjata-robottiautoa
Tomi Engdahl says:
Saksalaisyritys lupaa RISC-V-prosessorin, joka korvaa kaikki muut suorittimet
https://etn.fi/index.php/13-news/16872-saksalaisyritys-lupaa-risc-v-prosessorin-joka-korvaa-kaikki-muut-suorittimet
Saksalaislähtöinen Ubitium on kehittänyt innovatiivisen prosessoriarkkitehtuurin, joka yhdistää eri suorittimien (CPU, GPU, DSP, FPGA) toiminnot yhteen siruun. Yrityksen mukaan tämä uusi RISC-V-arkkitehtuuriin perustuva ratkaisu mullistaa yli 50 vuotta vanhan suorittimien suunnittelun.
Ubitiumin universaaliprosessori eliminoi tarpeen erikoistuneille suorittimille. Sen avulla laitteet voivat käsitellä erilaisia laskentatehtäviä yhdellä mikroarkkitehtuurilla, mikä vähentää kehityskustannuksia ja piirien monimutkaisuutta. Ratkaisu mahdollistaa tekoälyominaisuudet ilman lisäkustannuksia ja lupaa nopeuttaa uusien tuotteiden tuomista markkinoille.
Prosessoriarkkitehtuuri perustuu Ubitiumin teknologiajohtajan, Martin Vorbachin, 15 vuoden kehitystyöhön. Vorbach, jolla on yli 200 puolijohdepatenttia, on luonut työkuormasta riippumattoman mikroarkkitehtuurin, joka mahdollistaa samojen transistorien uudelleenkäytön erilaisiin tehtäviin. Tämä tekee erikoistuneista suoritinytimistä tarpeettomia. Prosessori käyttää avoimen lähdekoodin RISC-V-arkkitehtuuria, mikä tuo joustavuutta ja skaalautuvuutta. Ratkaisun ansiosta kehittäjät voivat keskittyä ohjelmistojen kehittämiseen ilman monimutkaisia laiteintegraatioita.
Ubitiumin tavoitteena on luoda tuoteportfolio, joka kattaa sekä pienet sulautetut laitteet että suuritehoiset tietokonejärjestelmät. Kaikki perustuvat samaan mikroarkkitehtuuriin ja ohjelmointipinoon, mikä mahdollistaa ratkaisujen skaalautuvuuden ja sovellusten joustavan kehittämisen.
Tomi Engdahl says:
Halvalla radio Raspberry Pi -pikokorttiin
https://etn.fi/index.php/13-news/16883-halvalla-radio-raspberry-pi-pikokorttiin
Raspberry Pi -perhe sai uuden jäsenen, kun Raspberry Pi Pico 2 W julkaistiin tänään. Uutuus on varustettu integroiduilla langattomilla ominaisuuksilla, kuten 2,4 GHz Wi-Fi:llä (Wi-Fi 4) ja Bluetooth 5.2:lla. Tämä tekee siitä houkuttelevan vaihtoehdon erityisesti IoT-projekteihin ja langattomiin sovelluksiin.
Vain 7 dollarin hintalapullaan Pico 2 W tarjoaa runsaasti vastinetta rahoille. Kortti on suunniteltu samaan muottiin kuin edeltäjänsä, Raspberry Pi Pico, ja se tukee laajasti lisävarusteita ja kehitystyökaluja.
Suoritin on uusittu RP2350-siru, joka yhdistää Arm Cortex-M33- ja RISC-V Hazard3 -arkkitehtuurit. Rortilla on 520 KB SRAM-muistia ja 4 MB flash-muistia. Radiomoduuli on Infineonin CYW43439 -moduuli, joka mahdollistaa Wi-Fi 4:n ja Bluetooth 5.2:n.
Kortilla on 26 GPIO-nastaa ja se tukee esimerkiksi UART-, SPI-, I2C-, PWM- ja ADC-yhteyksiä.
Raspberry Pi Pico 2 W on sale now at $7
https://www.raspberrypi.com/news/raspberry-pi-pico-2-w-on-sale-now/
Tomi Engdahl says:
(485) $8 MilkV Duo: Arduino on one core and Linux on the other
https://www.youtube.com/watch?v=SeExddxWdNs&t=228s
Imagine a chip that runs Arduino on one core, Linux on the other, and is built on RISC-V architecture – all for around ten dollars. Sounds like science fiction? Well, it’s not. This might just be the next big leap after Arduino, Espressif, and Raspberry Pi.
00:00 – Intro
00:39 – Where did we come from?
01:14 – What happened in the last months?
02:04 – What does the MilkV Duo offer?
03:48 – How can we run Linux and Arduino in parallel?
04:42 – Program it with the Arduino IDE
06:12 – What about Linux?
07:51 – Let’s test capabilities of the Arduino core
10:10 – The grand finale
12:40 – Summing up
Tomi Engdahl says:
https://www.sensorsiot.org/
Tomi Engdahl says:
Sonata v1.0 RISC-V platform combines AMD Artix-7 FPGA and Raspberry Pi RP2040 MCU, features CHERIoT technology for secure embedded systems
https://www.cnx-software.com/2024/12/26/sonata-v1-0-risc-v-platform-combines-amd-artix-7-fpga-and-raspberry-pi-rp2040-mcu-features-cheriot-technology-for-secure-embedded-systems/
Tomi Engdahl says:
Writing A RISC-V OS From Scratch
https://hackaday.com/2025/01/09/writing-a-risc-v-os-from-scratch/
If you read Japanese, you might have seen the book “Design and Implementation of Microkernels” by [Seiya Nuda]. An appendix covers how to write your own operating system for RISC-V in about 1,000 lines of code. Don’t speak Japanese? An English version is available free on the Web and on GitHub.
The author points out that the original Linux kernel wasn’t much bigger (about 8,500 lines). The OS allows for paging, multitasking, a file system, and exception handling. It doesn’t implement interrupt handling, timers, inter-process communication, or handling of multiple processors. But that leaves you with something to do!
Tomi Engdahl says:
https://hackaday.com/2025/01/10/risc-v-microcontroller-lights-up-synth-with-led-level-meter/
Tomi Engdahl says:
RISC-V AI Chips Will Be Everywhere
Esperanto Techology’s chip heralds new era in open-source architecture; Intel set to cash in
https://spectrum.ieee.org/risc-v-ai
Tomi Engdahl says:
SiFive expands from RISC-V cores for AI chips to designing its own full-fat accelerator
Seems someone’s looking for an Arm wrestle
https://www.theregister.com/2024/09/19/sifive_ai_accelerator/
SiFive, having designed RISC-V CPU cores for various AI chips, is now offering to license the blueprints for its own homegrown full-blown machine-learning accelerator.
Announced this week, SiFive’s Intelligence XM series clusters promise a scalable building block for developing AI chips large and small. The idea is that others can license the RISC-V-based designs to integrate into processors and system-on-chips – to be placed in products from edge and IoT gear to datacenter servers – and hopefully foster more competition between architectures.
Fabless SiFive is no stranger to the AI arena. As we’ve previously reported, at least some of Google’s tensor processing units are already using SiFive’s X280 RISC-V CPU cores to manage the machine-learning accelerators and keep their matrix multiplication units (MXUs) fed with work and data.
And in a canned statement, SiFive CEO Patrick Little claimed the US-based outfit is now supplying RISC-V-based chip designs to five of the “Magnificent 7″ companies – Microsoft, Apple, Nvidia, Alphabet, Amazon, Meta and Tesla – though we suspect not all that silicon necessarily involves AI.
What sets SiFive’s Intelligence XM-series apart from previous engagements with the likes of Google or Tenstorrent is that rather than having its CPU cores attached to a third-party matrix math engine, all packaged up in the same chip, SiFive is instead bringing out its own complete AI accelerator design for customers to license and put into silicon. This isn’t aimed at semiconductor players capable of crafting their own accelerators, such as Google and Tenstorrent – it’s aimed at organizations that want to take an off-the-shelf design, customize it, and send it to the fab.
“For some customers, it’s still going to be right for them to do their own hardware,” Ronco said. “But, for some customers, they wanted more of a one-stop shop from SiFive.”
A closer look at the XM Cluster
SiFive’s base XM cluster is built around four of SiFive’s Intelligence X RISC-V CPU cores which are connected to an in-house matrix math engine specifically for powering through neural network calculations in hardware. If you’re not familiar, we’ve previously explored SiFive’s X280 and newer X390 X-series core designs, the latter of which can be configured with a pair of 1,024 vector arithmetic logic units.
Tomi Engdahl says:
Top 6 RISC-V Chips with Multi-core Design and AI Accelerator for AI and ML
https://www.dfrobot.com/blog-13462.html?srsltid=AfmBOooiENP9biefFSn04STpxplwpBsbx8DwclBUKCvYycZuz3t9hySY
I’m having trouble understanding what RISC-V GPUs and AI accelerators there are for sale out there
https://www.reddit.com/r/RISCV/comments/1c9ytuv/im_having_trouble_understanding_what_riscv_gpus/
Tomi Engdahl says:
RISC-V Enables Performant and Flexible AI and ML Compute
RISC-V: introducing new paradigms to the world of hardware design with software-focused hardware.
https://www.wevolver.com/article/risc-v-enables-performant-and-flexible-ai-ml-compute
The emergence of Artificial Intelligence (AI) and Machine Learning (ML) is one of the most significant computing trends in recent history. According to research, by 2027, spending on AI software alone will grow to nearly $300B, with a CAGR of 19.1% [1]. And, as the software half of the AI/ML world is growing at meteoric rates, the hardware side is also teeming with innovation. Similar research suggests that the AI accelerator market will increase from $21B in 2024 to $33B by 2028 [2].
AI/ML is a software-driven pursuit and can have very different requirements depending on the market and application (i.e., automotive, IoT, cloud, training vs inference, etc). Supporting this fast moving and diverse software market requires a collaborative,industry-wide effort to develop flexible and customized domain-specific hardware solutions optimized for this range of AI workloads. Innovation means that the market should not be limited to a few key players. Rather, the process needs to be democratized to enable everyone, enterprises and startups, to contribute their ideas to the growing AI/ML computing landscape.
RISC-V has become a preferred standard for designing the industry’s most performant and efficient AI/ML computing resources. Let’s take a look at what’s happening in the world of RISC-V for AI/ML and discover why RISC-V is a key technology for supporting the industry’s future.
Why RISC-V for AI/ML?
RISC-V is a compelling architecture for the development of AI/ML systems.The extensible industry standard RISC-V ISA enables a software-focused approach to AI hardware, freeing developers from the restrictions of proprietary compute. RISC-V provides a common language for AI development, as an industry standard ISA, creating a cohesive ecosystem for AI/ML development. This robust and highly capable ecosystem of member companies, organizations, technologists, enthusiasts and academics, brings the expertise and technologies that can deliver future generations of innovative new AI systems.
The configurability and openness of RISC-V enables a “software-focused” design paradigm, wherein hardware customization for specific workloads becomes feasible without the constraints imposed by proprietary instruction sets. This is achieved through RISC-V’s modular architecture, which allows developers to define custom extensions and instructions tailored to their unique workloads. For example, in AI/ML applications, developers can implement specialized instructions for matrix multiplications and vector processing—key operations in neural network computations.
Using custom instructions, such as Single Instruction, Multiple Data (SIMD) operations, RISC-V processors can execute multiple data points with a single instruction, significantly boosting performance in parallel processing tasks common in AI/ML workloads. Additionally, hardware accelerators tailored to AI tasks can be integrated seamlessly. These accelerators, including tensor processing units (TPUs) or specialized neural processing units (NPUs), are designed to handle the intensive mathematical operations required for deep learning models, such as convolutions and backpropagation.
Creating a Common Language
The RISC-V instruction set architecture (ISA) provides a uniform language for hardware and software developers, creating a cohesive ecosystem for AI/ML development. It allows developers to create tailored domain specific solutions with greater flexibility. Importantly, the controlled way in which this is enabled ensures that the base foundational software elements, such as those running on Linux, remain consistent and interoperable across different RISC-V implementations.
There’s no doubt that this RISC-V ecosystem has taken a foothold in the industry at large. In fact, so far, we estimate that more than 10 billion RISC-V processor cores have shipped [3]. Now, we’re seeing similar adoption in the AI/ML hardware markets, where reports are indicating that RISC-V-based AI SoCs will have a CAGR for units of 73.6% by 2027, while AI SoC unit shipments are projected to reach 25B by then. [4]. RISC-V is quickly becoming the defacto standard for building AI accelerators.
Here are some of the highlights of RISC-V’s use in AI/ML.
Meta’s MTIA v1 AI Inference Accelerator [5]
Esperanto ET-SoC-1 [6]
Google’s TPU [7]
SiFive Intelligence X390 [8]
StreamComputing STPC920 [10]
Ventana Veyron V2 [11]
Andes Technology QiLai SoC [12]
Semidynamics ‘All-In-One AI’ IP [13]
Axelera AI Metis AI Platform [14]
Project Open Se Cura [15]
Codeplay oneAPI Construction Kit [16]
Tomi Engdahl says:
https://www.reddit.com/r/RISCV/comments/1h7fsms/ai_models_on_risc_v/
Tomi Engdahl says:
RISC-V is making moves, but it has work to do if it wants to hit the mainstream
Can it topple x86 and Arm, or is the gap too wide to close?
https://www.theregister.com/2025/01/02/riscv_journey_to_mainstream/
RISC-V has been talked up as a challenger to Arm and x86, offering an open royalty-free architecture that promises flexibility and innovation without licensing costs. But for all the noise, you’re more likely to find it buried inside IoT gadgets and obscure embedded systems than powering anything that’ll typically grab a headline.
Arm runs the mobile and embedded world, and x86 still has desktop, laptop, and server markets locked down, but RISC-V? Well, it’s still waiting to punch above its weight, but it’s gaining traction as a CPU architecture. Whether or not it will make its way into the broader marketplace and power a wider range of devices is the big question.
Nvidia has quietly folded RISC-V cores into its GPUs and SoCs, and the GPU-maker expects to ship a billion RISC-V cores across its GPUs, SoCs, and other products by the end of 2024. The most notable of Nvidia’s implementations of RISC-V is the GPU System Processor, or GSP, which essentially offloads kernel driver functions and takes care of GPU utilization within the cores.
Even Qualcomm is using RISC-V in some of its devices, using RV cores in microcontroller units built within its Snapdragon processors. Qualcomm has shipped devices with around 650 million RISC-V cores to date, so the project’s architecture and cores are to be found in everyday devices – but why isn’t RISC-V the headliner?
Google pulls back
Qualcomm and Nvidia aren’t the only companies that are finding use for RISC-V and the architecture. Google had been making moves in this space – it officially supported RISC-V in the Android-specific, Linux-derived Android Common Kernel (ACK) up until May 2024 when it removed support from the ACK – a significant setback for the architecture.
Despite this, Google said it remains committed to RISC-V, and plans to enhance support in the future. It told Android Authority at the time: “Android will continue to support RISC-V. Due to the rapid rate of iteration, we are not ready to provide a single supported image for all vendors. This particular series of patches removes RISC-V support from the Android Generic Kernel Image (GKI).”
Prior to the move, the hope was that manufacturers might look at building Android devices using SoCs based on the RISC-V ISA. Removing RISC-V support from the ACK doesn’t mean no Android on RISC-V kit, but rather that any maker planning to go down this road would have to do a significant amount of coding work themselves.
The China factor
Given all of the geopolitical issues surrounding China and its push for self-contained and homegrown technology, Beijing has significantly invested in the RISC-V architecture as part of its strategic solution to stave off any reliance on foreign architecture and technologies.
Companies such as Loongson, which is a Chinese chip designer, have made use of the ISA to create RISC-V-powered systems that are used within Chinese schools. Another key example is Chinese giant Alibaba, which plans to use RISC-V within its cloud servers.
You gotta have standards
It was certainly a big moment for RISC-V in October this year when the RVA23 profile was ratified. This essentially lays out a consistent set of ISA extensions that software developers can rely on and utilize to create compatible software on RISC-V architecture. Not only does it bring features such as vector operations, floating-point, and atomic instructions, but it gives RISC-V some very much needed support for AI and machine learning workloads.
Overall the ratification of the RVA23 profile brings much needed consistency to an architecture that is looking to make a name for itself, but hasn’t been able to get there.
Tomi Engdahl says:
https://hackaday.com/2025/01/03/high-performance-risc-v/