Here are my collection of trends and predictions for electronics industry for 2015:
The computer market, once the IC growth driver per se, apparently is approaching saturation status. Communications industry is still growing (6.8%.). Automotive V2X, LED lighting and smart domestic objects are set to drive semiconductor market growth through the year 2020, according to market analysis firm Gartner.
Car electronics will be hot in 2015. New cars will have more security features, smart infotainment and connectivity in them. It is an are where smart phone companies are pushing to. Automotive Industry Drives Chip Demand article says that until 2018, the IC demand from automotive customers is expected to exhibit the strongest average annual growth — 10.8% on average. This is significantly higher than the communications industry, at second place with 6.8%. Demand drivers include safety features that increasingly are becoming mandatory, such as backup cameras or eCall. But driver-assistance systems are also becoming ubiquitous. Future drivers will include connectivity, such as vehicle-to-vehicle communications, as well as sensors and controllers necessary for various degrees of autonomous driving.
Power electronics is a $90 billion-per-year market. The market for discrete power electronics is predicted to grow to $23 billion by 2024 from $13 billion today. Silicon rules power electronics industry, but new materials are pushing to headlines quickly. In the power electronics community, compound semiconductors such as gallium nitride (GaN) are drawing more attention as they try to displace silicon based power devices, which have been doing the heavy lifting for the past 30 years or so. While silicon-based devices are predicted to remain predominant with an 87% share of the market, it is expected that SiC- and GaN-based components to grow at annual rates of 30% and 32%, respectively. There’s no denying the cost advantages that silicon possesses.
Chip designs that enable everything from a 6 Gbit/s smartphone interface to the world’s smallest SRAM cell will be described at the International Solid State Circuits Conference (ISSCC) in February 2015. Intel will describe a Xeon processor packing 5.56 billion transistors, and AMD will disclose an integrated processor sporting a new x86 core, according to a just-released preview of the event. The annual ISSCC covers the waterfront of chip designs that enable faster speeds, longer battery life, more performance, more memory, and interesting new capabilities. There will be many presentations on first designs made in 16 and 14 nm FinFET processes at IBM, Samsung, and TSMC.
There is push to go to even smaller processes, and it seems that next generation of lithography equipment are started to being used. Earlier expectation was for chipmakers to use traditional immersion lithography for production of 10 nm chip, but it seems that extreme ultraviolet (EUV) scanners that allows allow scaling to 10 nm or even smaller is being used. TSMC to Use EUV for 7nm, Says ASML. Intel and TSMC have been injecting money in ASML to push process technology.
2015 promises to see initial FPGA product releases and (no doubt) a deluge of marketing claims and counter-claims. One thing is certain: 2015 will not be boring. There will be FPGA products that use processes beyond 20nm, for example Altera and Xilinx have committed to use the TSMC 16nm FinFET technology. There is publicized (and rumored) race to get to production at 14nm has seen time frames for initial samples move into 2015. However, with both FPGA companies reporting gross margins of close to 70 percent, it would be possible for either company to take an initial hit on margin to gain key socket wins.
It seems that the hardware becomes hot again as Wearables make hardware the new software. Apple invest its time when it released the Apple Watch last quarter, going up against the likes of Google’s Android Wear and others in the burgeoning wearables area of design. Once Apple’s bitten into a market, it’s somewhat a given that there’s good growth ahead and that the market is, indeed, stable enough. As we turn to 2015 and beyond wearables becomes an explosive hardware design opportunity — one that is closely tied to both consumer and healthcare markets. It could pick up steam in the way software did during the smartphone app explosion.
There will be more start-up activity within hardware sector. For recent years, the software has been on the main focus on the start-ups, and the hardware sector activity has been lower. Hardware sector has seem some start-up activity with many easy to use open hardware platforms became available (make development of complex devices easier and reachable for smaller companies). The group financing (Kickstarter, Indiegogo, etc.) have made it possible to test of new hardware ideas are market-worthy and get finance to get them to production.
EEs embrace hackathons aand accelerators. Design 2.0 is bubbling up in the engineering community, injecting new energy into the profession. In many ways, it’s the new Moore’s Law. Easy to use open hardware development platforms have made it possible to design working hardware device prototypes within hackathons.
Silicon Startups Get Incubator article tells that there will be new IC start-up activity as semiconductor veterans announced plans for an incubator dedicated to helping chip startups design their first prototypes. Keysight, Synopsys, and TSMC have signed exclusive deals to provide tools and services to the incubator. Silicon Catalyst aims to select its first batch of about 10 chip startups before April.
MEMS mics are taking over. Almost every mobile device has ditched its old-fashioned electret microphone invented way back in 1962 at Bell Labs. Expect new piezoelectric MEMS microphones, which promise unheard of signal-to-noise ratios (SNR) of up to 80 dB (versus 65 dB in the best current capacitive microphones) in 2015. MEMS microphones are growing like gangbusters.Also engineers have found a whole bunch of applications that can use MEMS microphone as a substitute for more specialized sensors starting in 2015.
There will be advancements in eco-design. There will be activity within Europe’s Ecodesign directive. The EC’s Ecodesign Working Plan for 2015-2017 is currently in its final study stages – the plan is expected to be completed by January 2015. The chargers will be designed for lower zero load power consumption in 2015, as on February 2016, after the 5-watt chargers are no longer at no load connected consume more than 0.1 watts of power. Socket for power supplies values are defined in the new Energy Star standard VI.
LED light market growing in 2015. Strategies Unlimited estimates that in 2014 the LED lamps were sold $ 7 billion, or about 5.7 billion euros. In 2019 the LED lamps will already sold just over 12 billion euros. LED technology will replace other lighting technologies quickly. For those who do not go to the LED Strategies Unlimited permission difficult times – all other lamp technologies, the market will shrink 14 percent per year. The current lighting market growth is based on LED proliferation of all the different application areas.
IoT market is growing fast in 2015. Gartner is predicting a 30 percent compound annual growth rate for the IoT chip market for the period 2013 to 2020. The move to create billions of smart, autonomously communicating objects known as the Internet of Things (IoT) is driving the need for low-power sensors, processors and communications chips. Gartner expects chips for IoT market to grow 36% in 2015 (IoT IC marker value in 2014 was from $3.9 billion to $9 billion depending how you calculate it). The sales generated by the connectivity and sensor subsystems to enabled this IoT will amount $48.3 billion in 2014 and grow 19 percent in 2015 to $57.7 billion. IC Insights forecasts that web-connected things will account for 85 percent of 29.5 billion Internet connections worldwide by 2020.
With the increased use of IoT, the security is becoming more and more important to embedded systems and chip designers. Embedded systems face ongoing threats of penetration by persistent individuals and organizations armed with increasingly sophisticated tools. There is push for IC makers to add on-chip security features to serve as fundamental enablers for secure systems, but it is just one part of the IoT security puzzle. The trend toward enterprise-level security lifecycle management emerges as the most promising solution for hardened security in embedded systems underlying the explosive growth of interconnected applications. The trend continues in 2015 for inclusion of even more comprehensive hardware support for security: More and more MCUs and specialized processors now include on-chip hardware accelerators for crypto operations.
Electronics is getting smaller and smaller. Component manufacturers are continually developing new and smaller packages for components that are mere fractions of a millimeter and have board to component clearances of less than a mil. Components are placed extremely close together. No-lead solder is a relatively recent legislated fact of life that necessitated new solder, new fluxes, higher temperatures, and new solder processing equipment. Tin whisker problems also increased dramatically. You should Improve device reliability via PCB cleanliness, especially if you are designing something that should last more then few years.
Photonics will get to the circuit board levels. Progress in computer technology (and the continuation of Moore’s Law) is becoming increasingly dependent on faster data transfer between and within microchips. We keep hearing that copper has reached its speed limit, and that optics will replace copper for high-speed signals. Photonics now can run through cables, ICs, backplanes, and circuit boards. Silicon chips can now have some optical components in them using silicon photonics technologies. For more than 10 years, “silicon photonics” has attracted significant research efforts due to the potential benefits of optoelectronics integration. Using silicon as an optical medium and complementary metal-oxide semiconductor fabrication processing technology, silicon photonics allows tighter monolithic integration of many optical functions within a single device.
Enter electro-optical printed circuits, which combine copper and optical paths on the same board. Electro-optical PCBs use copper for distributing power and low-speed data, and optical paths for high-speed signals. Optical backplane connectors have been developed, as well as a technique to align the small waveguides to transceivers on the board. The next challenge is to develop waveguides on to boards where the tight bends don’t degrade performance to unacceptable levels.
3D printing will bring structural electronics. With 3D printing hot in the news, and conformable, flexible, or even printed electronics fitting any shape, it is only a matter of time before electronic circuits can be laid-out as part of the 3D-printing process, the electronic framework becoming an integral supporting part of any object’s mechanical structure. For example “structural batteries” have already been implemented in electric cars, in racing-car aerofoils, and in the Tesla pure electric car.
Superconductors are heating up again. Superconductivity will be talked again in 2015 as there were some advancements in the end of 2014. A group of international scientists working with the National Accelerator Laboratory in Menlo Park, Calif., have discovered lasers that can create conditions for superconductivity at temperatures as high at 140°F. The Massachusetts Institute of Technology (MIT) has discovered a law governing thin-film superconductors, eliminating much of the trial and error for companies that manufacture superconducting photodetector. With MIT’s new mathematical law, new superconducting chips can be designed with the correct parameters determined ahead of time.
Frost and Sullivan forecast that “PXI to disrupt automated test” between 2015 and 2018. They predict PXI to achieve $1.75B in annual sales by 2020, up from $563M in 2013. That’s an aggregate growth rate of over 17%. Not bad for an industry that has an overall secular growth rate of 3 percent.
1,206 Comments
Tomi Engdahl says:
LVDS display bridges and automated measurements, part 1
http://www.edn.com/design/test-and-measurement/4439646/LVDS-display-bridges-and-automated-measurements–part-1?_mc=NL_EDN_EDT_EDN_analog_20150611&cid=NL_EDN_EDT_EDN_analog_20150611&elq=1b2ff464f1cc4acfa06a0fc717a9df5c&elqCampaignId=23405&elqaid=26382&elqat=1&elqTrackId=59cd6ad213a54356908c0a802c873077
Today’s vehicles use TFT LCD displays for presenting the vehicle’s status, entertainment system, and other information to the driver. The displays are driven by an SoC that contains memory, an control unit, and a bridge that delivers a serial LVDS (Low Voltage Differential Signaling) data stream. LVDS lets us achieve high speed data transfer with high signal integrity and low power consumption.
Characterizing LVDS devices requires us to make measurements under a range of power-supply voltage, temperature, and process variations. An automated test system makes and records the measurements and analyzes the results.
Tomi Engdahl says:
Interleaving ADCs: Unraveling the mysteries
http://www.edn.com/design/analog/4439662/Interleaving-ADCs–Unraveling-the-mysteries-?_mc=NL_EDN_EDT_EDN_analog_20150611&cid=NL_EDN_EDT_EDN_analog_20150611&elq=1b2ff464f1cc4acfa06a0fc717a9df5c&elqCampaignId=23405&elqaid=26382&elqat=1&elqTrackId=59e048785a37487ea3e121f63aba313c
Tomi Engdahl says:
Low-power position sensing in harsh environments: A robust application example
http://www.edn.com/design/analog/4439651/Low-power-position-sensing-in-harsh-environments–A-robust-application-example?_mc=NL_EDN_EDT_EDN_analog_20150611&cid=NL_EDN_EDT_EDN_analog_20150611&elq=1b2ff464f1cc4acfa06a0fc717a9df5c&elqCampaignId=23405&elqaid=26382&elqat=1&elqTrackId=92b977990d2b4646a70370b61db80c51
For a variety of reasons, the requirement for low-power position sensing is growing in many product categories. With appliances and consumer goods, government regulations and environmental programs often are motivating factors in the drive for higher efficiency.
Low power consumption also is required in an entirely different category of products, for a different reason: in remotely installed instruments, or in subterranean or submarine sensors, low power is a purely financial and operational requirement. In many of these applications, low power consumption must be combined with extreme robustness: operating conditions might be harsh because of wide temperature ranges, high humidity, high pressure, or the presence of contaminants.
This article explores the latest options for position-sensing systems that combine low power consumption with tolerance of extreme conditions.
Tomi Engdahl says:
Documentation First! unifies design flow
http://www.edn.com/design/integrated-circuit-design/4439637/Documentation-First–unifies-design-flow?_mc=NL_EDN_EDT_EDN_analog_20150611&cid=NL_EDN_EDT_EDN_analog_20150611&elq=1b2ff464f1cc4acfa06a0fc717a9df5c&elqCampaignId=23405&elqaid=26382&elqat=1&elqTrackId=2af35c2558b04e79b4b1ef9e5fccd1b6
With aggressive time to market, cycle time reduction has been an unending goal. In this race of cycle time reduction, documentation often takes a back seat. Early and correct documentation is necessary for internal teams like verification and application, and for the end customer to meet SoC deadlines.
In conventional flow, documentation was updated when the designer found time; usually late in the cycle. This practice had lead to delays and iterations in stabilizing the SoC verification process. Hence, the pre-Si validation and the application team were also enabled late in cycle. The only way to move forward was to ensure that duplication was avoided and cycle time was gained. This lead to development of a flow where the designer felt incentivized to follow what we call Documentation First!
Documentation First! is not only a mindset to do documentation before design, but a whole tool-based methodology.
The two basic deliverables for a product is the chip and its reference manual. The key aspect of making a product successful is keeping both of them in sync. This can only be achieved if we have a single sourcing in the system. Both the reference manual and design needs to come from a single source. A unified flow [Fig 1.] is presented here to cater to the needs of Documentation First! and single sourcing.
Results and Conclusion
A typical use case with 40 registers in a memory map each 32 bit wide would roughly take 2 weeks of design and verification effort going by the manual process. This effort is reduced by ~90% [Fig. 7] with the automated flow as well as making it debug and error free. All outputs are generated by a push button and deliverables are checked by the internal release checker. For any change in register memory map only incremental change in the register documentation will generate updated RTL and updated verification environment.
Thus, the Unified Flow described herein resolves critical issues which eventually results in the zero customer errata due to design and documentation mismatch. It also reduces the cycle time for RTL bring up significantly.
Tomi Engdahl says:
Vacuum improves 3-d vapor-phase soldering process
http://www.edn.com/design/pc-board/4439630/Vacuum-improves-3-d-vapor-phase-soldering-process?_mc=NL_EDN_EDT_EDN_weekly_20150611&cid=NL_EDN_EDT_EDN_weekly_20150611&elq=4bde813709ed49a2845b39955b280054&elqCampaignId=23416&elqaid=26402&elqat=1&elqTrackId=fab38be218134634a7f791abb9094097
A vacuum can be used to achieve real advantages in the soldering process. We needed to take a closer look at the soldering process with vacuum profiles, so an evaluation project was performed. As a result of the uniform distribution of the vapor during the pre-vacuum phase, it was possible to significantly improve the 3-dimensional soldering process for a MID (molded interconnect device) application.
MID technology is used in particular where significant miniaturization, freedom of design with regard to geometry, and a reduced number of components for the electronics assembly is required. The electrical and mechanical features which are normally distributed to various components during conceptualization and development are combined into a single MID part.
When vacuum is used, the Galden Vapor is distributed uniformly throughout the process chamber instead of forming an ascending vapor front during preheating and soldering. In this way, the disadvantages of the temperature gradient associated with conventional vapor phase systems (the closer to the source of heat the sooner heat up takes place) and with convection systems (the closer to the source of heat the sooner heat up takes place and the hotter it gets) are avoided.
By using vapor phase soldering in combination with in-situ vacuum, geometry-related deviations in the temperature profiles can be eliminated in addition to reducing void content and void count.
What are molded interconnect devices?
http://www.edn.com/design/pc-board/4427506/What-are-molded-interconnect-devices-
Molded interconnect devices (MIDs) are 3-dimensional electromechanical parts that bring together the best of both mechanical and electrical engineering. MIDs combine the circuit board, housing, connectors, and cables that comprise traditional product interfaces and merge them into one fully functional, compact part.
The appeal of a device such as the MID is easily recognized. By reducing the amount of parts that go into a product, space is saved, fewer components are necessary, and the weight of the unit is reduced. In addition, the possibility of a 3D workspace lets engineers think outside of the square geometries that have previously limited circuit board design.
Originally developed in the 1980s, MIDs came on strong as a hot, new concept. Despite the early fanfare, however, MIDs didn’t catch on at first. High tooling costs and high volume manufacturing thresholds limited the market for MIDs.
All that has begun to change since the turn of the century, as MIDs have seen a comeback.
The classic Motorola “brick” cell phone as made famous by Oliver Stone’s Wall Street may not have had much use for miniature parts, but the smart phone in your pocket that doubles as your computer, personal assistant, GPS, and gaming device sure does.
As functionality of electronics has increased, we’ve demanded that their size does the opposite. In short, technology has evolved but the size of our hands hasn’t. For this reason, we’ve reached a point in time where, more than ever, electrical and mechanical product designers must be on the same page as far as making everything work in the limited space modern devices possess.
Fortunately for development teams, modern manufacturing methods make implementing MIDs a more pragmatic option than before.
The platable part, usually palladium doped plastic, forms the circuitry. The non-platable part, often polycarbonate, fulfills mechanical functions and completes the molding. The two parts are fused together and then undergo electroless plating. In this step the platable plastic is metallized, while the non-platable plastic remains non-conductive.
Due to the nature of having multiple parts, tooling for the two-shot molding process is often complex.
Another method for producing MIDs is laser direct structuring (LDS). A three-step process (patented by LPKF ), laser direct structuring builds on the benefits introduced by two-shot molding.
Tomi Engdahl says:
5G to disrupt the test equipment market
http://www.edn.com/electronics-blogs/test-cafe/4439597/5G-to-disrupt-the-test-equipment-market?_mc=NL_EDN_EDT_EDN_weekly_20150611&cid=NL_EDN_EDT_EDN_weekly_20150611&elq=4bde813709ed49a2845b39955b280054&elqCampaignId=23416&elqaid=26402&elqat=1&elqTrackId=6ea96544989b4bc58a4407330b6a011d
The coming 5G wave is set to not only disrupt the communications sector, but also the test equipment that serves it. While some traditional instrument product categories may be utilized in the development of 5G, the real heavy lifting will be performed by instrumentation not yet invented. The combinations of frequency, spectrum width, data rates, and multi-antenna architectures are simply not present in today’s instruments. But one thing is clear: modular instruments will play a primary enabling role for 5G. To explain why, let me first explain what 5G is all about.
Tomi Engdahl says:
The technology behind measuring distance and speed
http://www.edn.com/electronics-blogs/rowe-s-and-columns/4439632/The-technology-behind-measuring-distance-and-speed?_mc=NL_EDN_EDT_EDN_today_20150611&cid=NL_EDN_EDT_EDN_today_20150611&elq=2267ca3beabf46a2a58ba5b2164d8d66&elqCampaignId=23409&elqaid=26395&elqat=1&elqTrackId=053d7f1ef2c24313b8587511a4fea54d
Many measurements start with sensors, be they temperature, strain, light, position, or other physical properties. Accurately measuring the distance to and speed of an object has challenges relating to ambient light, color, surface properties, and other nearby objects.
Poulin identified some applications for the processor:
Automotive: Parking assistance, collision avoidance, detecting objects or people in the driver’s blind spot.
Navigation: Autonomous vehicles, mining, construction, cranes.
Home: Appliances, faucets, toilets, towel dispensers.
Security: Occupancy and detection of intruders.
Vehicle traffic: Counting number of vehicles and speed.
Smart lighting: Adjust lighting based on activity. For example, turning down lights in an empty parking lot.
Drones: Detect altitude and speed.
Tomi Engdahl says:
3D Power Packaging with Focus on Embedded Substrate Technologies
http://www.edn.com/design/power-management/4439641/3D-Power-Packaging-with-Focus-on-Embedded-Substrate-Technologies?_mc=NL_EDN_EDT_EDN_today_20150611&cid=NL_EDN_EDT_EDN_today_20150611&&elq=2267ca3beabf46a2a58ba5b2164d8d66&elqCampaignId=23409&elqaid=26395&elqat=1&elqTrackId=3e1d99eb665e4d7ebf0d21ad154f97f6
The power electronics industry and the semiconductor industry, inseparably intertwined with one another, are facing unprecedented efficiency, cost, construction and thermal challenges which provide many opportunities for innovation. These industries are in the focal point of the “energy challenge” a multifaceted problem that involves mobile and cloud infrastructure systems, Internet-of-Things, renewable energy, smart grid, vehicle electrification, and across-the-board power efficiency enhancements in order to keep up with the IT industry’s rapid growth in data consumption. These are the competitiveness and sustainability challenges of the twenty-first century.
The paradigm shift we have been experiencing in semiconductor packaging technology was brought about by advanced deep submicron semiconductor technology reaching a “cost barrier” that prevented further cost reduction by reducing transistor size and adding more functions to the semiconductor die. This barrier was circumvented through the development of wafer thinning that enabled through-silicon-via (TSV) technology, and the eventual introduction of 2.5D and 3D integration that facilitated heterogeneous (“More than Moore”) integration. It will allow the power requirements of the digital load to increase 2 to 5 times, within the same footprint, in a single generation. The power sources community must now find ways to package power sources that will meet this demand, but with no increase in footprint.
In parallel power semiconductor technology is facing a “construction barrier” that prevents realization of the huge benefits new technology can offer in terms of increased power efficiency and higher power density. These new technologies include gallium-nitride (GaN), silicon-carbide (SiC), and gallium-arsenic (GaAs) power semiconductor devices that require operation in an environment that is free of bond wires and minimizes parasitic interconnect elements. The leading packaging technology to achieve a significant reduction in parasitics (L, R, and C) is embedding active and passive components in printed circuit boards (PCBs) and using packaging technologies developed for 2.5D and 3D integration by the semiconductor industry, outsourced semiconductor assembly and test (OSAT) services, and original equipment manufacturers (OEMs). Thus existing 2.5D and 3D integration and component embedding becomes a key enabling technology for high density power sources utilizing these new power semiconductor devices.
Tomi Engdahl says:
Atmel on the Block
http://www.eetimes.com/document.asp?doc_id=1326820&
Atmel Corp. is on the block, looking for a potential buyer, Reuters reported Monday. If true, the move feeds further fuel into the M&A frenzy currently affecting the global semiconductor market.
Atmel, a mid-sized chip vendor with revenue last year of $1.41 billion, is known for its MCU and touch-sensing technology. Atmel’s latest pitch to the investment community is that its strategy — banking on the emerging Internet of Things market – has transformed it into a higher-margin, higher-growth business.
During the company’s earnings call last month, Steven Laub, president and CEO, announced his plan to retire at the end of August. He told financial analysts, “Today, the company is comprised of very desirable businesses: microcontrollers, wireless, touch, security and automotive, all of which are positioned to grow in attractive high growth markets.”
Exclusive: Chipmaker Atmel exploring sale – sources
http://www.reuters.com/article/2015/06/08/us-atmel-sale-exclusive-idUSKBN0OO2BD20150608
Atmel Corp (ATML.O), a maker of small processors called microcontrollers that are used in a variety of electronics, is exploring strategic alternatives, including a possible sale, three people familiar with the matter said on Monday.
Mid-sized semiconductor makers are becoming attractive takeover targets for larger semiconductor players looking to round out their capabilities with chips for cars, watches and other devices that will interact with each other in what is referred to as the “Internet of Things”.
Tomi Engdahl says:
Comparing Position Sensors for Hydraulic Cylinder Feedback
http://www.eetimes.com/author.asp?section_id=36&doc_id=1326845&
Magnetostrictive, variable resistance, and variable inductance sensors are the most popular position feedback sensors for hydraulic or pneumatic cylinders. How do they compare?
Position feedback sensors for hydraulic or pneumatic cylinders have used one of three traditional technologies: Magnetostrictive, variable resistance, and variable inductance sensors. While other sensor technologies have occasionally been used successfully in this application, these three sensor types are the most popularly used technologies.
Tomi Engdahl says:
The True Cost of DIY Manufacturing
http://www.eetimes.com/author.asp?section_id=36&doc_id=1326818&
Before you decide to set up your own manufacturing capability, review its true costs.
Manufacturers of niche electronics-based products sometimes toy with the idea of bringing their manufacturing in-house. Although vertical integration, generally speaking, has gone the way of the do-do bird, cash-strapped start-ups and product mangers with low-volume product lines may sometimes feel that there aren’t manufacturers out there who will be a good fit for them. But the true costs of manufacturing are often overlooked in discussions about bringing this capability in-house.
The often-overlooked costs of setting up an internal manufacturing capability include:
Real-estate & utilities
Costs of acquisition and maintenance
Software licenses
Costs to run the equipment
Perhaps the most significant cost of bringing manufacturing in-house, however, is a loss of focus. I strongly believe that OEMs should focus on the marketing and sale of their products: staying close to customers, understanding what the market needs, and working to innovate, sell, and support products to fit those needs.
Manufacturing is an entirely unique business from the marketing and sales of products.
Tomi Engdahl says:
Bosch’s MEMS business celebrated its 10th anniversary
German Bosch Sensortech is currently by far the largest manufacturer of MEMS sensors. Its turnover last year exceeded $ 1.2 billion. This week, the Bosch MEMS business celebrated its 10th anniversary.
Source: http://etn.fi/index.php?option=com_content&view=article&id=2964:boschin-mems-bisnes-taytti-10-vuotta&catid=13&Itemid=101
Tomi Engdahl says:
Intel vs. ARM—Will the Bear Strike Back?
http://intelligentsystemssource.com/intel-vs-arm-will-the-bear-strike-back/?utm_source=Pubpress&utm_medium=email&utm_term=Intel+vs.+ARM%E2%80%94Will+the+Bear+Strike+Back%3F+&utm_content=ISS+Enewsletter+June%3A+Intel+vs.+ARM%E2%80%94Will+the+Bear+Strike+Back%3F&utm_campaign=1506_ISS_enewsletter
Intel must be feeling like a bear being circled by wolves. The wolves are named ARM and they are gradually tearing meaty chunks out of the x86 bear. But beware of getting a bear cornered. A cornered bear can lash out with some pretty mean claws as well. For some time there has been a battle going on in the embedded space between the Intel Atom family of x86 low-power processors and a variety of ARM architecture-based devices, which are increasingly centered on the ARM Cortex M and R series cores. Intel’s advantage has been that the embedded world has largely been derived from that of the PC—high-volume, low-cost devices as well as widely used peripheral technologies like USB and PCI and now PCI Express. ARM’s big selling point has been its low power consumption, which despite all its efforts, Intel has never been able to match. This difference is being increasingly exacerbated with the surge in mobile devices, wireless connectivity and the need to save power at every step. This and the flattening of the PC market has allowed ARM and its many licensees to make steady gains. Add to this mix, Intel’s old nemesis, AMD, which has successfully marketed lines of processors based on its clean room-developed version of the x86 instruction set. Now even AMD is starting to move into the ARM arena.
It appears that so far Intel’s strategy has been to more aggressively and specifically target the embedded arena with such things as Atom and Core-based SoCs that incorporate a range of on-chip peripherals and increasingly to move into the server arena with powerful versions of its multi-core Xeon processors. Unfortunately, the lust for power-savings is also now rampant in server farms, which consume enormous amounts of electricity and dissipate ungodly amounts of heat—all of which can be visualized as dollar signs by their managers. And now ARM is targeting the server arena with a new line of 64-bit ARM cores and AMD, among others, have started offering processors targeting the server market based on these new cores.
Another thing that Intel has to contend with is the emergence of heterogeneous system architectures (HSAs) that integrate such elements as graphic processors, DSPs and FPGAs on the same die
Both Altera and its major rival Xilinx currently offer families of CPU/FPGA hybrid processors on which the CPU is an ARM device.
No FPGA company will be able to license something like Atom or Core i5 IP from Intel to build a competing device. So if Intel does acquire Altera, you can expect it to, of course, continue to support and develop Altera’s technologies and serve its customers. There were predictions that after its acquisition of Wind River, it would drop lines that served other processors, but that did not happen. We can, however, expect to see a discontinuation of ARM-based SoC FPGAs for a line of hybrids based on Atom and Core architectures.
If Intel does acquire a major programmable logic house like Altera with its built-in expertise, it will be able to turn out hybrid processors with a huge range of specific (network server) functions as well as generally programmable and configurable devices.
Tomi Engdahl says:
Correlation: An overlooked oscilloscope measurement
http://www.edn.com/design/test-and-measurement/4439578/Correlation–an-overlooked-oscilloscope-measurement?_mc=NL_EDN_EDT_EDN_analog_20150604&cid=NL_EDN_EDT_EDN_analog_20150604&elq=724e75da920347fa8b00c8d6cc732b8e&elqCampaignId=23297&elqaid=26258&elqat=1&elqTrackId=a7247d874d6f4bc0b435fcb2ce5b99c2
The correlation function is a useful signal-analysis tool that engineers often overlook. Its formidable equation, which you have probably not thought about since your undergraduate signals and systems course,
You can forget the pain that this equation evoked in your earlier life because modern oscilloscopes and third-party math software easily perform all the computations and make this powerful function available to everyone. Correlation can be classified into either of two functions, auto-correlation or cross-correlation, depending on the number of inputs. In this article, we’ll show some common applications for both cross-correlation and auto-correlation.
Tomi Engdahl says:
2015 Mergers, acquisitions and change in the global electronics industry
http://www.edn.com/electronics-blogs/anablog/4439603/2015-Mergers–acquisitions-and-change-in-the-global-electronics-industry?_mc=NL_EDN_EDT_EDN_review_20150605&cid=NL_EDN_EDT_EDN_review_20150605&elq=c653476f91da48388e8b6d9f9f7296ff&elqCampaignId=23319&elqaid=26279&elqat=1&elqTrackId=9f8fe260d53247c5921d52b0dfaef203
Tomi Engdahl says:
Out-of-spec problem with a long tail
http://www.edn.com/electronics-blogs/tales-from-the-cube/4403805/Out-of-spec-problem-with-a-long-tail
Not long after this adjustment, the problem in the field essentially vanished. My office mate and I were hailed as heroes, the company was sold on computer-aided circuit analysis, and the experience taught me never again to put my complete trust in a data sheet.
Tomi Engdahl says:
Reference designs ease IO-Link implementation
http://www.edn.com/electronics-products/other/4439636/Reference-designs-ease-IO-Link-implementation?_mc=NL_EDN_EDT_EDN_productsandtools_20150615&cid=NL_EDN_EDT_EDN_productsandtools_20150615&elq=e285574a28c84e2691aa66d3095e6b8c&elqCampaignId=23448&elqaid=26454&elqat=1&elqTrackId=4e8164dc8fa148c280ade8b8cf6ddc9a
Tomi Engdahl says:
Nantero Exits Stealth: Using Carbon Nanotubes for Non-Volatile Memory with DRAM Performance & Unlimited Endurance
by Kristian Vättö on June 11, 2015 12:35 PM EST
http://www.anandtech.com/show/9314/nantero-exits-stealth-using-carbon-nanotubes-for-nonvolatile-memory-with-dram-performance-unlimited-endurance
The race for next generation non-volatile memory technology is already on at full throttle. We covered Crossbar’s ReRAM announcement last year and last week a very exciting company with a different non-volatile technology exited stealth mode and shed light on its technology and commercialization plans. The company is called Nantero and it’s been developing its NRAM technology for well over a decade now.
The Technology
It goes without saying that Nantero is packed with semiconductor experience and know-how, but its technology isn’t any less interesting. NRAM is made out of carbon nanotubes, which is the strongest material known to man and provides far better thermal and electrical conductivity than any other known material.
The way NRAM works is in fact relatively simple. Essentially there are two nanotubes, which have low resistance when in physical contact and high resistance when separated. The amount of resistance then determines whether the cell is considered to be programmed as ‘0’ or ‘1’. Program operation (or “SET” as Nantero calls it) works by applying a voltage on one of the nanotubes, which will then attract the other nanotube and create a bond. The SET operation is very fast and takes only picoseconds, which is on par with or better than DRAM latency. The bond is kept in tact by Van der Waal’s interactions and is practically immortal with data retention terms even in 300°C is over ten years. In an erase operation (or RESET as Nantero calls it) the voltage is simply applied in the other direction, which will “heat up” (given the scale it’s more like vibration) the nanotube contacts and cause them to separate. Given that carbon nanotubes are one of the strongest materials in the world, the write/erase endurance is practically infinite as independent university study has shown Nantero’s NRAM technology to have over 1011 P/E cycles (for your information, 1011 translates to 100 billion).
The other great news is that carbon nanotubes are extremely small. One nanotube can have a diameter of only 2nm and the pitch between the two nanotubes in off-state can be an even tinier 1nm, so the technology has potential to scale below 5nm. NRAM can also scale vertically, or go 3D, and since the cell structure and manufacturing process are both quite simple, 3D stacking should, in theory, be much easier compared to what 3D NAND is today with no need for high aspect ratio etching as an example.
The process of making an NRAM wafer starts by taking a normal CMOS wafer with the normal cell select and array line circuitry, which is then spin coated with carbon nanotubes.
Tomi Engdahl says:
HTC: Asus Can’t Buy Us
http://www.eetimes.com/document.asp?doc_id=1326874&
HTC issued a thanks, but no thanks type of response after an Asus executive floated the idea that it could purchase the smartphone manufacturer.
Beleaguered smartphone manufacturer HTC issued a strong statement Monday, rejecting an overture from an Asus executive who suggested the PC maker was interested in buying the company.
“Our chairman has chatted about the topic internally,” Chang said, according to the Reuters report.
Tomi Engdahl says:
Chip, PC Demand Continues Decline
Some PC chips down as much as 20% in Q2
http://www.eetimes.com/document.asp?doc_id=1326870&
Demand for semiconductors continued to weaken in the second quarter with some PC assemblers in Asia suggesting a decline in purchases of some parts of as much as 15-20% from the second quarter of 2014, according to a report from Wall Street analysts at Deutsche Bank.
“The iPhone supply chain and the automotive market continue to remain the only bright spots,” said analysts who visited nearly 30 companies in Taiwan, Korea and Japan in five days.
Chip demand also is weak for tablets, TVs and many Android phones, according to the report that gave the chip sector a neutral ranking overall.
“Only Huawei and Xiaomi remain bright spots among the Chinese [smartphone] players,” the report said. “Samsung continues to struggle at the low-to-mid end, while the Galaxy S6 and S6 Edge combined look on course to reach a respectable 45 million units this year,” it added.
Tomi Engdahl says:
Yole Predicts the ‘Sensorization’ of Modern Life
http://www.eetimes.com/document.asp?doc_id=1326858&
After the consumerization of electronics — which took the semiconductor industry from something driven by enterprise computing to its current position as the supply of components of mobile devices — comes the sensorization of electronics, and of our lives. That is according to Jean-Christophe Eloy, CEO of market analysis firm Yole Developpement.
Over the next five years dramatic unit growth in MEMS sensors will be accompanied by a similar level of average selling price attrition along with investment cycles in software, production on 300mm-diameter wafers and the creation of novel methods of detection and related sensors.
Two of the categories likely to succeed are MEMS for photonics applications and gas sensors, according to Yole. This is based on an assessment of multiple criteria required for success in the market.
The global MEMS sensor market was worth about $11.1 billion in 2014, according to Yole. The company forecasts the market will be 30 billion units shipped in 2020 and be worth $20 billion.
Tomi Engdahl says:
10nm Chips Promise Lower Costs
http://www.eetimes.com/author.asp?section_id=36&doc_id=1326864&
The challenges in the supply chain logistics for semiconductors continue to increase, but the 10nm node will give one more opportunity to gain large benefits from technology scaling.
In March 2012, International Business Strategies (IBS) projected that gate costs at 20nm and 16/14nm would be higher than previous generations of technology. The analysis of the gate cost for 10nm now exhibits a different pattern, shown in the figure below.
While IBS did not project that scaling would stop, it predicted that cost penalties will occur with the adoption of 20nm bulk CMOS HKMG and 16/14nm FinFETs. These predictions on gate cost have been shown to be correct, and while 20nm products are in high volume for Apple, wafer capacity at 20nm is much lower than at 28nm.
TSMC provides another example. Its wafer capacity at 28nm is 150,000 wafers per month (WPM), but its wafer capacity at 20nm is nearly a third as much – 60,000 WPM. Globalfoundries also has 20nm capacity in its Malta, New York fab but the primary emphasis of this facility is on FinFETs. As for Samsung Electronics and UMC, they have decided to bypass 20nm.
While 16/14nm wafer volumes are ramping, wafer capacity at 16/14nm is again lower than 28nm. The wafer volume at 16/14nm is also driven by Apple again, but the length of use for 16/14nm technology will be determined by how rapidly 10nm will occur.
The lower gate cost at 10nm is due to the higher gate density that can be obtained compared to the increase in wafer cost. To attain lower gate cost at 10nm, there will be the need for high systemic and parametric yields, but this is achievable.
Tomi Engdahl says:
Software Development: Not Written Here Is New Norm
So long, source code
http://www.eetimes.com/document.asp?doc_id=1326865&
The new norm in the world of computing is code reuse, much of it proprietary third party or open source. Due to pressures of the market to produce software as fast as possible and at a low cost, many programmers are not doing what even a few years ago would be normal: writing their own original source code.
The pressure to instead use software developed elsewhere is intense. According to a survey of developers in 2014 by Venture Development Corp., the size of embedded code base alone is increasing at roughly three times the rate of the number of embedded software developers being hired. Where the number of software engineers available is expected to rise 9.6 percent through 2016, the expected code base growth is estimated to grow by 18.6 percent over the same period. Overall, embedded developers included in VDC’s 2014 survey said 51.1 percent of their project budgets were spent on software, versus 41.8 percent in 2012. Equally telling, respondents indicated that 51 percent of the end product value in 2014 was produced by the software versus 35.8 percent in 2012.
“Companies we surveyed said that they simply cannot keep pace in the embedded space with developers alone,” said Andre Girard, Senior Analyst at VDC. ”More than 40% of the developers in our survey reported their projects are running behind schedule.”
To deal with the disparity, embedded companies are currently using third party software in 44 percent of their designs. “Overall, 40.5% of respondents in medical device manufacturing, 28.6% in aerospace and defense, and 22.2% in auto and rail all expected to see an increase in commercial and other third-party code,” he said.
“Given such pressures, companies and their developers would be stupid not to take advantage of all the software code and IP building blocks openly available, and of all of the sources by which it can be obtained to speed up their designs.”
“The advent of tools such as NPM, Composer, Grunt, and Nugget, as well as the rise of GitHub as a major player in the open source community, give a good indication that developers are re-using code. These tools provide an easy way for developers to incorporate OSS within their own code with little effort – reusing existing modules instead of coding from scratch.”
Tomi Engdahl says:
Insecure radio links and the end of Moore’s Law discussed at DAC 2015
http://www.edn.com/electronics-blogs/benchtalk/4439670/Insecure-radio-links-and-the-end-of-Moore-s-Law-discussed-at-DAC-2015?_mc=NL_EDN_EDT_EDN_today_20150616&cid=NL_EDN_EDT_EDN_today_20150616&elq=9ebbdd84e2f44b8595dccd06965132df&elqCampaignId=23462&elqaid=26475&elqat=1&elqTrackId=860123c9a6bf418cacd9dfbb76f58490
Moore forever?
The Moore naysayers have been around for decades, predicting the demise of Moore’s Law, but so far, they’ve been proven wrong. But these days, more and more people are agreeing the end is nigh. But not Intel’s Vivek Singh. Despite oft-heard claims of flat or even increasing cost per transistor, Singh showed that transistor cost was actually continuing its exponential ride down to the zero limit. The 7nm node is already on track. His background is computational lithography, and he closed his talk with a pattern right out of a “magic eye” book.
Tomi Engdahl says:
Fairchild Out “Smarts” Dumb MEMS
http://www.eetimes.com/document.asp?doc_id=1326879&
Fairchild has been quietly perfecting microelectromechanical systems (MEMS) technologies since it first licensed the Sandia (National Laboratories) Ultra Planar Multilevel MEMS Technology (SUMMiT) for foundry services back in 2001. However, today after over a decade of technological development, the company is announcing its first Fairchild-branded MEMS using a “smart” technology more sophisticated than SUMMiT, namely a six-axis inertial measurement unit (IMU) with nine-axis sensor fusion algorithms.
“Fairchild knows that it is entering later a crowded space as ST, InvenSense and more recently also Bosch have established themselves solidly in the supply of IMUs and it can not offer a ‘me-too’ product,”
One “smart” aspect of Fairchild’s MEMS technology is its stacked die approach using state-of-the-art through-silicon vias (TSVs) instead of RF interference prone wire bonding.
Tomi Engdahl says:
GaN Systems’ 60A power transistor sets high point in current handling
http://www.edn-europe.com/en/gan-systems-60a-power-transistor-sets-high-point-in-current-handling.html?cmp_id=7&news_id=10006433&vID=1323#.VYJv1UZLZ4A
The gallium nitride device maker claims to now have the highest current GaN power transistor on market at 60A. The GS66516T 650V E-Mode power switch with top side cooling, low inductance GaNPX packaging and ultra low figure-of-merit Island Technology suits high frequency, high efficiency power conversion.
The GS65516T 650V E-mode power switch features GaN Systems’ topside cooling configuration announced in March this year, which allows the device to be cooled using familiar and conventional heat sink or fan cooling techniques. It is based on the company’s Island Technology die design, packaged in low inductance and thermally efficient GaNPX packaging and measures 9.0 x 7.6 x 0.45 mm. Features of the GS65516T 650V E-HEMT include reverse current capability, integral source sense and zero reverse recovery loss.
“GaN is real and happening right now,” according to Girvan Patterson, President, GaN Systems. “… hundreds of leading companies across the globe have embraced our technology to make sure they are among the first to market with new products that bring the benefits of GaN to products ranging from solar inverters to ultra-slim TVs.”
Tomi Engdahl says:
AMD Beats Nvidia to 2.5-D Graphics
Fiji GPU debuts with SK Hynix memory stack
http://www.eetimes.com/document.asp?doc_id=1326890&
AMD beat archrival Nvidia to the goal of rolling out high-end graphics cards that use DRAM chip stacks to provide more memory bandwidth — and thus performance — on relatively small, low-power boards. AMD rolled out the four new graphics cards at E3, a conference for serious gamers and those who develop for them.
The new Radeon R9 300 series is based on AMD’s new Fiji GPUs and High Bandwidth Memory (HBM) chip stacks from SK Hynix. “Fiji is the most complex and highest performance GPU we’ve ever built — it is the first with High Bandwidth Memory,” AMD CEO Lisa Su told attendees.
AMD described the 2.5-D HBM stack earlier this month but did not say which GPU would use the next-generation memory developed with SK Hynix. Its flagship Radeon Fury X uses 4GB of HBM memory, delivering up to 512 Gbits/second of memory bandwidth — an increase of around 63% over the previous generation Radeon R9 290X, principal analyst Patrick Moorhead of Moor Insights & Strategy wrote — to reach a 1.5x improvement in performance per watt.
The 28nm Fury X is a liquid cooled card with 4,096 stream processors and 64 compute units at clock speeds up to 1.05 GHz. Fury X can perform at up to 8.6 GFLOPS, a 65% over the previous generation, to display games at 45 frames per second (FPS) for 4K and 65 fps on future 5K displays.
Tomi Engdahl says:
Wearables Get Their Own MEMS
mCube optimizes power for tiny batteries
http://www.eetimes.com/document.asp?doc_id=1326880&
Ultra-low power followed by ultra-small size are the two most important aspects of microelectromechanical system (MEMS) sensors used in wearables. MEMS manufacturer mCube Inc. (San Jose, California) discovered this in its research and has set out to meet that not-so-tiny goal. Since mCube already had the industry’s smallest MEMS+CMOS die at 1-by-1 millimeters — allowing room for larger batteries in wearables — they decided to concentrate on technologies that would help extend the battery life of fitness, health monitoring and activity tracking wearables from hours or days, to weeks or months, according to chief executive officer (CEO) of mCube, Ben Lee.
“In a nutshell we already make the world’s smallest accelerometer — a 1-by-1 die in a 2-by-2 package,”
As an example, Lee described how their wearable MEMS chips saves power for a Bluetooth headset. When you set it down it goes into “sniff” activity-mode, which consumes only 0.6 microAmps by only sampling the accelerometer often enough to sense it being picked back up. When the user does pick it back up, mCube’s redesigned ASIC is fast enough to turn the headset back on and pair before the user even has it in their ear, according to Lee.
In fact, mCube has designed into its new ASIC three low-power modes for different functions — sniff at 0.6 microAmps, single-sample mode at 0.9 microAmps and a 25Hz sample rate, and a 4.7 microAmps mode with a 50Hz sample rate and full operation.
How’s it work?
The way mCube achieves its 1-by-1 millimeter die size is by using a special 8-inch wafer fabrication facility at Taiwan Semiconductor Manufacturing Company Limited (TSMC, Hsinchu, Taiwan) whose front-end fabs standard CMOS chips, but then switches to MEMS processing steps in the middle of the line thereby enabling a MEMS+CMOS chip to be created on a single fab line in 3-D with normal vias. As a result, there are no bonding wires to pick up RF interference or come loose, and much less parasitic capacitance than with the usual two-die solution, according to mCube.
Tomi Engdahl says:
News & Analysis
ASICs for the IoT Cross the Horizon
http://www.eetimes.com/document.asp?doc_id=1326924&
The recent burst of activity in the EDA, foundry, and contract chip design industries indicates that they have joined the scramble to stake out territory in the Internet of Things (IoT) market. While the design and fabrication of ASICs has broad applicability, EDA companies are now creating platforms and developing tool packages specifically to reduce barriers to entry for IoT design teams. The result may be a new wave of custom connected devices.
There are two major perceived issues with ASICs that have lead IoT design teams to work primarily with off-the-shelf resources instead, according to Huzefa Cutlerywala, a sr. director of Technical Solutions at custom chip designer Open-Silicon. “They think of ASIC design as being something long term,” Cutlerywala said in an interview with EE Times. “Because time to market is one of their main concerns, IoT designers have been avoiding ASICs.” The second major issue holding back ASIC use in the IOT, Cutlerywala pointed out, is risk. “It’s much safer when you’re starting with out-of-the-box functionality.”
But ASICs have significant advantages to offer the IoT design community, Cutlerywala added. Perhaps surprisingly, the traditional ASIC cost advantage in high-volume production is not necessarily one of them. “For IoT developers,” Cutlerywala said, “the product differentiation, added security, and form factor control that ASICs permit are more valuable than low cost.”
To secure these advantages for IoT developers while simultaneously reducing the design time and risks of an ASIC approach, the custom chip industry is turning to the platform approach, starting with sensor hubs for industrial IoT.
Tomi Engdahl says:
TechInsights: Inside 1X nm Planar NAND Flash
Planar NAND Flash continues to scale into 1X nm regime
http://www.eetimes.com/author.asp?section_id=36&doc_id=1326900&
NAND flash makers have started selling their 1X nm class of planar flash memory. Planar NAND flash may not make it past 10nm node, but here’s a look inside 15/16nm, analyzed by TechInsights.
Over the last year and a half, the major NAND flash makers have started selling their 1X nm class of planar flash memory.
There has been much discussion in the literature on the end of lithographic scaling of planar NAND flash, and its replacement with vertically stacked flash such as Samsung’s 3D V-NAND or Toshiba’s BiCS. There is a consensus that planar NAND will end near the 10 nm node, that is, one or two generations into the future from the 15/16 nm NAND flash that we at TechInsights are now completing analysis on.
The rate of process shrinks has slowed dramatically for the 25 nm and smaller product and this likely reflects the difficulties in implementing double patterning lithography and reducing electrical interference between adjacent cells.
Two approaches can be used for double patterning. Litho-etch-litho-etch (LELE) double patterning (DP) that is typically used for logic processes, or self-aligned double patterning (SADP) using sidewall spacers that is used by the memory makers. This has worked for NAND flash devices down to the present 16 nm node but may not make it to the 10 nm class of devices.
Tomi Engdahl says:
IBM Demos III-V FinFETs on Silicon
CMOS Compatible Process for Advanced Nodes
http://www.eetimes.com/document.asp?doc_id=1326904&
The entire semiconductor industry is trying to find a way to exploit the higher electron mobility of indium, gallium and arsenide (InGaAs) without switching from silicon substrates, including the leaders at Intel and Samsung. IBM has demonstrated how to achieve this with standard CMOS processing.
Last month IBM showed a technique of putting III-V compounds of InGaAs onto silicon-on-oxide (SOI) wafers, but now a different research group claims to have found an even better way that uses regular bulk-silicon wafers and have fabricated the InGaAs-on-silicon FinFETs to prove it.
Using a method similar to that of Belgium-based microelectronics research center Imec, IBM’s process has a twist that makes all the difference.
Tomi Engdahl says:
Liana B. Baker / Reuters:
Exclusive: Advanced Micro Devices mulling breakup, spinoff – sources
http://www.reuters.com/article/2015/06/19/us-amd-split-idUSKBN0OZ2KP20150619
Chipmaker Advanced Micro Devices is at the initial stage of reviewing whether to split itself in two or spin off a business, seeking to reverse its fortunes and take on rival Intel Corp, according to three people familiar with the matter.
The deliberations are preliminary and no decision has been made, the people said.
Tomi Engdahl says:
Sebastian Anthony / Ars Technica:
How lithium-ion batteries, industrial design and Moore’s law created modern laptops
The creation of the modern laptop
An in-depth look at lithium-ion batteries, industrial design, Moore’s law, and more.
http://arstechnica.com/gadgets/2015/06/from-laptops-that-needed-leg-braces-to-laplets-engineering-mastery/
Tomi Engdahl says:
ACE Awards Finalists Recognized for Innovation in Electronics
http://www.edn.com/electronics-blogs/now-hear-this/4439732/ACE-Awards-Finalists-Recognized-for-Innovation-in-Electronics?_mc=NL_EDN_EDT_EDN_today_20150618&cid=NL_EDN_EDT_EDN_today_20150618&elq=26f07b84e3064f93bd4bc597a75bbc03&elqCampaignId=23510&elqaid=26538&elqat=1&elqTrackId=e8a442f54f8e4dbaa959d98066fe022c
UBM has announced the finalists for the EDN and EE Times Annual Creativity in Electronics (ACE) Awards that honor technology innovators who demonstrate global electronics industry leadership.
Tomi Engdahl says:
Freescale i.MX 7 Finally Here
Heterogeneous Core Solutions Here Now
http://www.eetimes.com/document.asp?doc_id=1326934&
Application processors are the beating heart of the Internet of Things — from industrial controllers to handheld tablets to the new emerging legions of wearables. And with all the myriad functions performed by modern devices there was a gaping need for heterogeneous application processors that combined high-speed microprocessors with low-power microcontrollers, both of which could be turned on and off at will depending on the current function being performed. Freescale Semiconductor Inc. (Austin, Texas) claims to have pulled off just such a heterogenous mix for embedded designs with its long-rumored, but finally here, i.MX 7 series of application processors.
“Freescale is not the first to come out with heterogeneous processors — TI has done it for their OMAP [Open Multimedia Applications Platform] for mobile applications — but Freescale is the first to do it for embedded applications,”
The i.MX 7 is heterogeneous, because if houses either a single, or dual ARM Cortex-A7 high-performance (gigaHertz) microprocessor cores along with a single 288-megaHertzCortex-M4 micro-controller core (delivering 100 microWatt per megaHertz and 70 microWatt per megaHertz respectively)
The first member of the i.MX 7 series is built with Freescale’s 28 nanometer process
Tomi Engdahl says:
10nm Chips Promise Lower Costs
http://www.eetimes.com/author.asp?section_id=36&doc_id=1326864&
The challenges in the supply chain logistics for semiconductors continue to increase, but the 10nm node will give one more opportunity to gain large benefits from technology scaling.
In March 2012, International Business Strategies (IBS) projected that gate costs at 20nm and 16/14nm would be higher than previous generations of technology. The analysis of the gate cost for 10nm now exhibits a different pattern
While IBS did not project that scaling would stop, it predicted that cost penalties will occur with the adoption of 20nm bulk CMOS HKMG and 16/14nm FinFETs. These predictions on gate cost have been shown to be correct, and while 20nm products are in high volume for Apple, wafer capacity at 20nm is much lower than at 28nm.
TSMC provides another example. Its wafer capacity at 28nm is 150,000 wafers per month (WPM), but its wafer capacity at 20nm is nearly a third as much – 60,000 WPM.
While 16/14nm wafer volumes are ramping, wafer capacity at 16/14nm is again lower than 28nm. The wafer volume at 16/14nm is also driven by Apple again, but the length of use for 16/14nm technology will be determined by how rapidly 10nm will occur.
The expectation is that 10nm will be a high volume and long lifetime technology node. TSMC and Samsung are projecting risk production for 10nm in Q4/2015, and the customer target is clearly Apple. If there is the ability to ramp up 10nm in 2016 or even in mid-2017, 16/14nm will be a short lifetime technology node.
EDA Faces 10, 5nm Hurdles
http://www.eetimes.com/author.asp?section_id=36&doc_id=1326920&
The EDA community faces multiple challenges at the 10nm and 5nm nodes that experts will discuss at Semicon West.
The timing of insertion for extreme ultraviolet lithography has been debated and discussed for a number of years. Some experts have expressed the belief that EUVL will be ready for high-volume manufacturing (HVM) in the 2020 timeframe.
Development work for the 10nm node has been done primarily using 193 immersion (multi-patterning) lithography, raising the question of whether designs will be backward compatible should EUVL become available.
“If EUV becomes production ready in 2020, then it will be too late for the initial 10nm production tape outs,” said Rey.
“As such, for 10nm, EUV will have to show it is a cost-effective alternative to the most critical layers that currently require several multi-patterning (MP) exposures for immersion,” he said. “The cost comparison should consider both production costs and the adoption costs due to re-design and new masks,” he added.
Rey does not think it is possible at this time to come to a firm conclusion as to the feasibility of complete backwards compatibility.
“However, multi-patterning brings very specific requirements on designs that may not be required if EUV supplants MP for all the critical layers,”
Tomi Engdahl says:
Intel — The Litmus Test
http://www.eetimes.com/author.asp?section_id=36&doc_id=1326937&
Vivek Singh, an Intel fellow, in his DAC 2015 keynote Moore’s Law at 50: No End in Sight presented again the Intel chart below suggesting straight (log) line transistor cost reduction with dimensional scaling. In fact, his cost/transistor drop even seems to accelerate beyond the linear at 14 and 10 nanometers.
Less than a week later, Handel Jones (IBS) in his blog 10nm Chips Promise Lower Costs published an update down to 10nm of his well-known chart, presented below, of transistor cost with scaling.
Yes, 10nm transistor cost is a bit less than that of the 16/14nm node, but still higher than that of the 28nm node and clearly showing that the historical cost reduction of 30% per node stopped at 28nm node. From that point on Handel Jones’ cost projections have been either flat or even a bit higher. Clearly, those charts are in a striking contradiction!
“Samsung spent several years developing its 14nm technology and debating which process node it would invest in after 28nm. Low expects that 28nm will still be a popular process node for years to come because of its price…The cost per transistor has increased in 14nm FinFETs and will continue to do so
Intel has repeatedly used their chart in effort to promote their foundry business in competition with TSMC and in the process won the Altera business.
Tomi Engdahl says:
Nonvolatile memory resists gamma radiation
http://www.edn.com/electronics-products/other/4439730/Nonvolatile-memory-resists-gamma-radiation?_mc=NL_EDN_EDT_EDN_today_20150622&cid=NL_EDN_EDT_EDN_today_20150622&elq=5b4a0faf6fc040eab0fed59e3887b877&elqCampaignId=23547&elqaid=26584&elqat=1&elqTrackId=358dfc1ea20c4f1cb6a264b20aef4676
Using only one contact to simplify implementations in small, disposable medical sensors, the DS28E80 1-Wire EEPROM from Maxim Integrated Products resists gamma radiation of up to 73 kGy (kiloGray), allowing OEMs to calibrate a consumable medical sensor and to monitor or control unsanitary reuse of medical disposables. Gamma radiation sterilization is typically used on single-use disposable medical sensors and consumables, but the method is incompatible with conventional floating-gate memory technologies, as gamma’s high-ionizing radiation erases the memory.
The DS28E80 nonvolatile memory chip has 248 bytes of user-programmable memory, organized in blocks of 8 bytes. Each memory block can be written 8 times and individually write-protected.
In addition, the DS28E80 has its own guaranteed-unique 64-bit registration number that is factory-programmed into the chip. This registration number can serve as a node address in a multiple-device 1-Wire network.
Tomi Engdahl says:
SiTime uPower MEMS oscillator for wearables, IoT and mobile
http://www.edn.com/electronics-products/electronic-product-reviews/other/4439707/SiTime-uPower-MEMS-oscillator-for-wearables–IoT-and-mobile?_mc=NL_EDN_EDT_EDN_productsandtools_20150622&cid=NL_EDN_EDT_EDN_productsandtools_20150622&elq=4c4ce6ac5d6d4341b4df83738d39fc2b&elqCampaignId=23553&elqaid=26590&elqat=1&elqTrackId=82e10554649e42228461b73c94aeb0cf
SiTime Corporation recently announced a new family of µPower MEMS Oscillators for the wearable, IoT and mobile markets. The SiT8021 oscillator is the first device in this family. The company claims that the device consumes 90% lower power, is 40% smaller, and 70% lighter than existing quartz devices. This product enables long battery life as well as the small size and weight for smart watches, fitness bands, tablets, smart phones, portable audio and accessories.
Tomi Engdahl says:
PCIe cards generate signals to 625 Msamples/s
http://www.edn.com/electronics-products/electronic-product-reviews/other/4439739/PCIe-cards-generate-signals-to-625-Msamples-s?_mc=NL_EDN_EDT_EDN_productsandtools_20150622&cid=NL_EDN_EDT_EDN_productsandtools_20150622&elq=4c4ce6ac5d6d4341b4df83738d39fc2b&elqCampaignId=23553&elqaid=26590&elqat=1&elqTrackId=9d07efc99cda4415ade7ca6467cce5aa
When you need to generate test signals and can install your test equipment inside a PC’s chassis, the M4i.6620-x8, M4i.6621-x8, or M4i.6622-x8 PCIe boards from Spectrum Instrumentation. Each board can produce waveforms at rates up to 625 Msamples/s with bandwidth to 200 MHz and 16-bit vertical resolution. The cards differ in number of channels only.
M4i.6620-x8: 1 channel
M4i.6621-x8: 2 channels
M4i.6621-x8: 2 channels
All cards use PCIe x8 or x16 slots. FIFO memory lets you stream data to the cards at rates up to 1.5 Gbits/s. When using the two-channel or four-channel models, you can synchronize the channels to an internal or external clock. By combining cards, you can build a system with up to 32 channels (8 cards) using Spectrum’s Star Hub module. Output voltage levels are ±160 mV to ±5 V into high-impedance loads and ±80 mV to ±2.5 V into 50 Ω loads.
Tomi Engdahl says:
The Thrill of Shenzhen — Candyland for Electronics Geeks
http://hackaday.com/2015/06/22/the-thrill-of-shenzhen-candyland-for-electronics-geeks/
Tomi Engdahl says:
PCIe 16G May Take Until 2017
http://www.eetimes.com/document.asp?doc_id=1326922&
Engineers have 16 GTransfers/second up and running in the lab for PCI Express 4.0, aka Gen 4. The bad news is this is the last turn of the crank for a copper version of the interconnect and, despite progress, a final 1.0 version of the spec may not be ready until early 2017.
Developers in the PCI SIG hope to complete a 0.7 version of the spec by the end of the year, at which stage they expect no major changes to the technology. Getting out ahead of the standard, Cadence and Synopsys will both announce PCI Express 4.0 PHY and controller blocks at the annual PCI SIG conference here June 23.
The spec may be taking a bit longer to finish than previous PCIe generations. That’s understandable given the SIG chose to go for what they thought was the maximum possible data rate, squeezing copper links for all they could deliver, twice as much as in today’s Gen 3 products.
“We are getting 16G, something no one thought was possible a few years ago,” said Al Yanes, president of the PCI SIG in an interview with EE Times.
Gen 4 will use a new connector but the spec will be backward compatible mechanically and electrically with today’s 8GT Gen 3.
It’s easy to extrapolate that sometime beyond 2017 engineers pushing the limits of processor performance will need optical links. Several efforts over the last 20 years have pushed toward optical board and chip interconnects, but so far copper delivered required data rates at lower costs than any optical solutions.
“I got to believe engineers will find way to make [optics] cost effective by the time they are needed – even four years ago there was a big push on it,” Yanes said.
As of today the SIG has no optical programs in the works. Given the time frame, its possible alternatives may crop up.
Separately, the SIG expects to release a 1.0 standard in the fall for OcuLink, a cabled version of PCIe that uses four Gen 3 8 GT/s links. It is seen as an alternative to the Lightning interconnect co-developerd by Apple and Intel.
Tomi Engdahl says:
The Aging of EDA
http://www.eetimes.com/author.asp?section_id=36&doc_id=1326950&
Companies like Google attract people right out of college, whereas EDA conferences always seem to have an over-abundance of grey (or white) heads.
I just got back from the Electronic Design Process Symposium (EDPS) where an interesting and perennial question was asked: “Shouldn’t we be worried that everyone in EDA is so old?” The contrast is always drawn with companies like Google and Facebook who attract people right out of college (even pre-college), whereas EDA conferences always seem to have an over-abundance of grey (or white) heads like myself. The implication is that sources of new ideas are drying up, and that pretty soon EDA as we know it will disappear, since those of us who know anything about the topic will all be in rest-homes. I don’t think the outlook for EDA is quite this bleak.
First, conferences have a sampling bias. If you walk around the offices of most EDA companies, you will see lots of young people — maybe not Google-young, but plenty not-yet-married, getting married, and starting families.
In my view, the longer-term reason to be optimistic about the flow of young people into EDA is that our fascination with apps is limited. What really gets us excited is new devices; new devices means new hardware; and new hardware will drive the need for new EDA. This won’t look like today’s EDA, maybe, but it will pull in new talent. Once the Google / Facebook euphoria dies down, we’ll remember that technical talent chases deep technical challenges.
Tomi Engdahl says:
A Chip That Mimics Human Organs Is the Design of the Year
http://www.wired.com/2015/06/chip-mimics-human-organs-design-year/
Earlier this year, Paola Antonelli, the senior curator of design and architecture at the Museum of Modern Art, added an intriguing object to the museum’s permanent collection. It was a clear plastic chip, no bigger than a thumb drive, and it could soon change the way scientists develop and test life-saving medicines.
Called Organs-On-Chips, it’s exactly what it sounds like: A microchip embedded with hollow microfluidic tubes that are lined with human cells, through which air, nutrients, blood and infection-causing bacteria could be pumped. These chips get manufactured the same way companies like Intel make the brains of a computer. But instead of moving electrons through silicon, these chips push minute quantities of chemicals past cells from lungs, intestines, livers, kidneys and hearts. Networks of almost unimaginably tiny tubes give the technology its name—microfluidics—and let the chips mimic the structure and function of complete organs, making them an excellent testbed for pharmaceuticals.
Tomi Engdahl says:
Building a Safe and Robust Industrial System
http://www.eeweb.com/company-blog/avago_technologies/building-a-safe-and-robust-industrial-system/
Should production line stoppage occur at an industrial automation company, millions of dollars and opportunity costs can be lost while trying to fix the problem and get the lines running again.
Breakdown can occur in areas such as electromagnetic interference, high voltage surges, and safety standards. These areas of concern need to be checked at the initial design level rather than later, after manufacturing has been developed and built.
The harsher environment on the factory floor poses issues not relevant in an office environment.
Optocouplers are used extensively in industrial networking systems for numerous purposes. They allow electrical circuits and highly diverse voltage levels to work together as a system and can be coupled while remaining electrically isolated or galvanically separated from one another.
Circuit designers, when designing their applications, can encounter three types of isolation related issues:
Voltage Transients: These are potentially high current or voltage surges that may damage components and cause electric shock, possibly endangering human life. They are usually brief and intense surges between two circuits or systems.
Ground Loop Currents: These are unwanted signals between interconnections of different ground potentials, which cause disruptive ground loops. They are usually found in communication networks having different grounds at various connecting nodes. The potential difference between these grounds can be alternate current (AC) or direct current (DC), with a combination of various noise components found in that communication system. If the voltage potential is large enough, it may cause damage to equipment (e.g., communication ports), transmission error, or degradation of data signals. Long term exposure results in the heating and burning of circuit boards which damages components and causes electric shock, some potentially deadly to human beings.
High-voltage Level Shifting: With the migration of digital ICs to lower operating voltages, the need for devices to separate sensitive electronics from high power electronics is growing. In order to ensure reliable information exchanges and prevent current flow between different ground reference voltages, there is a need to use isolation. For example, in a motor control application, the electronic system of a motor consists of 2 stages, the low voltage controller and the power module. Within such a system, it is important to protect and insulate the two stages from switching transients and common mode voltage fluctuations. At the same time, it is necessary to provide level shifting and signal isolation of interface control and feedback circuits.
Tomi Engdahl says:
Foxconn’s going to ‘exploit’ Indian labour? SCORE! Bye, poverty
Now the Indians will get rich too
http://www.theregister.co.uk/2015/06/17/foxconns_moving_the_apple_production_line_to_india_hurrah/
El Reg serves us up the news that Foxconn is looking to India to set up production lines, presumably for the assembly of Apple’s products. This is excellent news as it means that now Indian workers will get exploited and become rich, as those Chinese have in recent decades.
And yes, it is indeed exploitation and yes they will indeed get rich(er).
India does try to promote internal assembly by allowing components in tariff-free but charges for assembled pieces – and then rather screwing this up by playing silly buggers with the factories when they are there, as with Nokia’s former assembly plant in the country.
We can check this, too. Before the great explosion of Chinese assembly plants (and no, I’m not saying this was the only factor) manufacturing wages in China were around the $1,000-a-year mark in 2000. Today they’re around the $6,500.
So, as foreign companies piled in in search of cheap labour, even the labour supply of a place as large as China got soaked up and thus wages rose. And now, obviously, there’s a move to go off in search of the next bolus of cheap labour.
Textiles to Vietnam, Indonesia and Bangladesh, here we’ve got electronics assembly to India. And yes, undoubtedly, the labour in those places will be exploited; they’ll earn peanuts to produce stuff of high value. The more people who follow in that search for the lucre of profits, the faster local wages will rise
In fact, that progressive move around the globe in search of those last pockets of cheap labour is the thing that is actually, finally, going to end that absolute poverty that we all decry.
Cheaper Apple iStuff? Foxconn eyes costs-busting Indian move
China’s wage inflation finally prompts action
http://www.theregister.co.uk/2015/06/12/hon_hai_foxconn_opening_factories_india/
Taiwanese multinational and Apple device manufacturer Hon Hai/Foxconn is planning to expand into India, opening roughly ten factories and date centres by 2020, according to Indian government officials.
Reuters reports the touted move may lower prices in “the world’s third largest smartphone market where [Apple] trails Samsung Electronics and local players.”
Foxconn has given no details yet, citing commercial sensitivity.
Tomi Engdahl says:
AMD: We’re not splitting our gfx and servers biz, ignore all the rumours
Firm dismisses break-up or sale talk but something’s got to give
http://www.channelregister.co.uk/2015/06/24/amd_break_up_denial/
Under-the-weather chip maker AMD is denying that it is mulling a break-up or spin-off – but both analysts and channel customers agree something has to change if the firm is to survive prosper.
“Usually we do not comment on rumours and speculation but in this case there is no such plan in the works, and we are committed to the plans that we presented to financial analysts in May.”
Tomi Engdahl says:
Secure IoT MCUs Drive Freescale-NXP
http://www.eetimes.com/document.asp?doc_id=1326956&
The future of Freescale Semiconductor and NXP is in connecting and securing the Internet of Things, with a major focus on automotive. The CEOs of both companies outlined their collective vision for the merger, which will likely close in November, during a keynote at Freescale Technology Forum (June 23).
The merger will create the fifth-largest non-memory semiconductor company, NXP CEO Rick Clemmer said at Freescale Technology Forum (held here, June 22-24). The goal isn’t to generate massive cost savings, but to provide more well-rounded options for IoT customers.
Leading semiconductor companies — Intel, Qualcomm, Broadcom/Avago, and Texas Instruments — all have narrowly focused strategies that focus on microcontrollers, communications, and analog. This leaves a prime area for the new NXP to focus on.
“No companies are focused on creating secure connections and infrastructure for a smarter world,” Freescale CEO Gregg Lowe said. “Clearly if we do that successfully, and we can do that very rapidly, we can move up in succession.”
Tomi Engdahl says:
Power monitor IC provides configurable analog output
http://www.edn.com/electronics-products/other/4439745/Power-monitor-IC-provides-configurable-analog-output?_mc=NL_EDN_EDT_EDN_today_20150624&cid=NL_EDN_EDT_EDN_today_20150624&elq=3c4609e8cd964470afdd0abdd2d4fa24&elqCampaignId=23602&elqaid=26641&elqat=1&elqTrackId=7b96ca2cd4e94785b89a59314761dd6e
he PAC1921 power-monitoring device from Microchip Technologies is a high-side current sensor with both a digital output and a configurable analog output that can present power, current, or voltage over a single output pin. All power-related output values are also available simultaneously over the 2-wire digital bus, which is compatible with I2C.
It monitors power rails from 0 to 32 V with a full-scale capability of 100 mV across the sense resistor. The device achieves 1% power measurement accuracy and cancels the zero offset from the input pins.
The analog output is adjustable for use with 3-V, 2-V, 1.5-V, or 1-V microcontroller inputs.
Tomi Engdahl says:
Introduction to AXIe
http://www.edn.com/electronics-blogs/test-cafe/4439746/Introduction-to-AXIe?_mc=NL_EDN_EDT_EDN_today_20150624&cid=NL_EDN_EDT_EDN_today_20150624&elq=3c4609e8cd964470afdd0abdd2d4fa24&elqCampaignId=23602&elqaid=26641&elqat=1&elqTrackId=e587b1c950ec41afa71ba91c6f21994b
If you’ve been reading about modular instruments, or speaking with one of several vendors that offer AXIe-compatible products, you may have come across the term “AXIe”. What is it? Where is it used? How is it different, or similar, to other instrument standards? How does it compare to PXI? If so, you’ve come to the right place. These are the questions I aim to answer in this introduction to AXIe.
AXIe is a modular standard of pluggable test instrumentation similar to PXI or VXI, but with some important differences. AXIe is an abbreviation for “Advanced Telecommunications Computing Architecture Extensions for Instrumentation and Test”, a reference to the industrial bus standard it is based on.
AXIe is often referred to as the “big brother” of PXI, since it acts like a large PXI system in many aspects, but supports a larger board format suitable for high power applications.
like PXI, AXIe is based on a high-speed PCIe (PCI Express) data fabric, a low latency and high-speed bus. AXIe data communication is so similar to PXI, that a controller perceives the two to be the same, and uses similar IVI or LabView drivers to control the instruments.
The most obvious difference is the module size, so let’s start with that.
An AXIe module measures 12.7 inches by 11 inches, nearly six times the area of a PXI module.
The large format and air passages allow up to 200 watts to be reliably cooled on a single module, compared to PXI’s 30 watts.
What types of applications need these board and power densities? AXIe finds itself deployed in high-speed data converter and digital applications in mil/aero (military/aerospace), semiconductor characterization and test, and high-energy physics. Today, AXIe digitizers range up to 40Gs/s, arbitrary waveform generators up to 65Gs/s, and bit error rate testers to 32Gb/s.
AXIe chassis must be awfully tall to support these larger modules, right? Actually, not. In fact, the smallest AXIe chassis are only 2U rack units tall, half that of a typical PXI chassis. This brings us to the second major physical distinction with PXI: most AXIe chassis, at least for small module counts, are horizontal.
AXIe chassis can come in any number of slots up to 14 per mainframe. However, 2-slot, 5-slot, and 14-slot are the most common.
AXIe chassis typically (not always) come with the same “Slot 1” capability built into the chassis by the chassis vendor itself. They are ready to plug in instrument modules. T
AXIe includes a high performance triggering system to complement and coordinate the modules. There are 12 parallel triggers lines that span all slots, as well as a star-based trigger and timing subsystem that originates from the system slot. The 12 parallel trigger lines can operate to 100MHz rates.
AXIe supports communication to each module via PCIe via the system module. Today, each link is a x4 link (4 lanes wide), which equates to 2GBytes/s nominal throughput with a typical PCIe Gen 2 system. The AXIe Consortium has approved an extension to AXIe that will widen the links up to x16, increasing the nominal data rates of AXIe to 8GByte/s. Increasing from Gen 2 to Gen 3 speeds will nearly double the bandwidth again.
To control the modules, Cable PCIe (a flexible high speed cable) is connected between an external controller and the system module. If the system module functionality is embedded in the chassis, as is typically the case, there will be a Cable PCIe connector on the chassis. Users may also choose to deploy an embedded controller, one designed into the AXIe format. In this case, the embedded controller is simply plugged into one of the AXIe slots.
In addition to PCIe, an AXIe chassis also routes LAN to each slot. Though most modules are PCIe-based, LAN communication is also allowed, and may deliver new low cost capability in the future.
A unique bus structure to AXIe is called the “local bus”. Referring to the trigger and timing figure on the previous page, you can see that the local bus is a set of very short buses that connect from one slot to an adjacent slot, and no further. The short path length, combined with the large number of lanes (62 differential pairs) allows very high data rates. AXIe products have shown 40GByte/s and even 80GByte/s rates to be transferred over the local bus. The local bus itself is protocol agnostic, and can include timing as well as data signals.