Electronics trends for 2015

Chip designs that enable everything from a 6 Gbit/s smartphone interface to the world’s smallest SRAM cell will be described at the International Solid State Circuits Conference (ISSCC) in February 2015. Intel will describe a Xeon processor packing 5.56 billion transistors, and AMD will disclose an integrated processor sporting a new x86 core, according to a just-released preview of the event. The annual ISSCC covers the waterfront of chip designs that enable faster speeds, longer battery life, more performance, more memory, and interesting new capabilities. There will be many presentations on first designs made in 16 and 14 nm FinFET processes at IBM, Samsung, and TSMC.

There is push to go to even smaller processes, and it seems that next generation of lithography equipment are started to being used. Earlier expectation was for chipmakers to use traditional immersion lithography for production of 10 nm chip, but it seems that extreme ultraviolet (EUV) scanners that allows allow scaling to 10 nm or even smaller is being used. TSMC to Use EUV for 7nm, Says ASML. Intel and TSMC have been injecting money in ASML to push process technology.

2015 promises to see initial FPGA product releases and (no doubt) a deluge of marketing claims and counter-claims. One thing is certain: 2015 will not be boring. There will be FPGA products that use processes beyond 20nm, for example Altera and  Xilinx have committed to use the TSMC 16nm FinFET technology. There is  publicized (and rumored) race to get to production at 14nm has seen time frames for initial samples move into 2015. However, with both FPGA companies reporting gross margins of close to 70 percent, it would be possible for either company to take an initial hit on margin to gain key socket wins.

It seems that the hardware becomes hot again as Wearables make hardware the new software. Apple invest its time when it released the Apple Watch last quarter, going up against the likes of Google’s Android Wear and others in the burgeoning wearables area of design. Once Apple’s bitten into a market, it’s somewhat a given that there’s good growth ahead and that the market is, indeed, stable enough. As we turn to 2015 and beyond  wearables becomes an explosive hardware design opportunity — one that is closely tied to both consumer and healthcare markets. It could pick up steam in the way software did during the smartphone app explosion.

There will be more start-up activity within hardware sector. For recent years, the software has been on the main focus on the start-ups, and the hardware sector activity has been lower. Hardware sector has seem some start-up activity with many easy to use open hardware platforms became available (make development of complex devices easier and reachable for smaller companies). The group financing (Kickstarter, Indiegogo, etc.) have made it possible to test of new hardware ideas are market-worthy and get finance to get them to production.

EEs embrace hackathons aand accelerators. Design 2.0 is bubbling up in the engineering community, injecting new energy into the profession. In many ways, it’s the new Moore’s Law. Easy to use open hardware development platforms have made it possible to design working hardware device prototypes within hackathons.

Silicon Startups Get Incubator article tells that there will be new IC start-up activity as semiconductor veterans announced plans for an incubator dedicated to helping chip startups design their first prototypes. Keysight, Synopsys, and TSMC have signed exclusive deals to provide tools and services to the incubator. Silicon Catalyst aims to select its first batch of about 10 chip startups before April.

1,206 Comments

1. April 16, 2015 at 8:14 am

   Tomi Engdahl says:

   Validating MEMS and other sensors
   http://www.edn.com/design/integrated-circuit-design/4439188/Validating-MEMS-and-other-sensors?_mc=NL_EDN_EDT_EDN_today_20150415&cid=NL_EDN_EDT_EDN_today_20150415&elq=32e16977841c4c9bb5457852642ca4ab&elqCampaignId=22552&elqaid=25360&elqat=1&elqTrackId=4ee32b85d8a645448a26010d810a446e

   Sensors find places in almost every consumer, industrial, and automotive product these days. For example, mobile devices have accelerometers, ambient light sensors, gyroscopes, etc., and automobiles have airbag sensors, tire pressure monitors, proximity/pedestrian detection sensors, and more. No matter what applications they go in, ensuring sustained operation of sensors throughout their life-cycle is extremely important.

   This paper discusses the various platforms used during sensor product validation. Depending on the type of sensor under validation (“SUV”), one or more of the below platforms are applicable for evaluation.

   Reply
2. April 16, 2015 at 8:15 am

   Tomi Engdahl says:

   Busting the 3 Big Common Myths about Physical Prototyping
   http://www.techonline.com/electrical-engineers/education-training/tech-papers/4438903/Busting-the-3-Big-Common-Myths-about-Physical-Prototyping?_mc=NL_EDN_EDT_EDN_systemsdesign_20150415&cid=NL_EDN_EDT_EDN_systemsdesign_20150415&elq=0a130cb4e2b143eaa9476c5930f8a30a&elqCampaignId=22554&elqaid=25362&elqat=1&elqTrackId=f11d00c41d9541f289a0a01914eb7d88

   FPGA-based prototyping is popular because it provides an economical way to functionally validate an ASIC design by creating a prototype that runs “at speed”, includes real world I/O, and enables early software development. Experienced prototypers are familiar with its benefits but there are still designers opposed to physical prototyping for a number of reasons. These are all myths rooted in the struggles of developing in-house prototypes with limited automation software of years past.

   Reply
3. April 16, 2015 at 8:17 am

   Tomi Engdahl says:

   Altera’s new Power Management team kicks it into high gear
   http://www.edn.com/design/power-management/4439176/Altera-s-new-Power-Management-team-kicks-it-into-high-gear?_mc=NL_EDN_EDT_EDN_systemsdesign_20150415&cid=NL_EDN_EDT_EDN_systemsdesign_20150415&elq=0a130cb4e2b143eaa9476c5930f8a30a&elqCampaignId=22554&elqaid=25362&elqat=1&elqTrackId=81c4fd367fbe438eb5da3337754ee82e

   Reply
4. April 16, 2015 at 9:03 am

   Tomi Engdahl says:

   Fuse Characteristics of Surface Mount Current Sensor ICs
   http://www.eeweb.com/company-blog/allegro_microsystems/fuse-characteristics-of-surface-mount-current-sensor-ics/

   Allegro MicroSystems, LLC offers a broad product family of current sensor IC solutions with integrated conductors. These products can be used to measure current in a variety of applications, including motor control, inverters, load detection and management, and overcurrent fault detection. For applications with normal operating currents up to 50 A, Allegro offers current sensor ICs in a number of standard surface mount packages, such as SOIC-8, SOICW-16, QSOP-24, and QFN1. Due to their integrated conductors, these sensor ICs are placed in series with the current they are measuring. The integrated conductors are especially low resistance (1.2 mΩ or less depending on the package), so they generate very little heat under normal operating conditions. However, like all components that are in the current path, it is important to understand how they behave when subjected to currents above their rated nominal capability due to short circuits, inrush currents, or other transient conditions.

   The heat dissipation characteristics, particularly at moderate currents (<150 A), will vary depending on the PCB layout used for the high current traces near the current sensor IC.

   Reply
5. April 16, 2015 at 9:17 am

   Tomi Engdahl says:

   Power Electronics Market Surges
   Electric vehicles help drive growth
   http://www.eetimes.com/document.asp?doc_id=1326345&amp;

   The power electronics market is recovering after several tough years and will continue to expand, according to analysts at French research firm Yole Development. The market will surpass 17 billion Euro by 2020, largely driven by electric and hybrid vehicles.

   IGBT power modules will lead this growth and reach a compound annual growth rate of 10.3% through 2020, compared to 5.1% growth for discrete components.

   ”New technologies have appeared in the last decade, such as Super Junction MOSFETs, which have brought the MOSFET family into higher voltage segments up to 900V, with better performance. In terms of power packaging, ongoing evolution is driven particularly by the EV/HEV industry,” the Yole report said.

   Power electronics must follow the broad industry trend to become more compact

   There is more space-saving pressure in electric vehicles, for example, which drives lower density components with voltage ranges between 600 Volts and 1,200V. EV also need lower than 10 kW on-board chargers and DC/DC converters, said Pierric Gueguen, business unit manager of Yole power electronics.

   Gueguen also pointed to the wide band gap device market, which Yole expects to represent 5% of the total power market by 2020. Silicon carbide (SiC) and gallium nitride (GaN)-based devices are intended for high voltage, high frequency, and high temperature applications such those in rail traction and PV inverter markets.

   “Wide band gap — compared to typical power devices like IGBTs and super junction MOSFETs — have intrinsic properties that are better than silicon,” Gueguen told EE Times. “In the coming years we see those wide band devices will enter automotive applications mainly due to smaller converters.”

   Reply
6. April 16, 2015 at 9:18 am

   Tomi Engdahl says:

   Intel Does Balancing Act
   Q1 flat: PCs down & IoT, servers, tablets up
   http://www.eetimes.com/document.asp?doc_id=1326348&amp;

   Intel reported flat Q1 revenue year over year, with $2.6 billion operating income, up 4 percent over last year. Intel, the largest semiconductor company, hit a Q1 revenue of $12.8 billion with operating income of 2.6 billion (net income 2.0 billion), the company reported Tuesday (April 14) in its earnings call.

   “Year-over-year revenues were flat, with double-digit revenue growth in the data center, IoT and memory businesses offsetting lower than expected demand for business desktop PCs,” said Intel CEO Brian Krzanich in a prepared statement.

   Reply
7. April 16, 2015 at 9:20 am

   Tomi Engdahl says:

   Would MediaTek Dare Take on Intel in PC Business?
   http://www.eetimes.com/author.asp?section_id=36&doc_id=1326356&amp;

   MediaTek, the world’s third-largest chip designer, is rumored to take on Intel in the PC business this year.

   Some interesting speculation has cropped up on the Internet in recent days that MediaTek, the world’s third-largest chip designer, may take on Intel in the PC business sometime around the end of this year.

   Much of the conjecture centers around MediaTek’s MT8173 processor, which combines two ARM Cortex A53 cores with a pair of Cortex A72 cores. The MediaTek chip scores about 1,500 on single-core Geekbench results — reportedly the highest score ever for a mobile processor, including those from Intel.

   An extrapolation of the 1,500 single-core score indicates a multi-core grade of about 7,500 for an octa-core processor based on A72 technology. The MT8173 is fabricated with 28 nm process technology at Taiwan Semiconductor Manufacturing Co. (TSMC).

   If MediaTek were to produce the chip with TSMC’s 16 nm FinFET when the technology becomes commercially available later this year, so the story goes, MediaTek’s new version of the chip would benefit from a 25% boost in performance, yielding a single-core performance score of about 1,850 and an octa-core rating as high as 9,000.

   That would put the hypothetical MediaTek chip in the same ballpark as Intel’s desktop PC processors.

   Reply
8. April 16, 2015 at 9:20 am

   Tomi Engdahl says:

   Con Min Compliance No Easy Task, But Doable
   http://www.eetimes.com/author.asp?section_id=36&doc_id=1326353&amp;

   The trading of illegal minerals to finance conflicts, particularly in central Africa, is an ongoing concern for us all. However, meeting the demands of the Dodd-Frank Act has proven easier said than done.

   In 2010, the Dodd-Frank Act was the first legislation aimed expressly at addressing the issue by changing corporate behavior.

   The European Union is now moving to finalize its own legislation against the trade in conflict minerals and, post Dodd-Frank, was urged to impose less burdensome obligations. The current European Commission proposal includes a voluntary self-certification scheme that will only apply to companies marketing raw materials.

   Reply
9. April 16, 2015 at 9:26 am

   Tomi Engdahl says:

   Virtual Factory to reduce costs

   European companies and research institutes have jointly developed a cloud-based, modular and easily customizable software platform, which can be exploited to increase the sustainability of industrial products, as well as to reduce the manufacturing costs and emissions. EPES project has also been involved in VTT.

   EPES-platform (Eco-Process Engineering System for composition of Services to Optimise product life-cycle)) provides a virtual collaboration platform for organizations to work together developing the same product or service. Recently completed project, combined with effective cloud computing, Internet of Things, co-operation networks, simulation, and environmental impact assessment.

   The software can be used to clarify the extent and automate complex development tasks, as well as a combination of manual expert concluded that the software improvements. Analyses are repeatable and will therefore allow the traditional ways of the wider structuring.

   Source: http://www.etn.fi/index.php?option=com_content&view=article&id=2691:virtuaalitehdas-vahentaa-kustannuksia&catid=13&Itemid=101

   Reply
10. April 16, 2015 at 3:51 pm

    Tomi Engdahl says:

    Robust asynchronous-reset architecture for scan coverage
    http://www.edn.com/design/integrated-circuit-design/4439203/Robust-asynchronous-reset-architecture-for-scan-coverage?_mc=NL_EDN_EDT_EDN_today_20150416&cid=NL_EDN_EDT_EDN_today_20150416&elq=31567fca78c8473ea0bae727225fd3b0&elqCampaignId=22576&elqaid=25387&elqat=1&elqTrackId=28c8b66d21194520b905dc09b7748fcc

    Digital integrated circuits typically use asynchronous set/resets to set the value of memory elements (flip-flops) without depending on any clock pulses. This logic, however, requires special handling during scan based testing of the device. Also, the logic associated with asynchronous set/reset may constitute 2-4% of the total faults in a design. With growing focus on high test-coverage and zero DPPM, especially for critical applications like automotive and medical devices, it is important to thoroughly test such faults to ensure overall system robustness.

    This article presents various scenarios, and the test architecture to robustly detect scan coverage – including potential race conditions – on asynchronous paths.

    The salient features of this architecture are:

    Targets coverage on internally generated set and reset logic
    Avoids glitches due to reconvergence on scan-enable and async-SE signals
    Reuses scan-in pin during capture to delay the async-SE trigger

    Reply
11. April 17, 2015 at 8:08 am

    Tomi Engdahl says:

    Samsung Describes Road to 14nm
    FinFETs a challenge, FD-SOI an alternative
    http://www.eetimes.com/document.asp?doc_id=1326369&amp;

    ust days after it was confirmed the Samsung Galaxy S6 uses an Exynos processor made in Samsung’s 14nm FinFET process, a Samsung executive talked about the company’s road to 14nm. The milestone was a huge one for the Korean giant, beating rival TSMC to become the second chip maker after Intel to ship a 14nm FinFET chip.

    “I think competition is healthy, it pushes everyone to achieve their limits – either from a technology angle, execution, or the ability to deliver service levels,” Kelvin Low, senior director of foundry marketing for Samsung Semiconductor, told EE Times.

    Low would not comment on production volumes, yields, or the number of devices using Samsung’s 14nm process. Instead, he outlined the applications using 14nm and described the foundry’s FinFET strategy.

    FinFETs promise lower leakage and lower power, which is important in handsets such as the Galaxy S6 and for data centers that want to increase their GHz/Watt performance.

    Samsung’s 14nm chips are in production in Korea and Austin, Texas, though Low would not comment where certain chips are made.

    Reply
12. April 17, 2015 at 8:09 am

    Tomi Engdahl says:

    NFC Tags Check Food Freshness
    http://www.eetimes.com/document.asp?doc_id=1326372&amp;

    In December last year, researchers at the Massachusetts Institute of Technology (MIT) had designed simple gas sensors relying on nanotubes-based chemiresistors (electrical circuits whose resistance changes when exposed to a particular chemical).

    In their implementation, the carbon nanotubes were chemically modified so that their ability to carry an electric current changed in the presence of a particular gas. This chemiresistive property was then integrated into the powering circuit of commercial near-field communication (NFC) tags.

    Reply
13. April 17, 2015 at 8:12 am

    Tomi Engdahl says:

    Improving Touchscreen Products Using Silver Nanowire Conductors
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1326365&amp;

    The use of silver nanowires is cost-effectively accelerating the transition to next-generation flexible and wearable devices and — beyond that — to products we can only imagine.

    Who’s using silver nanowire?
    You will likely recognize some of the names that are already using silver nanowire-based touchscreens because they’ve been adopted as the transparent-conductor-of-choice by leading industry heavyweights, including Hitachi, LG, TPK, Nissha, 3M, Okura, and many others.

    Wearability = flexibility

    The flexibility of silver nanowires — along with their transmission and conductive properties — are enablers for an array of existing and forthcoming electronic displays and consumer wearables, as well as IoT inventions for as-yet unimagined applications.

    Brighter, stronger, more sensitive, lower power…
    There are several factors that make silver nanowires a material ideally suited to new products for the “touch age.” Let’s start by noting that touchscreens should be thin, light, visible in various ambient light conditions, highly responsive, and — perhaps most importantly — lower-cost.

    The most popular touchscreen technology is projected capacitance, or pro-cap.

    highly conductive transparent conductors with high transmission ability. Silver nanowire delivers on all counts.

    Transparent conductors may also be applied as electrodes for LCD, OLED, thin film photovoltaic cells, shutters for 3D TVs, and applications that are yet to be imagined. In general, the requirements are the same. This means higher conductivity, better light transmission, and no side-effects like moiré or pattern visibility, along with the ability to support flexible touch screens. OEM systems companies naturally want all of these features at less cost than traditional technologies.

    …and thinner!
    Single-layer touch sensors are in demand for tablets, mobile phones, and — doubtless — whatever comes next. A single-layer approach offers notably lower cost because there are fewer layers of adhesives and conductors in the touchscreen stack.

    Less to make
    There’s more good news. Overall, silver nanowire-based touchscreens range from slightly less to significantly lower cost than equivalent ITO film-based solutions. The manufacturing process doesn’t use chemicals and there are no waste disposal problems, so it’s a greener way of making new touchscreens.

    Reply
14. April 17, 2015 at 11:20 am

    Tomi Engdahl says:

    One in seven of the IC chip is from contract manufacturers lines

    Circuits contract manufacturing is growing rapidly, because most of the semiconductor in the house can no longer afford to build factories for the manufacture of chips. Taiwanese TSMC is in this race class of its own: its market share is already 53.7 per cent. Contract manufacturers produce one-seventh of microcircuits.

    TSMC’s net sales grew last year by more than 25 per cent to 25.2 billion dollars.

    The second-largest manufacturer of foundry is also in Taiwan – Globalfoundries with turnover last year was $ 4.6 billion and a market share of just under 10 per cent.

    Samsung is one of contract manufacturing are rapidly increasing business. Last year, its net sales amounted to 2.4 billion dollars (745 million was traditional contract manufacturing, but most from Apple processors).

    A total of microcircuits contract manufacturing market last year were $ 46.9 billion in size. Size of the market grew last year by 16 per cent.

    Semiconductors total market last year were a size nearly 340 billion dollars.

    Source: http://www.etn.fi/index.php?option=com_content&view=article&id=2702:joka-seitsemas-mikropiiri-sopimusvalmistajien-linjoilta&catid=13&Itemid=101

    Reply
15. April 17, 2015 at 2:18 pm

    Tomi Engdahl says:

    Flash dead end is deferred by TLC and 3D
    Behold, data centre bods, the magical power of three
    http://www.theregister.co.uk/2015/04/17/flash_deadend_deferral_with_tlc_and_3d/

    The arrival of a flash dead-end is being delayed by two technologies, both involving the number three – three-level cell (TLC) flash and three-dimensional (3D) flash – with the combination promising much higher flash chip capacities.

    As ever with semi-conductor technology, users want more data in the same space and faster access to it too, please.

    Progress means making devices faster and denser: getting more transistors in flash dies, and hence more cells, with no access time penalty or shortened working life.

    Flash data access can be speeded up by using PCIe NVMe interfaces, with several lanes active simultaneously, and so going faster than SAS or SATA disk-based interfaces.

    It can also be hastened by putting the flash in memory DIMM slots, as SanDisk’s ULLtraDIMM product does using Diablo Technologies’ intellectual property. However Diablo and SanDisk are involved in a legal case involving NetList alleging that they are using its intellectual property improperly. Until that is resolved DIMM flash technology is in hibernation.

    But the core issue is flash chip capacity: how can we get denser chips and hence larger capacity SSDs?

    With flash memory this has been achieved by adding a bit to the original single-level cell (SLC) flash, and by making the process geometry smaller.

    It is currently in the 1X area, meaning cell sizes in the range of 19nm to 10nm.

    Smaller cells don’t last as long as larger cells as they sustain fewer write cycles. With 2-layer cell technology, called MLC, the cell stores two bits through two levels of charge and this adds to the process shrink problem.

    It has been managed successfully with better error detection and the use of digital signal processing techniques by the flash controllers so weaker signals can be processed successfully with 2X-class flash (29-20nm cell geometry).

    Shrink the process size to the 1X area, however, and the problems get worse the further below the 19nm level we get. Go below 10nm and they look insoluble. You can’t defeat physics.

    TLC technology has been around for some years. It gives an immediate 50 per cent increase in capacity over MLC flash

    A serious problem is detecting the level of charge in the cell. What happens is that there are eight possible levels, double the four levels of MLC flash, which is double the two levels of SLC flash.

    SLC flash can have two levels of charge, or states, equivalent to binary 1 or 0. MLC adds a second bit to the SLC cell, meaning each SLC state can have two additional states, 0 or 1, giving us four states in total.

    TLC flash goes one stage further, adding a third bit and therefore two additional states for each MLC state.

    The main flash foundry operators, Intel-Micron, Samsung and SanDisk-Toshiba, are all active in TLC and 3D NAND developments.

    Reply
16. April 20, 2015 at 7:01 am

    Tomi Engdahl says:

    Qualcomm to Leverage Monolithic 3D for Smartphones
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1326383&amp;

    Qualcomm is looking to leverage Monolithic 3D IC technology to win market share in the 8 billion dollar smart phone market.

    Starting as soon as 2016 Qualcomm is looking to leverage Monolithic 3D IC technology to win market share in the 8 billion dollar smart phone market, said Karim Arabi, vice president of engineering at Qualcomm

    Quoting: “Our 3D VLSI technology, which we call 3DV, enables die size to be shrunk in half, while simultaneously increasing yields,”…“The final advantage of 3DV chips,” according to Arabi, “is that you only need to use the most expensive and latest node technology on the bottom layer. For instance, the bottom layer housing the CPU, GPU and other high-speed devices can be fabricated at 10-to-14 nanometer, whereas the higher layers housing less critical functions can be fabricated at a less expensive relaxed node of, say, 28-nanometers.”

    Reply
17. April 20, 2015 at 7:02 am

    Tomi Engdahl says:

    TSMC Cuts Capex by $1 Billion
    Cites faster conversion to 16nm
    http://www.eetimes.com/document.asp?doc_id=1326378&amp;

    aiwan Semiconductor Manufacturing Co. (TSMC), the world’s largest chip foundry, cut its planned capital expenditure for this year by $1 billion, citing improvements in capital efficiency and a faster-than-expected migration to its leading-edge 16nm process technology.

    The company, which in January weighed in with the chip industry’s largest planned layout for expansion this year, said at an announcement of its first-quarter results today that its revised 2015 capex will fall within a range of $10.5 billion and $11 billion.

    TSMC’s slashed spending plan follows Intel, which earlier this week pared about $1.3 billion from its 2015 capex budget to a revised $8.7 billion. IC Insights earlier this year forecast that Samsung would take the number-two spot with a capex budget of $11.3 billion. The downward revisions come with a weaker outlook for the global economy.

    Reply
18. April 20, 2015 at 7:04 am

    Tomi Engdahl says:

    Paper Memory Ready to Roll
    http://www.eetimes.com/document.asp?doc_id=1326381&amp;

    Researchers at the Finish VTT Technical Research Centre have demonstrated they could print memory circuits directly on paper, using simple roll-to-roll printing techniques with a particular mix of commercially available metallic inks.

    The researchers envisage their cheap paper memories to be used in applications such as sensor data recording, product originality marking, playing cards, interactive packaging and product information cards.

    The write-once-read-many (WORM) memories can be fabricated directly on the product or packaging using flexographic or inkjet printing machines, common in the packaging industry. Each writable memory bit, measuring about 0.2×0.3mm each in the researchers’ experiments, consist of a mix of two commercially available silver nanoparticle inks, dried after a regular R2R printing process of the actual bits and their associated writing/reading electrodes.

    Before writing, each bit is in the 1 state of high resistance. Writing a bit is performed by applying a low voltage (under 10V) across the bit, which in effect sinters adjacent silver nanoparticles and creates a path of least electrical resistance, hence turning the memory bit from a high resistivity ’0 state to a low resistivity 1 state.

    This sintering step is non-reversible

    The VTT lab was able to print a roll length of 150m containing more than 10 000 printed WORM memory banks on a 125um thin heat stabilized PET substrate, but in prior research, it had demonstrated the sintering capability of the memory bits on paper.

    Reply
19. April 20, 2015 at 7:07 am

    Tomi Engdahl says:

    Odds of Success of Mie Fujitsu, Japan’s Pure-Play Foundry
    Born out of Fujitsu’s chip business restructuring
    http://www.eetimes.com/document.asp?doc_id=1326373&amp;

    Mie Fujitsu Semiconductor is a four-month-old foundry company whose existence defies the declining trend for semiconductor manufacturing fabs. Hence, its exceptionally low profile.

    Mie Fujitsu, a 300-mm wafer fab, is a byproduct of the drastic restructuring measures Fujitsu applied to its semiconductor business in February 2013. The Japanese company’s chip division, suffering from unpredictable revenue largely dependent on fluctuations in demand, belatedly chose to go fabless.

    Burdened with numerous fixed costs and huge investment requirements, Fujitsu hoped to shed its manufacturing facilities.

    In August 2014, Fujitsu reversed course, deciding to turn the Mie fab into a new, independent foundry as a fully-owned subsidiary of Fujitsu Semiconductor.

    Later, Mie Fujitsu received 10 billion yen (about 84 million US dollars)* in total from Taiwanese foundry UMC, which helped the new foundry to kick- start operations.

    Nevertheless, there is an air of optimism at Mie Fujitsu Semiconductor.

    But seriously, how do they pull it off? Fujitsu Semiconductor’s capacity is miniscule — producing only 35,000 wafers per month — and it lags far behind its competitors’ investment in advanced fine process technology.

    Reply
20. April 20, 2015 at 8:59 am

    Tomi Engdahl says:

    No More Expiration Dates: MIT Is Developing Sensors To Detect When Food Is Going Bad
    http://www.fastcoexist.com/3045113/no-more-expiration-dates-mit-is-developing-sensors-to-detect-when-food-is-going-bad?partner=rss

    Forget dubious dates on containers. These sensors could tell when food is starting to rot and reduce food waste.

    One reason the U.S. wastes 40% of all the food it harvests is that we don’t have a good handle on the status of that food. As consumers, we rely largely on best before and use by dates that are notoriously conservative, and often flat-out wrong. Actual food decays at variable rates that aren’t reflected in that information.

    That’s why new types of food quality sensors could be so useful. If we can assess the actual state of each food item, that should allow us to make more informed choices and thus manage our fridges better. All things being equal, better information ought to lead to better decision-making.

    One promising technology: the sensors being developed by Timothy Swager’s lab at MIT. Swager is testing an electrically-conductive material that changes resistance in the presence of gases called amines, which are released when food starts going bad. By reading that resistance from outside a package, you can figure out how edible the food is inside.

    Reply
21. April 20, 2015 at 9:17 am

    Tomi Engdahl says:

    When Blueprints Were Really Blue: Is Engineering Becoming Less Satisfying?
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1326391&amp;

    Back then, working as a professional EE was like being a home hobbyist on steroids. Much of what we did, at least on the hardware side, wasn’t too far removed from what you might do tinkering at home in your garage.

    Flight simulators were all unique, depending on the particular avionics fit of the aircraft we were simulating. The control loading was overwhelmingly analog.

    Reply
22. April 20, 2015 at 10:07 am

    Tomi Engdahl says:

    5.5 µA Iq Boost Converter
    http://www.eeweb.com/company-news/texas_instruments/5.5-a-iq-boost-converter/

    The TPS61222 is a boost converter with low input voltage and has a 5.5 µA quiescent current. The device provides a power-supply solution for products powered by either a single-cell, two-cell, or three-cell alkaline, NiCd or NiMH, or one-cell Li-Ion or Li-polymer battery.

    The device is offered in a 6-pin SC-70 package (DCK) measuring 2 mm × 2 mm

    Up to 95% Efficiency at Typical Operating Conditions
    Operating Input Voltage from 0.7 V to 5.5 V
    Adjustable Output Voltage from 1.8 V to 6 V

    TPS61222 (ACTIVE)
    Tiny Low Input Voltage Boost Converter
    http://www.ti.com/product/tps61222

    Reply
23. April 20, 2015 at 1:39 pm

    Tomi Engdahl says:

    Internet of Things: A Fancy Way of Saying “More Embedded Linux, Please”
    http://intelligentsystemssource.com/internet-of-things-a-fancy-way-of-saying-more-embedded-linux-please/

    Spanning server to deployed device, configurations of Linux have reached levels of flexibility, performance and real-time capability that enable it to function at all levels in the Internet of Things.

    To recap the past decade or so of embedded computing:: Linux is the dominant operating system in embedded devices and its use is increasing, while the deployment of custom or in-house operating systems has taken a sharp downward turn, according to the 2014 Embedded Market Study by UMB Tech. This remains true, even when taking Android and all of its associated “Linux or not” questions out of the equation, with the next contenders being Windows, custom OSes, and RTOS as a distant fourth.

    Why is Linux so dominant? It’s not the smallest, fastest, or lowest energy OS. Memory requirements ranging from 2 MB to 512 MB preclude its use on many smaller devices. A custom OS that has been pared down and optimized for a given microprocessor or System-on-Chip (SoC) will probably deliver better performance.

    Embedded Linux Keeps Growing Amid IoT Disruption, Says Study
    https://www.linux.com/news/embedded-mobile/mobile-linux/818011-embedded-linux-keeps-growing-amid-iot-disruption-says-study

    A new VDC Research study projects that Linux and Android will continue to increase embedded market share through 2017 while Windows and commercial real-time operating systems (RTOSes) will lose ground. The study suggests that the fast growth of IoT is accelerating the move toward open source Linux.

    “Open source, freely, and/or publicly available” Linux will grow from 56.2 percent share of embedded unit shipments in 2012 to 64.7 percent in 2017, according to VDC’s “The Global Market for IoT and Embedded Operating Systems.” That represents a CAGR of 16.7 percent for open Linux, says VDC.

    The surging open source Linux growth more than compensates for the decline from 6.3 percent to 5.0 percent in commercial Linux shipments. In 2013, there were more than 1.7 times more shipments of embedded devices based on open source OSes, including free RTOSes, than for commercial platforms, says VDC.

    “Linux, in particular, continues to grow its developer base and support from leading vendors,” says Daniel Mandell, an analyst at VDC Research. “Linux is the primary OS for new connected device classes such as IoT gateways.”

    Reply
24. April 20, 2015 at 1:39 pm

    Tomi Engdahl says:

    Report: Linux takes leading role in IoT-obsessed market
    http://linuxgizmos.com/linux-takes-leading-role-in-iot-obsessed-market/

    Spurred on by IoT, open source Linux will grow from a 56.2 percent share of embedded device shipments in 2012 to 64.7 percent in 2017, says VDC Research.

    Earlier this month, VDC Research released a report on the embedded OS market that says embedded Linux is growing in adoption in a market increasingly obsessed with the Internet of Things. The popularity of open source as well as the need for more advanced wireless and security stacks have helped Linux gain share from Microsoft’s Windows Embedded and from real-time operating systems (RTOSes), according to VDC’s “The Global Market for IoT and Embedded Operating Systems.”

    Reply
25. April 20, 2015 at 2:02 pm

    Tomi Engdahl says:

    Infineon confirms dual-strand approach to GaN product portfolio
    http://www.edn-europe.com/en/infineon-confirms-dual-strand-approach-to-gan-product-portfolio.html?cmp_id=7&news_id=10006027&vID=1323#.VTUGqpNLZ4A

    Infineon which, by internal development and acquisitions, now has a range of power device architectures available to it, has confirmed it intends to continue to offer multiple options and has disclosed plans for a portfolio of energy-efficient enhancement mode and cascode configuration GaN-on-Silicon transistors.

    The company has announced the expansion of its Gallium Nitride (GaN)-on-Silicon technology and product portfolio; Infineon now offers both enhancement mode (normally-off transistor) and cascode configuration (depletion mode, normally on with companion silicon driver transistor) GaN-based platforms.

    Reply
26. April 21, 2015 at 8:13 am

    Tomi Engdahl says:

    Is Formal Verification Artificial Intelligence?
    http://www.eetimes.com/author.asp?section_id=31&doc_id=1326394&amp;

    Artificial intelligence or not, formal verification is a technology that has become a must-have in the modern verification flow.

    I recently started reading a book, Super Intelligence: Paths, Dangers, Strategies, by Nick Bostrom. I was surprised to find the following text in the chapter describing state-of-the-art artificial intelligence (AI) applications:

    Theorem-proving and equation-solving are by now so well established that they are hardly regarded as AI any more. Equation solvers are included in scientific computing programs such as Mathematica. Formal verification methods, including automated theorem provers, are routinely used by chip manufacturers to verify the behavior of circuit designs prior to production.

    Reply
27. April 21, 2015 at 8:13 am

    Tomi Engdahl says:

    Resistive RAM Memory is Finally Here
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1326351&amp;

    Resistive RAM’s low power consumption and small cell area make it a no-brainer for non-volatile memory.

    The end of lithographic scaling of DRAM and NAND somewhere between 16nm and sub-10nm has been a popular call for the last few years, with many touting the emergence of new memory types including phase change RAM (PCRAM), ferro-electric RAM (FRAM), magneto-resistive RAM (MRAM), and more recently, resistance RAM as replacements (ReRAM and CBRAM).

    Over the years TechInsights has analyzed PCRAM from Numonyx and Samsung, FRAM from Ramtron and MRAM from Freescale and its spin-off Everspin. These devices have found niche applications, but are not seen as replacements for NAND or DRAM due to scaling or power consumption constraints. Resistive RAM, on the other hand, features low power consumption and a small cell area; both compelling reasons for their adoption as a non-volatile memory.

    Reply
28. April 21, 2015 at 8:14 am

    Tomi Engdahl says:

    The GaN Era Approaches
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1326389&amp;

    Gallium nitride possesses many characteristics that will allow production of power transistors that outperform silicon devices.

    Exacting demands are now placed upon the manufacturers of consumer electronics goods, as they strive to provide their customer base with more streamlined, sleeker products that can sustain longer periods between battery recharges. Likewise, legislative guidelines are pushing datacenters to become more power efficient and support an intensified concentration of electronics hardware.

    These issues, among others, mean that the industry is compelled to adopt new semiconductor materials, so that components can be produced which have higher power conversion efficiencies, faster switching speeds and greater power densities.

    Gallium nitride (GaN) is now coming to the fore, possessing many characteristics that will allow production of power transistors which outperform Si devices. GaN has wider band gap and a considerably higher critical electric field, as well as very high electron mobility. These advantages offer power electronics engineers the opportunity for superior power density since GaN offers the same level of performance as Si while fitting into a much more compact area.

    Reply
29. April 21, 2015 at 8:47 am

    Tomi Engdahl says:

    Synopsys to buy the Oulu Codenomicon

    Electronic design tools for developing the American Synopsys is known as one of the three major EDA-house. Now it buys from Oulu Codenomicon.

    Commercial describes EDA houses need to improve its offering of software testing tool. The company is the acquisition acquired Coverity platform, which Codenomicon tools will be integrated.

    Source: http://www.etn.fi/index.php?option=com_content&view=article&id=2713:synopsys-ostaa-oululaisen-codenomiconin&catid=13&Itemid=101

    Reply
30. April 21, 2015 at 8:54 am

    Tomi Engdahl says:

    Mountain of electrical waste reaches new peak
    http://phys.org/news/2015-04-mountain-electrical-peak.html

    A record amount of electrical and electronic waste hit the rubbish tips in 2014, with the biggest per-capita tallies in countries that pride themselves on environmental consciousness, a report said Sunday.

    Last year, 41.8 million tonnes of so-called e-waste—mostly fridges, washing machines and other domestic appliances at the end of their life—was dumped, it said.

    That’s the equivalent of 1.15 million heavy trucks, forming a line 23,000 kilometres (14,300 miles) long, according to the report, compiled by the United Nations University, the UN’s educational and research branch.

    Less than one-sixth of all e-waste was properly recycled, it said.

    Almost 60 percent of e-waste by weight came from large and small kitchen, bathroom and laundry appliances.

    Read more at: http://phys.org/news/2015-04-mountain-electrical-peak.html#jCp

    Reply
31. April 21, 2015 at 9:22 am

    Tomi Engdahl says:

    Exclusive: Qualcomm to Use Samsung’s Foundries for Its Next High-End Chip
    http://recode.net/2015/04/20/exclusive-qualcomm-to-use-samsungs-foundries-for-its-next-high-end-chip/

    Breaking from past practice, Qualcomm plans to have its next-generation Snapdragon 820 processor manufactured at Samsung’s chip-making plants, according to sources familiar with Qualcomm’s roadmap and Samsung’s foundry operations.

    Historically, Qualcomm has manufactured its leading-edge chips largely at contract chip maker Taiwan Semiconductor Manufacturing Co. as well as other foundries. However, Samsung has had an edge over TSMC and other chip plants because it is cranking out chips using thinner 14-nanometer wiring, compared with 20-nanometer transistors at TSMC. All other things being equal, thinner wires mean smaller and less costly chips as well as better battery performance.

    Reply
32. April 21, 2015 at 9:36 am

    Tomi Engdahl says:

    Flash dead end is deferred by TLC and 3D
    Behold, data centre bods, the magical power of three
    http://www.theregister.co.uk/2015/04/21/flash_dead_end_is_deferred_by_tlc_and_3d/

    The arrival of a flash dead-end is being delayed by two technologies, both involving the number three – three-level cell (TLC) flash and three-dimensional (3D) flash – with the combination promising much higher flash chip capacities.

    As ever with semi-conductor technology, users want more data in the same space and faster access to it too, please.

    Progress means making devices faster and denser: getting more transistors in flash dies, and hence more cells, with no access time penalty or shortened working life.

    Flash data access can be speeded up by using PCIe NVMe interfaces, with several lanes active simultaneously, and so going faster than SAS or SATA disk-based interfaces.

    But the core issue is flash chip capacity: how can we get denser chips and hence larger capacity SSDs?

    With flash memory this has been achieved by adding a bit to the original single-level cell (SLC) flash, and by making the process geometry smaller.

    It is currently in the 1X area, meaning cell sizes in the range of 19nm to 10nm.

    Smaller cells don’t last as long as larger cells as they sustain fewer write cycles. With 2-layer cell technology, called MLC, the cell stores two bits through two levels of charge and this adds to the process shrink problem.

    It has been managed successfully with better error detection and the use of digital signal processing techniques by the flash controllers so weaker signals can be processed successfully with 2X-class flash (29-20nm cell geometry).

    You can have another bite at the same cherry by layering existing planar – 2D – flash dies in a 3D way, stacking them one above the other to create much higher-capacity chips.

    TLC technology has been around for some years. It gives an immediate 50 per cent increase in capacity over MLC flash – so why isn’t it popular in enterprise flash storage products?

    A serious problem is detecting the level of charge in the cell. What happens is that there are eight possible levels, double the four levels of MLC flash, which is double the two levels of SLC flash.

    Reply
33. April 21, 2015 at 12:24 pm

    Tomi Engdahl says:

    Old Marconi Patent Inspires Tiny New Gigahertz Antenna
    http://science.slashdot.org/story/15/04/20/1755240/old-marconi-patent-inspires-tiny-new-gigahertz-antenna

    Gehan Amaratunga and a group of engineers in England noted that the Guglielmo Marconi’s famous British patent application from 1900 had an interesting and little noticed detail.

    New Theory Leads to Gigahertz Antenna on a Chip
    http://spectrum.ieee.org/tech-talk/telecom/wireless/gigahertz-antenna-on-a-chip

    It’s well understood that a dipole or monopole metal antenna’s length has to be at least one eighth of the wavelength of the wireless signal in order to transmit enough power. For transmission in the gigahertz range, where most mobile communication takes place, wavelengths between 15 and 30 centimeters had set a limit for miniaturization of transmitter and receiver antennas even as the silicon chips on which they must be integrated got ever smaller.

    Now researchers have found a way to reduce the size of GHz antennas by modifying an existing technique, the use of antennas made from a dielectric or insulating material instead of a conductor. In a proof of concept experiment, researchers at the department of engineering at the University of Cambridge and at the National Physical Laboratory in Teddington, Middlesex, UK, have shown that they can reduce the size of a GHz antenna without significant transmission loss by using dielectric materials as the radio wave emitting material. They reported the results earlier this month in Physical Review Letters.

    The UK team argues that the concept of symmetry breaking explains why dielectric matter can transmits electromagnetic waves. “Until now this was not well understood,”

    Dielectric antennas are already in use, but they are too bulky for on-chip use. Instead of the dielectric materials in use today, Sinha and his colleagues chose a piezoelectric film.

    Reply
34. April 22, 2015 at 7:15 am

    Tomi Engdahl says:

    A single misplaced atom can cause a system failure
    http://www.edn.com/design/test-and-measurement/4439223/A-single-misplaced-atom-can-cause-a-system-failure?_mc=NL_EDN_EDT_EDN_today_20150421&cid=NL_EDN_EDT_EDN_today_20150421&&elq=77b0cfead7a0444a94b6c51ef69ad93f&elqCampaignId=22642&elqaid=25466&elqat=1&elqTrackId=16c26ce2afe04f5bbd108f1cd95da1e2

    As semiconductor processes let manufacturers produce more compact, lower-power devices created from smaller structures, finding and fixing problems has become increasingly challenging. A device that might appear to have been correctly manufactured can still show performance problems thanks to defects arising from a single atom being in the wrong place. Determining the root cause of these failures requires a disciplined and systematic analytical process, along with sophisticated tools for testing and visualizing the behaviors and other characteristics of sample devices.

    Reply
35. April 22, 2015 at 7:35 am

    Tomi Engdahl says:

    TI Obsoletes FPGA
    Mixes ARM cores with DSPs and programmable logic
    http://www.eetimes.com/document.asp?doc_id=1326403&amp;

    Texas Instruments (TI) — king of the DSP — is at it again, this time targeting the FPGA market with a 9 processor jack-of-all-trades device capable of radically downsizing mammoth avionic, military, test and measurement and medical instruments — from backpack radars to portable magnetic resonance instruments (MRIs).

    According to TI, the Keystone-II (66AK2L06) solution allows devices using it to be 66 percent smaller, consume 60 percent less power, cost 50 percent less and are 3-times faster to market than using an FPGA solution.

    “Our newest Keystone II system-on-chip [SoC] has two ARM’s Cortex A15 MPCore processors, four 1.2 GHz C66x DSPs [digital signal processors) and four programmable accelerators,”

    That spells significant system-level savings for high-speed data acquisition when paired with 4-lanes of JEDEC-compatible input/output (I/O) running at 7.3 Gbits/sec per lane (JESD204B).

    Reply
36. April 22, 2015 at 7:36 am

    Tomi Engdahl says:

    WSTS Marks America Up for 2015 Boom
    http://www.eetimes.com/document.asp?doc_id=1326404&amp;

    The market for semiconductors in the Americas region will grow by 15 percent in 2015, according to a revised estimate from the World Semiconductor Trade Statistics (WSTS) organization.

    This, together with strength in the market in the Asia-Pacific region, has led WSTS to increase its annual growth estimate worldwide for 2015. WSTS now forecasts the market for semiconductors in the Americas region will enjoy 15.0 percent annual growth in 2015, a mark up from 5.3 percent growth figure given in December 2014 (see Chip market forecast raised for 2014, 2015).

    Forecasts for the other main geographic regions have also been altered with a more pessimistic view taken for Europe and Japan and a higher growth figure plugged in for the Asia Pacific region. Europe has been marked down to a contraction in dollar terms of 2 percent compared with growth of 1.5 percent.

    As a result worldwide semiconductor market growth has been marked up to 4.9 percent the previous forecast of 3.4 percent. The worldwide estimate for 2016 growth has not been changed and remains at 3.1 percent.

    Reply
37. April 22, 2015 at 7:38 am

    Tomi Engdahl says:

    Athena Security IPs Designed to Mend Holes in SoCs
    Zooming in on differential power analysis
    http://www.eetimes.com/document.asp?doc_id=1326395&amp;

    The need to protect connected systems — cars, mobile phones, smart grids, connected factories and any other IoT devices — by using security chips with crypto keys is growing rapidly, while not clearly answering a critical question: How do we know if the security chips designed into such connected systems aren’t leaking key information?

    The Athena Group, Inc. (Gainesville, Florida) hopes to answer the $64 billion question on Monday (April 20) by rolling out a portfolio of security IP cores with side-channel attack countermeasures, based on advanced differential power analysis (DPA) countermeasure approaches pioneered by the Rambus Cryptography Research Division.

    It’s widely known that cyber-attackers can exploit an extra source –from timing information, power consumption or electromagnetic leaks of chips — to break a cryptosystem.

    DPA — which involves statistically analyzing power consumption measurements from a cryptosystem — is believed to be one of the biggest challenges for designers of countermeasures. “DPA attacks are extremely difficult to detect,

    DPA-resistant IP cores for ASICs and FPGAs
    Athena is seeking to level the playing field by making available “a full set of DPA-resistant off-the-shelf and custom IP core solutions — for the first time — for ASIC targets as well as FPGA devices from Microsemi, Altera, and Xilinx,” according to the company.

    Reply
38. April 22, 2015 at 12:06 pm

    Tomi Engdahl says:

    Intel’s 10nm Secrets Predicted
    Quantum well FETs, germanium, InGaAs in mix
    http://www.eetimes.com/document.asp?doc_id=1326410

    A semiconductor analyst is making a bold and detailed prediction about the process technology Intel Corp. will use for its next two generations. If he is right, the world’s largest chip maker is set to leapfrog the industry once again.

    Intel will use quantum well FETs starting with its 10nm process, said David Kanter in an analysis posted on his Real World Technologies Web site. The new transistor structures will use two new materials – indium gallium arsenide (InGaAs) for n-type transistors and strained germanium for p-type devices, he said.

    If correct, Intel could gain a capability as early as 2016 to produce 10nm transistors as much as 200 millivolts lower in power consumption than the rest of the industry. Kanter expects other chip makers will not be able to catch up with the techniques until their 7nm node, at least two years later.

    “The question is not will Intel do quantum well FETs, the question is will it be at 10 or 7nm,” he said.

    Reply
39. April 23, 2015 at 6:14 am

    Tomi Engdahl says:

    Linear Technology knows how to make a Power uModule
    http://www.edn.com/electronics-products/electronic-product-reviews/other/4439256/Linear-Technology-knows-how-to-make-a-Power-uModule?_mc=NL_EDN_EDT_EDN_today_20150422&cid=NL_EDN_EDT_EDN_today_20150422&elq=093b2bc92bf542bda570010c8f9b9706&elqCampaignId=22665&elqaid=25495&elqat=1&elqTrackId=f5c880d2f99a4dceb3d9ed2635021845

    There is an art to designing a power supply that is fully enclosed in a compact molded plastic package. Not only do you have to effectively get the heat out but you need to pack in a DC/DC controller, magnetics, power MOSFETs and assorted passive components—Oh yeah, and then include an integrated heat sink (In the cases ofLTM4620, LTM4620A and LTM4637 step-down uModule regulators). And it can’t be big (especially if you are calling it a uModule!)

    Well, Linear Technology introduced a new family of buck-boost µModule® (micromodule) regulators recently, the LTM8055 and LTM8056. These devices regulate output voltages equal to, greater or less than the input voltage.

    They are able to design the entire regulator in a 15mm x 15mm x 4.92mm BGA package, including the inductor, DC/DC regulator, MOSFETs and the supporting passive components.

    Reply
40. April 23, 2015 at 6:15 am

    Tomi Engdahl says:

    Designing your first PXI test system? Start inside out.
    http://www.edn.com/electronics-blogs/test-cafe/4439174/Designing-your-first-PXI-test-system–Start-inside-out-?_mc=NL_EDN_EDT_EDN_today_20150422&cid=NL_EDN_EDT_EDN_today_20150422&elq=093b2bc92bf542bda570010c8f9b9706&elqCampaignId=22665&elqaid=25495&elqat=1&elqTrackId=0e639897381a46368975fc7bb4968e42

    A logical method might be to choose a chassis and fill it up with modules. You’d then add a controller and software. While this may be logical for the actual integration, it is not the optimal process for choosing products or designing the system. You should design the system starting with the modules and software first, and then choose the controller and chassis.

    The specific steps are:
    • Choosing modules and software
    • Choosing the controller
    • Choosing the chassis
    • Final iteration and integration

    Multichannel RF/analog recorder stores up to 10 Tbytes
    http://www.edn.com/electronics-products/other/4439227/Multichannel-RF-analog-recorder-stores-up-to-10-Tbytes?_mc=NL_EDN_EDT_EDN_today_20150422&cid=NL_EDN_EDT_EDN_today_20150422&elq=093b2bc92bf542bda570010c8f9b9706&elqCampaignId=22665&elqaid=25495&elqat=1&elqTrackId=bb8e09eb65d248deb92d92f803143c8d

    Used for recording extremely long RF/analog waveforms, the TERAQC14 data-acquisition system from Ultraview stores up to 10 Tbytes of wideband content acquired on one to four channels, concurrently triggered by either an internal or external start signal. This 14-bit, 400-Msample/s system can be used to observe waveforms with high signal-to-noise ratio for timespans of up to two hours with the 10-Tbyte model in such applications as signal intelligence, radar, missile testing, communication systems, and antenna testing.

    Reply
41. April 23, 2015 at 6:25 am

    Tomi Engdahl says:

    New Fabrication Technique Prints Silicon on Paper
    http://www.medicaldesignbriefs.com/component/content/article/1104-mdb/news/21970

    Using a single laser pulse, a group of researchers at Delft University of Technology in The Netherlands has devised a method that allows silicon, in the polycrystalline form used in circuitry, to be produced directly on a paper substrate from liquid silicon ink. The process can be expanded to create biomedical sensors and stretchable electronics.

    The capacity for printing silicon ink onto substrates has existed for some time, but has required a 350° C thermal annealing step—far too hot for many flexible surfaces. The researchers’ new method bypasses the thermal annealing and transforms the liquid silicon directly into polysilicon.

    Reply
42. April 23, 2015 at 6:27 am

    Tomi Engdahl says:

    Alternative PCB fabrication tools
    http://www.edn.com/design/pc-board/4439221/Alternative-PCB-fabrication-tools?_mc=NL_EDN_EDT_EDN_today_20150422&cid=NL_EDN_EDT_EDN_today_20150422&elq=093b2bc92bf542bda570010c8f9b9706&elqCampaignId=22665&elqaid=25495&elqat=1&elqTrackId=10dbb38a5b6348cfbc020c1a7c340567

    Designing and producing your own circuit board can be daunting to say the least. Most of us turn to tried and true processes to get them made. Just soldering up perf boards and shopping out PCB fabrication are both beyond time consuming. Of course, we want professional-grade prototypes at every stage of the dev process. It’s certainly getting easier now, with a plethora of new alternative PCB fabrication tools and services available.

    Needless to say, it doesn’t have to be an ordeal to DIY your own board, and plenty of alternative methods are out there that can simplify the process. In this roundup, we feature some of the prominent methods of making your own circuit boards that will help to alleviate some of the issues that entail the manufacturing process.

    Alternative PCB Fabrication Methods: Tools to Know
    http://www.eetimes.com/document.asp?doc_id=1326234

    Reply
43. April 23, 2015 at 9:36 am

    Tomi Engdahl says:

    Boffins laser print flexible transistors
    If you can’t stand the heat, turn down the temperature
    http://www.theregister.co.uk/2015/04/23/laser_printings_latest_twist_flexible_transistors/

    Printing transistors is nothing new – silicon fabrication is, after all, essentially a print process – but printing silicon ink onto flexible substrates is usually too a problem because there’s too much heat for the medium to handle.

    The difficult step is annealing, as that process turns a silicon ink into the polysilicon that forms the transistor. Pulling off that trick needs temperatures of around 350°, too much heat for substrates. So Delft University of Technology boffins have skipped the annealing step, instead firing a laser at the target for a few nanoseconds.

    “We coated liquid polysilane directly on paper by doctor-blading, or skimming it by a blade directly in an oxygen-free environment. Then we annealed the layer with an excimer-laser”

    Reply
44. April 23, 2015 at 12:25 pm

    Tomi Engdahl says:

    The chip giant Qualcomm’s second-quarter profit fell 46 percent. The biggest reason for this drop was a company in China ordered a big abuse of the monopoly of the use of a financial penalty.

    The allegations related to Qualcomm’s patent licensing practices, of which the Chinese authorities ordered the company to pay approximately over 900 million fine.

    The company was also forced to cut its net sales forecast for the current year. The reason was reported the loss of a key customer of Samsung’s high end districts, as well as the smartphone market, the more expensive the equipment the concentration of Samsung and Apple’s hands.

    Qualcomm lost part of Samsung’s orders, the Korean company chose to use in the most recent high end models it’s own Exynos circuits instead of Qualcomm’s Snapdragon chips.

    Qualcomm’s Snapdragon fresh 810 chip has been very successful despite the fact that the district reportedly suffered on overheating issues – it is used in high end models from LG, Sony, Xiaomi and HTC.

    Source: http://www.tivi.fi/Kaikki_uutiset/2015-04-23/Qualcommin-j%C3%A4ttisakko-Kiinassa-romautti-voitot—my%C3%B6s-Samsung-ahdistaa-3220448.html

    Reply
45. April 24, 2015 at 6:57 am

    Tomi Engdahl says:

    Verilog-AMS vs. SPICE view: An SoC verification comparison
    http://www.edn.com/design/integrated-circuit-design/4439239/Verilog-AMS-vs–SPICE-view–An-SoC-verification-comparison?_mc=NL_EDN_EDT_EDN_today_20150423&cid=NL_EDN_EDT_EDN_today_20150423&elq=30a2c06451154e4ab71672375e1d0744&elqCampaignId=22684&elqaid=25518&elqat=1&elqTrackId=80f2c920cedf416ea2c2bc75b1d1128d

    Dozens of analog and digital IP blocks are integrated into today’s SoCs. They contain multiple voltage domains that support several modes, like Standby, Low power, Reduced Clock Mode, etc. Additionally, there are several IPs used to interface with real world signals and external ICs. These include Data Converters, Clock sources like RC Oscillators and Crystal Oscillators, PLLs, etc.

    To achieve first pass success of such complex SoCs in silicon, a robust pre-silicon verification methodology needs to be implemented. The high level of analog IPs in these SoCs necessitates the need for Analog Mixed Signal (AMS) simulations that target the various features and modes being supported. In addition, many of these simulations also need to be run across process and temperature corners. This results in an AMS simulation count that runs into the hundreds. Defining and implementing these simulations accurately is a complex task. Moreover, simulating all of them is quite computationally intensive.

    Thus it is important to weigh the pros and cons of a Verilog/Verilog-AMS view versus a SPICE view for all the analog blocks and IPs within a SoC. This process needs to be carefully repeated for different AMS simulations, each targeting a different type of check.

    Reply
46. April 24, 2015 at 6:57 am

    Tomi Engdahl says:

    Kintex-7, SEU mitigation using an isolated-design flow, part 1
    http://www.edn.com/electronics-blogs/out-of-this-world-design/4439234/Kintex-7–SEU-mitigation-using-an-isolated-design-flow–part-1?_mc=NL_EDN_EDT_EDN_today_20150423&cid=NL_EDN_EDT_EDN_today_20150423&elq=30a2c06451154e4ab71672375e1d0744&elqCampaignId=22684&elqaid=25518&elqat=1&elqTrackId=344baf7ab5334fc8bd7c315befba4fdd

    Some of the latest, COTS, SRAM-based FPGAs are being baselined for small satellite and launcher applications offering significant performance, resource, power, and cost advantages over formally-qualified, QML devices. Ultra-deep-sub-micron parts have become intrinsically tolerant to high levels of total-dose exposure as thinner gate oxides trap less positive charge. Furthermore, a combination of lower-core voltages together with fabrication using epitaxial layers have made FPGAs less sensitive to latch-up effects.

    Smaller transistors and lower-operating supply rails have reduced the critical charge necessary to generate an SEU and increased gate densities have made FPGAs more sensitive to multi-bit errors from a single ion strike. For many space applications, not all of the logic and routing resources are required, opening up the possibility of enhancing SEU mitigation by replicating and isolating redundant blocks within the fabric.

    Although the reliability of FPGAs has improved considerably, Xilinx’s Isolation-Design Flow (IDF) offers fault-tolerant implementation of FPGAs, confining errors to a single module thus preventing their propagation.

    Reply
47. April 24, 2015 at 7:01 am

    Tomi Engdahl says:

    Home> Tools & Learning> Products> Product Brief
    EtherCAT slave controller integrates dual 10/100 PHYs
    http://www.edn.com/electronics-products/other/4439262/EtherCAT-slave-controller-integrates-dual-10-100-PHYs?_mc=NL_EDN_EDT_EDN_today_20150423&cid=NL_EDN_EDT_EDN_today_20150423&elq=30a2c06451154e4ab71672375e1d0744&elqCampaignId=22684&elqaid=25518&elqat=1&elqTrackId=f97ef980c01644d392136b6ee8c9bf4d

    Offered in 64-pin QFN and QFP-EP packages, the LAN9252 standalone EtherCAT slave controller from Microchip not only furnishes two 10/100-Mbps Ethernet transceivers that accommodate both fiber and copper cable, but also cable diagnostics and multiple interfaces, including 8/16-bit Host Bus and SPI/SQP communication interfaces. Standalone digital I/O gives designers the flexibility to select from a wide range of microcontrollers when implementing the real-time EtherCAT communications standard.

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48. April 24, 2015 at 7:09 am

    Tomi Engdahl says:

    Mobile apps provide manufacturing flexibility
    http://www.edn.com/electronics-blogs/now-hear-this/4439260/Mobile-apps-provide-manufacturing-flexibility?_mc=NL_EDN_EDT_EDN_analog_20150423&cid=NL_EDN_EDT_EDN_analog_20150423&elq=374b79fda156427da1edac6b6aa9eb52&elqCampaignId=22676&elqaid=25513&elqat=1&elqTrackId=bc54a65c0d23494da6f178bb4cfb2c45

    Supply chains are increasingly feeling pressure to improve their efficiency, effectiveness, productivity, and profitability to create a more agile supply chain. Increasing fast-paced global competition, as well as the need to automate processes and information flow, are spurring the adoption of mobile technology that automates business processes.

    According to a Ventana Research paper (PDF), the need for faster information and just-in-time processes that leads to automating business processes using mobile technology improves both manufacturing and customer service. OEMs are using mobile technologies to achieve a variety of benefits and activities including:

    Speeding up order processes by moving them closer to the actual interactions.
    Enabling quicker response to post-delivery customer requests for changes and streamlining fulfillment to enable faster billing.
    Making it possible for service personnel to update customer and product information while in field.
    Enabling easier compliance with industry-specific compliance requirements such as security validation of when and by whom specific actions were taken.
    Reducing waste and improving efficiency by automating notifications of failure found in inspections.
    Accessing information on material handling and inventory.
    Queuing up materials for timeliest use and replenishing low stocks efficiently.
    Tracking location of materials, in-process goods and inventory at every point and identifying demand signals as they occur in service interactions, or in the field.

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49. April 24, 2015 at 12:41 pm

    Tomi Engdahl says:

    Windows 10 is now slowing down of the semiconductor market

    Semiconductors sold this year, 354 billion dollars, Gartner predicts. The figure is four per cent higher than last year, but it could be even higher. The sector is suffering now too strong dollar, too high inventories, and the fact that the XP machines to update the PC market is over. Everyone is waiting for the forthcoming Windows 10 operating system.

    According to Gartner, strengthening of the dollar against other currencies has prompted manufacturers to think about strategies. In some markets, such as Europe, prices will be increased so that margins would remain unchanged.

    Source: http://www.etn.fi/index.php?option=com_content&view=article&id=2730:windows-10-hidastaa-nyt-puolijohdemarkkinoita&catid=13&Itemid=101

    Reply
50. April 24, 2015 at 12:42 pm

    Tomi Engdahl says:

    Samsung Busts TSMC’s ‘Monopoly,’ Analysts Say
    http://www.eetimes.com/document.asp?doc_id=1326409&amp;

    Samsung has broken the monopoly in leading-edge foundry services recently held by Taiwan Semiconductor Manufacturing Co. (TSMC), according to analysts who cover the chipmakers.

    TSMC, the world’s largest chip foundry, is likely to lose pricing power this year in its most profitable technology nodes ranging from 28nm to 16nm as key customers including Qualcomm, MediaTek, Apple, Nvidia and Marvel shift to Samsung and other TSMC competitors as second sources, the analysts said after TSMC posted its first-quarter 2015 financial results on April 16.

    “TSMC’s monopoly on leading edge has been broken thanks to Samsung’s successful ramp of 14nm with current yields exceeding 70%,” said Mehdi Hosseini, an analyst with Susquehanna International Group. “Samsung has effectively become as good as TSMC at 14nm while offering a much lower ASP per wafer.”

    Reply