Nowadays you can find many low-cost microcontroller devboards (starting from just few dollars/euros). More recently, we’ve seen ARM Cortex kits for $10-$50, the flowering of the whole Arduino ecosystem, and of course, the Raspberry Pi. It’s microcontroller heaven with very many dev boards available. You you want more performance, there is a wide selection of Linux friendly single board computers in around $35 to $200 range.
What do you want to try next after microcontroller dev boards? Maybe FPGA. A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing. FPGAs contain programmable logic components called “logic blocks”, and a hierarchy of reconfigurable interconnects that allow the blocks to be “wired together” – somewhat like many (changeable) logic gates that can be inter-wired in (many) different configurations. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR.
Those of us wanting a cheap “in” to the FPGA world have been less lucky than developers looking for microcontroller dev boards. FPGA boards under $100: Introduction article is indicting that the times, they are a changin’. Many FPGA devkits, from both chipmakers and third parties, have broken – or downright shattered – the $100 barrier, opening the door to low-cost FPGA prototyping, education, hobby projects, and so on. FPGA boards under $100: Introduction article offers a good overview of what is available.
Here are some interesting additions to the listed boards:
Hacklet 28 – Programmable Logic Hacks posting tells about Arduino-Compatible FPGA Shield. The shield features a Xilinx Spartan 6 FPGA and is available in The Hackaday Store. It has the needed regulators and level shifters. The price is $69.97. Not sure where to start? Check out Spartan-6 FPGA Hello World! that uses Xilinx’s free tool chain to getting a “hello world” led blinker running!
Hacklet 28 – Programmable Logic Hacks posting also mentions Chameleon. Chameleon is an Arduino compatible FPGA board with a Xilinx Spartan 3A FPGA on-board. The Chameleon Arduino-compatible shield board was designed to support two general application areas: (1) soft-core processors, and (2) intelligent serial communications interface.
Cheap FPGA-based HDMI Experimenting Board project is designing a (relatively) cheap little board for experimenting with HDMI using a Spartan-6 FPGA.
432 Comments
Tomi Engdahl says:
Apple II FPGA
https://hackaday.com/2017/10/10/apple-ii-fpga/
Stephen Edwards] had some time one Christmas. So he took a DE2 FPGA board and using VHDL built a pretty faithful reproduction of an Apple II+ computer. He took advantage of VHDL modules for the 6502 CPU and PS/2 keyboard, and focused more on the video hardware and disk emulation.
According to [Stephen], you can think of the Apple II as a video display that happens to have a computer in it. The master clock is a multiple of the color burst frequency, and the timing was all geared around video generation. [Stephen’s] implementation mimics the timing, although using more modern FPGA-appropriate methods.
The FPGA also has a read-only disk emulator. The image resides on an SD card and an SPI interface loads it into memory as required.
Apple2fpga: Reconstructing an Apple II+ on an FPGA
http://www.cs.columbia.edu/~sedwards/apple2fpga/
Tomi Engdahl says:
Hackaday Prize Entry: Programming FPGAs With Themselves
https://hackaday.com/2017/10/23/hackaday-prize-entry-programming-fpgas-with-themselves/
We don’t know if [Luke]’s entry to the Hackaday Prize is the killer project that will do it, but it is very neat. He’s designed a tiny FPGA development board using a Lattice iCE40 FPGA that’s able to program itself over USB. It’s small, it’s cheap, it’s easy to use, and there are working examples of FPGA development using this board.
TinyFPGA B-Series
https://hackaday.io/project/26848-tinyfpga-b-series
Low-cost, open-source FPGA boards in a tiny form factor with built-in USB, SPI flash, LDO, and MEMS clock.
Tomi Engdahl says:
The Coming of the Age of the Maker FPGA Board
https://blog.hackster.io/the-coming-of-the-age-of-the-maker-fpga-board-52a29572549e
Field-programmable gate arrays (FPGAs) are a very different to a regular microcontroller board. With a microcontroller you have control over is the software, the code that runs on the chip, but with an FPGA you start with a blank slate and design the circuit rather than write the code that runs on it. There is no processor to run software, at least not until you design it.
A number of FPGA boards targeting the maker market — like Alorium’s XLR8 for instance — are starting to appear, and among them is a new range of open source TinyFPGA boards.
Tomi Engdahl says:
FPGA Design From Top to Bottom
https://hackaday.com/2017/10/24/fpga-design-with-free-software/
[Roland Lutz] gave a talk about FPGA design using the free tools for Lattice devices at the MetaRheinMainChaosDays conference this year. You can see the video below. It’s a great introduction to FPGAs that covers both the lowest-level detail and some higher level insight. If you’re getting started with these FPGAs, this video is a must-see.
MRMCD2017 FPGA design with Free Software: The Lattice iCE40 HX1K/HX8K FPGA
https://www.youtube.com/watch?v=eWo7CINPu4w
Tomi Engdahl says:
Mid-range FPGAs offer optimised cost, lower power, better security
http://electronics-know-how.com/article/2559/mid-range-fpgas-offer-optimised-cost-lower-power-better-security
Electronics-know-how.com sat down with Microsemi’s Rick Goerner to talk about the PolarFire series of fifth-generation flash-based FPGAs.
While Microsemi has been in the programmable logic business for nearly 30 years, until recently the company was addressing only 35-40 percent of the field programmable gate array (FPGA) market. The launch of its mid-range PolarFire FPGAs, with up to treble the logic density, has increased the market Microsemi could serve by $1 billion.
“There were applications in the communications infrastructure, defense and industrial automation segments we previously couldn’t address, as we didn’t have sufficient density or gate count, fabric performance or things like10Gbps serial transceivers,” explains Rick Goerner, executive vice president of marketing and sales at Microsemi. “With PolarFire, we can address these applications, and compete for sockets of up to 500k logic elements.”
PolarFire is the company’s fifth generation of FPGAs on UMCs 28nm process node, and now offers higher density products with the same compelling power, security and cost advantages as previous families.
Tomi Engdahl says:
SFP optical modules: Legacy compatibility vs. improved performance
https://www.edn.com/design/components-and-packaging/4458966/SFP-optical-modules–Legacy-compatibility-vs–improved-performance
Tomi Engdahl says:
FPGA Metastability Solutions
https://hackaday.com/2017/10/25/fpga-metastability-solutions/
Gisselquist Technology recently posted a good blog article about metastability and common solutions. If you are trying to learn FPGAs, you’ll want to read it. If you know a lot about FPGAs already, you might still pick up some interesting tidbits in the post.
Don’t let the word metastability scare you. It is just a fancy way of saying that a flip flop can go crazy if the inputs are not stable for a certain amount of time before the clock edge and remain stable for a certain amount of time after the clock edge. These times are the setup and hold times, respectively.
Normally, your design tool will warn you about possible problems if you are using a single clock. However, any time your design generates a signal with one clock and then uses it somewhere with another clock, metastability is a possible problem. Even if you only have one clock, any inputs from the outside world that don’t reference your clock — or, perhaps, any clock at all — introduce the possibility of metastability.
Some Simple Clock-Domain Crossing Solutions
http://zipcpu.com/blog/2017/10/20/cdc.html
Tomi Engdahl says:
386 Too Much Horsepower? Try a 186, in an FPGA!
https://hackaday.com/2017/11/03/386-too-much-try-a-186-in-an-fpga/
Typically when we hear the term “System-on-Chip” bandied around, our mind jumps straight to modern ARM-based processors that drive smartphones and embedded devices around us. Coming a little bit more out of left field is [Jamie]’s 80186 core, that runs on Intel FPGAs.
[Jamie] has implemented the entire set of 80186 instructions in Verilog, and included some of the undocumented instructions too. This sort of attention to detail is important – real world parts don’t always meet the original specifications on paper, and programmers can come to rely on this. The key to compatibility is understanding how things perform in the real world, not just on the spec sheet.
S80186: 16-bit 80186 compatible IP core
https://www.jamieiles.com/80186/
The S80186 IP core is a compact, 80186 binary compatible core, implementing the full 80186 ISA suitable for integration into FPGA/ASIC designs. The core executes most instructions in far fewer cycles than the original Intel 8086, and in many cases, fewer cycles than the 80286. The core is supplied as synthesizable SystemVerilog, along with a C++ reference model, extensive tests, a reference BIOS implementation and reference FPGA designs. The core is released under the GPLv3 license.
Tomi Engdahl says:
Don’t Let FPGA Compiles Be a Bottleneck
How to create real-time, over-the-air testbeds.
https://semiengineering.com/dont-let-fpga-compiles-be-a-bottleneck/
Wireless engineers often want to use over-the-air signals to go from concept to prototype. Software defined radios (SDRs) such as the USRP (Universal Software Radio Peripheral) device provide a flexible solution to meet that need. With today’s applications demanding higher bandwidths and lower latencies, more of this signal processing needs to be implemented on the FPGAs of SDRs. However, wireless engineers programming FPGAs often face the following challenges:
1. Difficulties interfacing between FPGAs and RF signals, the host CPU, and other resources like on-chip memory
2. Unfamiliar programming paradigms for algorithm implementation, and
3. Long compile times
FPGAs for Wireless Engineers Series: Don’t Let FPGA Compiles Be a Bottleneck
http://www.ni.com/white-paper/54246/en/
Tomi Engdahl says:
eFPGA IP Density, Portability And Scalability
https://semiengineering.com/efpga-ip-density-portability-and-scalability/
A look at the different business models and what happens when companies embed FPGA IP.
FPGA chip companies generally build a new generation of FPGAs every ~3 years when there is a major advance in process technology.
They pick one foundry, one node, one variation of that node and do full-custom circuit design with typically the maximum or near-maximum number of metal layers in order to get the highest density FPGA they can. It takes them most of the 3 years to do the complex engineering required.
Since FPGA customers want a range of sizes and some variation in the ratio of options like DSP/RAM, the FPGA chip companies will construct their FPGAs from some modular pieces: a block of LUTs, a DSP block, and typically a block-RAM (dual port). The 3-10 different sizes of the FPGA are put together from the blocks with circuit designers tuning the mesh interconnects and I/O’s for the array size.
Dense, Portable, Scalable Silicon-Proven eFPGA GDS
http://www.flex-logix.com/dense-scalable-portable-proven-efpga-gds/
Tomi Engdahl says:
Mid-range FPGAs offer optimised cost, lower power, better security
https://www.eetimes.com/document.asp?doc_id=1332467&
While Microsemi has been in the programmable logic business for nearly 30 years, until recently the company was addressing only 35-40 percent of the field programmable gate array (FPGA) market. The launch of its mid-range PolarFire FPGAs, with up to treble the logic density, has increased the market Microsemi could serve by $1 billion.
“There were applications in the communications infrastructure, defense and industrial automation segments we previously couldn’t address, as we didn’t have sufficient density or gate count, fabric performance or things like10Gbps serial transceivers,” explains Rick Goerner, executive vice president of marketing and sales at Microsemi. “With PolarFire, we can address these applications, and compete for sockets of up to 500k logic elements.”
PolarFire is the company’s fifth generation of FPGAs on UMCs 28nm process node, and now offers higher density products with the same compelling power, security and cost advantages as previous families.
Tomi Engdahl says:
Develop on Intel® FPGAs
https://software.intel.com/iot/hardware/fpga?utm_source=Facebook&utm_medium=banner&utm_content=IoT_Enthusiasts_Commercial_EMEA&utm_campaign=DRD_17_146
Accelerate the smart and connected world with scalable and flexible solutions.
Introducing the Intel® Cyclone® 10 LP FPGA Evaluation Kit
This low-cost kit is an excellent hardware platform for FPGA developers, IoT system designers, makers, and students to begin designing with programmable logic. Intel® Cyclone® 10 LP FPGAs are optimized for power and cost-sensitive applications and designed for commercial, industrial, and automotive use.
Tomi Engdahl says:
The Future of Microcontrollers
https://www.eetimes.com/author.asp?section_id=36&doc_id=1332604&
Integration of eFPGA into microcontrollers is happening today now that this technology is available from multiple suppliers in 180nm to 16nm process nodes.
Microcontrollers today have an issue and an opportunity.
The issue is that at older process nodes, there are dozens of SKUs of microcontrollers with small variations in the type and number of serial I/Os and/or hardware accelerators. At 40nm, the mask costs start to rise substantially so doing dozens of variations is an expensive proposition.
The opportunity for microcontrollers is around the “glue” FPGA chips used by designers for decades. If these FPGA chips are integrated instead of being standalone, customers can significantly improve the cost, speed and power consumption of MCUs. This is a huge value proposition.
While not a new technology, embedded FPGA (eFPGA) is finally at the stage where it is ready to go mainstream with multiple suppliers, design wins in progress and proven silicon.
Programmable I/O
Microcontrollers often have dozens of variations to accommodate customer requirements for different combinations of serial I/Os: UART, USART, I2C, SPI and more.
With eFPGA, serial I/Os can now be programmed as needed. This enables MCU companies to save on mask costs and validation and provides customers with exactly the serial I/O they want, even variations on the standard versions.
Initially, customers may not even realize they are using eFPGA because the manufacturer can program the eFPGA differently for each SKU.
This is just the start.
The next step is to use the eFPGA to process I/O so as to offload the MPU, improve performance and even lower power.
Reconfigurable Accelerators
Microcontrollers today sometimes have hardwired to offload the processors to improve performance. Examples of this are crypto-engines such as Advanced Encryption Standard (AES.)
Tomi Engdahl says:
HDMI in to HDMI out on a ZYNQ based platform.
HDMI demonstration on the EMC2 development platform from Sundance with signal processing
https://hackaday.io/project/12536-hdmi-in-to-hdmi-out-on-a-zynq-based-platform
The demonstration runs on a stand-alone EMC² Development Platform PCIe/104 OneBank™ board feature a Zynq XC7Z030 with dual ARM9 CPU, a reconfigurable FPGA Logic and an interface to CPU specific I/O features.
The ARM processor core have direct access to the DDR3 memory that provides 1GByte of storage.
The purpose of this demo is to allow real-life data, in this case a video-stream from a HDMI Output to be loaded into the Zynq’s DDR memory and then displayed again on a second HDMI-Input device (typically a monitor).
In this demonstration, a VITA57.1 FMC® compatible Daughter Card is plugged to the EMC²-DP to provide HDMI input/output capabilities.
This demo shows how to implement computing intensive tasks in hardware by using High Level Synthesis tools.
Hardware design
The demo is based on a customed design platform developed in Vivado 2017.2. The demo runs on a Zynq XC7Z030.
The resolution of the input and output video data is set at 1280×720 with a 65MHz frequency rate.
For the video input and video output we used respectively HDMI input IP and HDMI output IP that already existed. The HDMI input component (ADV7611) and the HDMI output component (ADV7511) are configured by software at start up.
A UART interface is used to communicate and configure different part of the system (HDMI, VDMA, VTC).
Tomi Engdahl says:
Get eFPGA With Your CPU Now
https://semiengineering.com/get-efpga-with-your-cpu-now/
Embedded FPGA accelerators provide a boost for both ARM and RISC-V processors.
Tomi Engdahl says:
Intel is now the FPGA manufacturer after the recent acquisition of Altera. Now the company has introduced the market’s first FPGA chip with integrated high-speed EMBED (Embedded Multi-Die Interconnect Bridge). As a result, data is transferred from the units to the memory at 512 gigabytes per second.
In an Intel Roadmap, FPGAs are used as processor for data center servers. Very specific floating point counts can be implemented in the programmable matrix, which makes the execution of a variety of algorithms significantly faster than the general processors.
The Stratix 10 MX is the first circuit in which Intel uses its HMB2 memory (High Memory Bandwidth). Compared to a standard DDR-type DIMM, the bus is about 10 times faster.
The 14-nanometer processor with a 1 GHz clock frequency FPGA has a fast, 28-gigabit transceiver in the Stratix 10 standard.
Source: http://www.etn.fi/index.php/13-news/7339-fpga-dataa-10-kertaa-nopeammin
More: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/wp/wp-01264-stratix10mx-devices-solve-memory-bandwidth-challenge.pdf
Tomi Engdahl says:
Programmable Logic Holds the Key to Addressing Device Obsolescence
https://www.eetimes.com/author.asp?section_id=36&doc_id=1332754
The use of programmable devices helps designers not only to address component obsolescence, but also to reduce the cost and complexity of the solution.
Many applications have a long service life — for example those deployed within industrial, scientific and military industries. In these applications, the service life may exceed that of component availability, impacting the ability of the manufacturer to perform repairs or start new production runs. If the obsolete devices are discrete components such as passive devices, replacement parts might be identified more easily.
However, if the component which has been made obsolete is more complex, such as a processor, logic function or microcontroller, then identifying a suitable replacement device is much more complicated. Replacing these more advanced, obsolete components in a design can be very costly, potentially requiring an entire redesign of the electronic hardware and software. The use of programmable devices helps mitigate these impacts allowing designers not only to address the component obsolescence, but also to reduce the cost and complexity of the solution.
Programmable logic devices are provided in a range of devices of different types, capabilities and sizes, from FPGAs to System on Chips (SoC) and Complex Programmable Logic Devices (CPLD). Designers can select the appropriate type and device dependent upon their requirements.
The flexible nature of these programmable devices provides two significant benefits:
Any-to-any interfacing capabilities: The devices can be configured to implement legacy and bespoke bus interfaces as well as any industry standard interface.
Emulation: The obsolete function can be emulated within the device, whether it is a logic function implemented in programmable logic in a CPLD, FPGA or SoC, or a processor system implemented in an FPGA or SoC. Complex processor systems can be implemented using either a soft core within a FPGA, or a dedicated hard core based ARM processor within a processing system, forming a System on Chip.
Tomi Engdahl says:
Hands On
Use the ezPixel FPGA Board to Control Giant Arrays of Smart LEDs
https://spectrum.ieee.org/geek-life/hands-on/use-the-ezpixel-fpga-board-to-control-giant-arrays-of-smart-leds
Tomi Engdahl says:
PulseRain M10
https://www.crowdsupply.com/pulserain-technology/pulserain-m10
The power of FPGA meets the simplicity of Arduino.
“It’s now possible to embed a soft-core MCU into an FPGA rather than using a hard-core ASIC MCU and here is where PulseRain comes into play with an open source design down to the silicon level.”
The PulseRain M10 is an FPGA dev board. But unlike standard dev boards, the M10 takes a distinctive technical approach by embedding an open source soft MCU core (96 MHz) in an Intel/Altera MAX10 FPGA, while offering an Arduino-compatible software interface and form factor. It also features onboard resources like a voice CODEC, microSD socket, SRAM, onchip ADC, TSD (Temperature Sensor Diode) and dual IO voltages. On top of that, the whole design is 100% open, including the PCB design, the System Verilog code for the FPGA, and the software.
Tomi Engdahl says:
TinyFPGA Computer Project Board
https://hackaday.io/project/29526-tinyfpga-computer-project-board
An FPGA retro-computer Pico-ITX board you assemble with through-hole
Tomi Engdahl says:
SmartFusion®2 Maker-Board
https://www.digikey.com/en/product-highlight/m/microsemi-soc/smartfusion2-maker-board?WT.mc_id=PressRelease
Microsemi introduces its Digi-Key exclusive low-cost evaluation board based on SmartFusion2 SoC FPGA technology
Microsemi’s SmartFusion®2 maker board, available exclusively at Digi-Key, provides designers with the lowest cost evaluation board to access the SmartFusion2 system-on-chip (SoC) FPGA. This device integrates a 12 K LE Flash-based FPGA fabric, a 166 MHz ARM® Cortex®-M3 processor, DSP blocks, SRAM, eNVM, and general purpose GPIO interfaces all on a single chip.
The SmartFusion2 maker board can be used with Microsemi’s Libero SoC v11.8 software or more recent versions of it. Libero SoC with a silver license will program the FPGA fabric of the SmartFusion2. To code the ARM Cortex M3, Microsemi offer a full featured, Eclipse based IDE called SoftConsole. This IDE enables firmware engineers to program in C/C++ and includes full debugging of the ARM Cortex-M3.
Tomi Engdahl says:
Arrow’s $30 FPGA Board Reviewed
https://hackaday.com/2018/01/27/arrows-30-fpga-board-reviewed/
We like cheap FPGA boards. It isn’t just that we’re cheap — although that’s probably true, too — but cheap boards are a good way to get people started on FPGAs and we think more people should be using FPGAs more often. One inexpensive board is the Max-1000 from Trenz and Arrow. At $29, it is practically an impulse buy. [ZipCPU] did a great write up on his experience using the board.
On the good side, the board is cheap and powerful. It doesn’t have a lot of I/O on board, but it has enough expansion options that you shouldn’t have any problems. The bad side was mostly documentation and driver issues.
The biggest problem, though, was the lack of Linux drivers. This was later fixed, but he found the Linux drivers didn’t work, and required him to remove other FTDI drivers which was not convenient. The good news is that the open source libsvf driver worked fine.
Arrow’s Max-1000: A gem for all the wrong reasons
http://zipcpu.com/blog/2017/12/16/max1k.html
While I love the MAX1000’s design and the opportunities built into the circuit board, and while the sales sheet looks beautiful, building with this board has already taken more work than I had expected. The primary difficulty I’ve had so far, other than the Ugly section below, has been finding the documentation.
The first part of working with any circuit board is always finding the documentation. This means finding a board’s schematic, its User Guide, and any data sheets for the parts on the board. In this regard, I may be spoiled by Digilent
Okay, now for the really ugly part: I bought my MAX1000 only to discover on the wiki that they hadn’t finished building their Linux driver yet, so they hadn’t yet posted it for download.
Conclusion
I suppose at the end of any review I should offer a recommendation: should someone buy this board or not? To that question I would answer that it depends upon the someone.
If you are willing to do some soldering, and you aren’t afraid of working without the best documentation then you might find this a nicely built, well-designed FPGA board to work with.
It certainly offers more capabilities than the CMod S6, at a much lower price point, although you will need to do some soldering if you want to connect the MAX1000 to a breadboard.
In a similar fashion, if you want to do some experimentation with the FT2232 interface found on many FPGA boards, the documentation and libxvsf should give you a clear enough starting point.
On the other hand, if you’ve never done any FPGA design before and just want a beginner’s board, this probably isn’t (yet) the board you want to start out with.
As for me, finding an open source FT2232 interface and schematic makes it all worth while.
Tomi Engdahl says:
A Look at TinyFPGA Boards
https://www.eeweb.com/profile/duane-benson-2/articles/a-look-at-tinyfpga-boards
TinyFPGA boards offer an inexpensive way for ‘microcontroller jockeys’ to get an introduction to the world of FPGAs
I haven’t spent any time with my FPGA (Field-Programmable Gate Array) boards in nearly a year. It’s not that I no longer like FPGAs; it’s just that I’ve just been occupied with other things.
Recently, however, I spotted something that piqued my programmable logic interest: the TinyFPGA series by Luke Valenty (TinyFPGA.com). As of this writing, Luke has three variations for sale, all of which are based on small FPGAs from Lattice Semiconductor. The TinyFPGA A1 offers an XO2-256 containing 256 logic cells; the A2 sports an XO2-1200 with 1200 logic cells (imagine that), and the B2 boasts an ICE40LP8K with 7680 logic cells.
The A1 and A2 ($12.00 and $18.00, respectively) require Luke’s TinyFPGA Programmer ($9.00), while the B2 ($38.00) is programed over USB and doesn’t require a separate programmer.
Tomi Engdahl says:
http://linuxgizmos.com/open-source-cape-opens-beaglebone-up-to-lattice-ice40-fpga/
Open source cape opens BeagleBone up to Lattice iCE40 FPGA
Feb 28, 2018 — by Eric Brown — 228 views
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A CrowdSupply campaign is pitching an open source $85 “BeagleWire” BeagleBone cape with a Lattice iCE40HX-4k FPGA, 4x Grove interfaces, 4x PMODs, and 32MB RAM.
Tomi Engdahl says:
Grinding Coffee with a TinyFPGA Board
https://www.eeweb.com/profile/duane-benson-2/articles/grinding-coffee-with-a-tinyfpga-board
TinyFPGA boards offer an inexpensive way for ‘microcontroller jockeys’ to get an introduction to the world of FPGAs
Tomi Engdahl says:
FPGA Calculator Uses Joystick
https://hackaday.com/2018/02/28/fpga-calculator-uses-joystick/
FPGAs are great fun, but sometimes you need a few starter projects under your belt. These projects might be something you could just as well do with a CPU, but you have to start somewhere. [LambdaPI] recently shared a 4-bit calculator created using an FPGA
https://github.com/LambPi/Calculator
Tomi Engdahl says:
Caped Beagle is FPGA Superhero
https://hackaday.com/2018/03/03/caped-beagle-is-fpga-superhero/
We miss the days when everything had daughterboards. Now, Arduinos have shields and Raspberry Pis have hats. The BeagleBone has capes. Whatever. However, regardless of the name, the open source BeagleWire cape/shield/hat/daughterboard connects to a BeagleBone and provides a Lattice iCE40HX FPGA, some support hardware, and common I/O connectors like Pmod and Grove. You can see a video about the board below.
In addition to the FPGA, the board contains a EEPROM, RAM, flash memory, an oscillator, and a few buttons, switches and LEDs. The buttons even feature hardware debouncing. The parts list and design files are all available and — depending on a successful crowdfunding campaign — you might be able to buy one for $75 in the future.
https://www.crowdsupply.com/qwerty-embedded-design/beaglewire
Tomi Engdahl says:
Small Stack Computing in VHDL
https://blog.hackster.io/small-stack-computing-in-vhdl-823bef3594d4
Forth virtual machine was relatively simple to implement, there are numerous implementations of the language. Amongst them is the J1 put together by James Bowman, a small Forth-based CPU implemented for FPGA. Implemented in just 200 lines of Verilog, a 50 MHz J1 CPU was used as a co-processor for the Gameduino.
Tomi Engdahl says:
A DIY Nine Channel Digital Scope
https://hackaday.com/2018/03/22/a-diy-nine-channel-digital-scope/
Have you ever found yourself in the need of a nine channel scope, when all you had was an FPGA evaluation board? Do not despair, [Miguel Angel] has you covered. While trying to make sense of the inner workings of a RAM controller core, he realized that he needed to capture a lot of signals in parallel and whipped up this 9-channel digital oscilloscope.
The scope is remote-controlled via a JavaScript application, and over Ethernet. Graphical output is provided as a VGA signal at full HD, so it is easy to see what is going on. Downloading sampled data to the controlling computer for analysis is in the works. [Miguel] runs his implementation on an Arty A7 development board which is currently available for around a hundred dollars, but the design is transferable to other platforms. The code and some documentation is available on GitHub
ScopeIO
Embedded Measurement System for FPGA
https://hackaday.io/project/98429-scopeio
Tomi Engdahl says:
VerilogBoy – GameBoy on FPGA
A Pi emulating a GameBoy sounds cheap. What about an FPGA?
https://hackaday.io/project/57660-verilogboy-gameboy-on-fpga
Tomi Engdahl says:
Getting Started with the MiniZed FPGA SoC
https://www.hackster.io/dhq/getting-started-with-the-minized-fpga-soc-aa7a25
Learn how to pulse width modulate an LED from the FPGA side of a ZYNQ SoC.
Tomi Engdahl says:
Tech Talk: FPGA RTL Checking
How to make sure the RTL in an FPGA matches what you developed.
https://semiengineering.com/tech-talk-fpga-rtl-checking/
Tobias Welp, software architect and engineering manager at OneSpin Solutions, explains how to ensure the RTL created by design engineers matches what shows up in an FPGA.
Tomi Engdahl says:
http://www.etn.fi/index.php/13-news/7886-graafisesti-koodia-fpga-piireille
Tomi Engdahl says:
The Arduino IDE-Compatible Snō Module Looks Like a Great Way to Get Started with FPGAs
https://blog.hackster.io/the-arduino-ide-compatible-snō-module-looks-like-a-great-way-to-get-started-with-fpgas-e1b3b3ea9086
FPGAs tend to have a steep learning curve, and a big part of that is due to the difficultly of programming them. The Snō FPGA module from Alorium Technology is designed to make that easier by integrating an ATmega328 that’s compatible with the Arduino IDE.
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Cameron Coward
Author, writer, maker, and a former mechanical designer. http://www.cameroncoward.com @cameron_coward
May 1
The Arduino IDE-Compatible Snō Module Looks Like a Great Way to Get Started with FPGAs
An FPGA (field-programmable gate array) is a device that enables you to actually program true circuits, instead of hard wiring or emulating them. You can, for instance, program a vintage Z80 CPU in hardware — you’re not just emulating it in software. But, FPGAs tend to have a steep learning curve, and a big part of that is due to the difficultly of programming them. The Snō FPGA module from Alorium Technology is designed to make that easier by integrating an ATmega328 that’s compatible with the Arduino IDE.
The board contains a real FPGA chip — an Intel MAX 10 with 1,000 logic array blocks. That’s certainly not a record-breaking number, but it’s surprisingly good for the Snō’s very affordable $49 price. However, the real selling point here is the workflow for programming the FPGA. Through the Arduino IDE, you can use pre-programmed or downloadable XBs (Xcelerator Blocks) that configure the FPGA for functions like servo control and NeoPixel operation.
OpenXLR8 workflow gives you the ability to program and upload new XBs for your own functions.
Tomi Engdahl says:
Tiny FPGA Board Fits in Your Laptop
https://hackaday.com/2018/05/31/tiny-fpga-board-fits-in-your-laptop/
There are a bunch of FPGA development boards to choose from, but how many will fit inside your laptop? The PicoEVB is a tiny board that connects to a M.2 slot and provides an evaluation platform for the Xilinx Artix-7 FPGA family.
This minimalist board sports a few LEDs, a PCIe interface, an integrated debugger, on-board EEPROM, and some external connectors for hooking up other bits and pieces. The M.2 connector provides the board with power, USB for debugging, and PCIe for user applications.
Xilinx Artix FPGA development board, M.2
$219.00
https://picoevb.com/
Tomi Engdahl says:
FPGAs Becoming More SoC-Like
https://semiengineering.com/fpgas-becoming-more-soc-like/
Lines blur as processors are added into traditional FPGAs, and programmability is added into ASICs.
FPGAs are blinged-out rockstars compared to their former selves. No longer just a collection of look-up tables (LUTs) and registers, FPGAs have moved well beyond into now being architectures for system exploration and vehicles for proving a design architecture for future ASICs.
Tomi Engdahl says:
Pipelining Digital Logic in FPGAs
https://hackaday.com/2018/06/05/pipelining-digital-logic-in-fpgas/
When you first learn about digital logic, it probably seems like it is easy. You learn about AND and OR gates and figure that’s not very hard. However, going from a few basic gates to something like a CPU or another complex system is a whole different story. It is like going from “Hello World!” to writing an operating system. There’s a lot to understand before you can make that leap. In this set of articles, I want to talk about a way to organize more complex FPGA designs like CPUs using a technique called pipelining.
These days a complex digital logic system is likely to be on an FPGA. And part of the reason we can get fooled into thinking digital is simple is because of the modern FPGA tools. They hide a lot of complexity from you, which is great until they can’t do what you want and then you are stuck.
While we tend to think of our circuits as perfect, they aren’t. The logic gates are fast — very, very fast — but they are not infinitely fast. On larger chips, even the time for a signal to get to one part of the chip to another becomes significant.
Tomi Engdahl says:
CAT Board
https://hackaday.io/project/7982-cat-board
The CAT Board is part of a Raspberry Pi-based hand-held FPGA programming system.
The CAT Board is an OSHW Raspberry Pi HAT with a Lattice iCE40HX FPGA. It’s meant to be programmed using the OSS myhdl, yosys, arachne-pnr, IceStorm tools right on the RPi.
Tomi Engdahl says:
FPGA Persistently Rick Rolls You
https://hackaday.com/2018/06/11/fpga-persistently-rick-rolls-you/
When [Im-pro] wants a display, he wants it to spin. So he built a persistence of vision (POV) display capable of showing a 12-bit color image of 131 x 131 pixels at 16 frames per second. You can see a video about the project below, but don’t worry, you can view it on your normal monitor.
The project starts with a Java-based screen capture on a PC. Data goes to the display wirelessly to an ESP8266. However, the actual display drive is done by an FPGA that drives the motor, reads a hall effect index sensor, and lights the LEDs.
https://im-pro.at/index.php/projekte/2018-pov
Tomi Engdahl says:
Getting Good at FPGAs: Real World Pipelining
https://hackaday.com/2018/06/11/understanding-a-mosfet-mixer/
Parallelism is your friend when working with FPGAs. In fact, it’s often the biggest benefit of choosing an FPGA. The dragons hiding in programmable logic usually involve timing — chaining together numerous logic gates certainly affects clock timing. Earlier, I looked at how to split up logic to take better advantage of parallelism inside an FPGA. Now I’m going to walk through a practical example by modeling some functions. Using Verilog with some fake delays we can show how it all works. You should follow along with a Verilog simulator, I’m using EDAPlayground which runs in your browser. The code for this entire article is been pre-loaded into the simulator.
If you’re used to C syntax, chances are good you’ll be able to read simple Verilog.
https://hackaday.com/2018/06/05/pipelining-digital-logic-in-fpgas/
Tomi Engdahl says:
FPGA-Based Edge Detection Using HLS
https://www.hackster.io/adam-taylor/fpga-based-edge-detection-using-hls-192ad2
Leveraging HLS functions to create a image processing solution which implements edge detection (Sobel) in programmable logic.
Tomi Engdahl says:
Signal Generator Uses FPGA
https://hackaday.com/2018/08/11/signal-generator-uses-fpga/
Although there are a few exceptions, FPGAs are predominantly digital devices. However, many FPGA applications process analog data, so you often see an FPGA surrounded by analog and digital converters. This is so common that Opal Kelly — a producer of FPGA tools — launched the SYZYGY open standard for interconnecting devices like that. [Armeen] — a summer intern at Opal Kelly — did a very interesting open source FPGA-based signal generator using a Xilinx FPGA, and a SYZYGY-compliant digital to analog converter.
Verilog code (available on GitHub) shows a lot of interesting things
Following how the AM and FM generation works is a great introduction to signal synthesis in an FPGA.
High Performance FPGA-Based Signal Generator using the XEM7320, FrontPanel, and SYZYGY DAC
https://www.opalkelly.com/high-performance-fpga-based-signal-generator-using-the-xem7320-frontpanel-and-syzygy-dac/
Tomi Engdahl says:
FPGAs are getting a lot of press these days with Arduino jumping in the fray.
https://hackaday.com/2018/07/30/hands-on-with-new-arduino-fpga-board-mkr-vidor-4000/
Tomi Engdahl says:
Cheap FPGA Board Roundup
https://hackaday.com/2018/08/20/cheap-fpga-board-roundup/
Tomi Engdahl says:
Visualizing Verilog Simulation
https://hackaday.com/2018/09/03/visualizing-verilog-simulation/
You don’t usually think of simulating Verilog code — usually for an FPGA — as a visual process. You write a test script colloquially known as a test bench and run your simulation. You might get some printed information or you might get a graphical result by dumping a waveform, but you don’t usually see the circuit. A new site combines Yosys and a Javascript-based logic simulator to let you visualize and simulate Verilog in your browser. It is a work in progress on GitHub, so you might find a few hiccups like we did, but it is still an impressive piece of work.
http://digitaljs.tilk.eu/
Tomi Engdahl says:
34C3: Reverse Engineering FPGAs
https://hackaday.com/2018/01/17/34c3-reverse-engineering-fpgas/
Tomi Engdahl says:
Apple One, On FPGA
https://hackaday.com/2018/03/29/apple-one-on-fpga/
Tomi Engdahl says:
CDL – Circuit Description Language
An improved hardware description language.
https://hackaday.io/project/28634-cdl-circuit-description-language
The project is intended to be a learning experience in language/compiler theory. The intent of CDL is to provide a relatively beginner-friendly hardware description language that can be compiled into VHDL code which would then be synthesized to run on an FPGA.
Tomi Engdahl says:
MicroZed Chronicles: Triple Modular Redundancy and MicroBlaze
https://blog.hackster.io/microzed-chronicles-triple-modular-redundancy-and-microblaze-78080b8046e4
One common theme throughout my career has been developing FPGAs and SoCs for high reliability applications. This has ranged from controlling nuclear reactors to satellites, defense, and automotive applications.
Tomi Engdahl says:
MicroZed Chronicles: A Look at the Zynq MPSoC EV H.265 Video Codec
https://blog.hackster.io/microzed-chronicles-a-look-at-the-zynq-mpsoc-ev-h-265-video-codec-f076c6eca94a
In addition to the high reliability design work I mentioned last week, I also spend a significant amount of time designing imaging processing applications for systems such as automotive, astronomy, aerospace and defense, etc.