Moore’s Law is turning 50 years old. On April 19, 1965, Electronics magazine published a paper in which Gordon Moore made a stunning observation: About every two years, engineers should be able to cram twice as many transistors into the same area of a silicon chip. At its core of the article was a non-intuitive, and incredibly ballsy, prediction that with the advent of microelectronics, computing power would grow dramatically, accompanied by an equally dramatic decrease in cost. At the time of the publication there was no special name for this observation – the name came later. Caltech professor Carver Mead is widely credited with popularizing the phrase “Moore’s Law.” Over the next 50 years, engineers more or less managed to maintain that predicted pace of innovation, delivering dramatically better semiconductors.
Moore’s prediction may have started out as a fairly simple observation of a young industry, but over time it became an expectation and self-fulfilling prophecy as engineers and companies that saw the benefits of Moore’s Law and did their best to keep it going. Gordon Moore now says himself that he formulated “laws” because he saw that the semiconductor industry should go in that direction. Moore’s Law, the greatest impact has been the technology price even lower prices.
This development has had huge effect to everybody. More changes in the world can be traced back to the enabling power of the semiconductor industry than any other industry This development has generated huge value for a large number of companies directly and indirectly: “The market value of the companies across the spectrum of technology driven by Moore’s Law amounted to $13 trillion in 2014,” Hutchison estimated. “Another way to put it is that one-fifth of the asset value in the world’s economy would be wiped out if the integrated circuit had not been invented and Moore’s law never happened”
IEEE is running a worth to read special report on “50 Years of Moore’s Law” that considers “the gift that keeps on giving” from different points of view. Chris Mack begins by arguing that nothing about Moore’s Law was inevitable. Another article on the same topic is How Gordon Moore Made “Moore’s Law”. Check also EDN article collection Moore from the Archives and ExtremeTech article Moore’s Law is dead, long live Moore’s Law.
33 Comments
Tomi Engdahl says:
Moore’s Law: Dead or Alive
The Busters and Boosters determining its future
http://www.eetimes.com/document.asp?doc_id=1326377
Few people know that McGraw-Hill invented the moniker “Electronics” in 1930 for its magazine on that subject. I joined Electronics on its 50th birthday, for which we did a special bound-book history of electronics including Gordon Moore’s amazing accomplishments founding Fairchild Semiconductor and later co-founding Intel (with Andy Grove and Robert Noyce, see photo). However, it was on Electronics 35th birthday that Gordon Moore contributed an article titled “Cramming more components onto integrated circuits.” In that article he speculated that the number of transistors on chips would “double every 12 months,” which in 1975 he revised to every two years. Moore made no reference to a “law”, but Caltech professor Carver Mead, who literally invented very-large-scale-integration (VLSI), popularized the notion of “Moore’s law” as governing the way VLSI would grow the future of electronics.
Since then, Moore’s law has become a self-fulfilling prophecy,
Tomi Engdahl says:
Moore’s Law @50 in the News
http://www.eetimes.com/author.asp?section_id=36&doc_id=1326392&
Here’s a sampler of some of the best of the reports that marked the official anniversary of Moore’s Law on Sunday, April 19.
Google News tracked 116 articles on the official 50th anniversary of Moore’s Law on April 19. I’m amazed the number is so small given the Web site sometimes serves up thousands of articles on hot topics.
Without Moore’s Law there would be no Google News or a whole host of much more significant innovations too numerous to mention. So, let me point to just a few of the good articles on the topic I clicked through on Sunday.
Tomi Engdahl says:
Moore’s Law: Dead or Alive
The Busters and Boosters determining its future
http://www.eetimes.com/document.asp?doc_id=1326377&
Tomi Engdahl says:
Remove the Moore’s Law Blinders
http://www.eetimes.com/author.asp?section_id=36&doc_id=1326408&
The best is yet to come as new materials, logic architectures and software portend to deliver performance gains far beyond Moore’s Law scaling limits.
Tomi Engdahl says:
Moore’s Law: What Broke the Model
http://www.eetimes.com/author.asp?section_id=182&doc_id=1326655&
In a sense Moore’s Law, or at least many of the benefits it gives, ended years ago around the 90 nm node when Dennard scaling fell apart.
Last month (April, 2015) was the 50th anniversary of Moore’s Law.
No one seems to be sure what Moore’s Law is. Moore originally predicted the number of transistors on a chip would double every year; later he amended that to two years. Some now claim the law sets an 18 month rate. Others say the law predicts that system performance will double every 18 months (or two years, depending on who is making the claim).
The mainstream press is clueless about the “law.”
. . . In a sense Moore’s Law, or at least many of the benefits it gives, ended years ago around the 90 nm node when Dennard scaling fell apart.
The demise of Moore’s Law
http://www.embedded.com/electronics-blogs/break-points/4439472/The-demise-of-Moore-s-Law
In a sense Moore’s Law, or at least many of the benefits it gives, ended years ago around the 90 nm node when Dennard scaling fell apart. In 1974 Robert Dennard noted that as geometries shrink we get all sorts of goodness like higher clock rates and lower power. Many of the benefits he described no longer come with increasing densities. Today the law does give us more transistors per unit area, which translates into better performance and a lower cost-per-gate. However, some believe that 20 nm broke even the cost model.
A silicon atom is about 0.25 nm in diameter. Gate oxide thicknesses are measured in a handful of atoms. The scales are truly amazing, and to think of us manipulating things on an atomic scale is breathtaking. The technology is astounding. And yet it’s commonplace; most everyone in the developed world has a device built with 28 nm or smaller processes.
How many transistors are in your pocket?
A few months ago I bought a 128 GB thumb drive for $45. 128 GB means a trillion bits of information. Who could resist tearing something like that apart? It has two memory chips, so each chip stores a half-trillion bits. Memory vendors don’t say much about their technology, but I haven’t seen MLC flash with more than three levels. Each of these chips may have over 100 billion transistors.
I suspect Moore’s Law will have a healthy future. Memory devices are leading the way into 3D architectures. Processors might follow
Tomi Engdahl says:
Sindhu put some heat behind his words. He noted the declining benefits of Moore’s Law as we enter the last few turns of the crank on standard CMOS process technology.
“Ten years ago we started to see that phenomena tapering off,” Sindhu said. “Today clock frequencies top out at 4GHz, instructions per clock are not increasing and as you increase the number of cores the power or bandwidth is the limit — and memories not getting any faster,” he said,
Nevertheless, “the hunger of the world for more compute has not gone away, so we have essentially a crisis in computing [because] you are getting no more than 10-20% improvement and in the next ten years that will flatten completely,” he said, predicting a rise in specialized silicon engines paired with general-purpose processors.
Source: http://www.eetimes.com/author.asp?section_id=36&piddl_msgid=341308&doc_id=1326666&page_number=2
Tomi Engdahl says:
Moore’s Law Keeps Going, Defying Expectations
https://www.scientificamerican.com/article/moore-s-law-keeps-going-defying-expectations/
It’s a mystery why Gordon Moore’s “law,” which forecasts processor power will double every two years, still holds true a half century later
Personal computers, cellphones, self-driving cars—Gordon Moore predicted the invention of all these technologies half a century ago in a 1965 article for Electronics magazine. The enabling force behind those inventions would be computing power, and Moore laid out how he thought computing power would evolve over the coming decade. Last week the tech world celebrated his prediction here because it has held true with uncanny accuracy—for the past 50 years.
It is now called Moore’s law, although Moore (who co-founded the chip maker Intel) doesn’t much like the name. “For the first 20 years I couldn’t utter the term Moore’s law. It was embarrassing,
Of course, Moore’s law is not really a law like those describing gravity or the conservation of energy. It is a prediction that the number of transistors (a computer’s electrical switches used to represent 0s and 1s) that can fit on a silicon chip will double every two years as technology advances. This leads to incredibly fast growth in computing power without a concomitant expense and has led to laptops and pocket-size gadgets with enormous processing ability at fairly low prices. Advances under Moore’s law have also enabled smartphone verbal search technologies such as Siri—it takes enormous computing power to analyze spoken words, turn them into digital representations of sound and then interpret them to give a spoken answer in a matter of seconds.
But Moore never thought his prediction would last 50 years. “The original prediction was to look at 10 years, which I thought was a stretch,
“This was going from about 60 elements on an integrated circuit to 60,000—a 1,000-fold extrapolation over 10 years. I thought that was pretty wild. The fact that something similar is going on for 50 years is truly amazing.”
Tomi Engdahl says:
Moore’s Law creates new test product categories
http://www.edn.com/electronics-blogs/test-cafe/4439518/Moore-s-Law-creates-new-test-product-categories?_mc=NL_EDN_EDT_EDN_weekly_20150528&cid=NL_EDN_EDT_EDN_weekly_20150528&elq=e142faa441cb421f979dca34d9e45c9c&elqCampaignId=23198&elqaid=26131&elqat=1&elqTrackId=649d7857f2a34df1af56c8578425a7dc
This year we celebrated the 50th anniversary of Gordon Moore’s famous paper “Cramming more components onto integrated circuits”, the basis of Moore’s Law. Rereading the paper, I was struck by the insight and vision Moore had about the future. Extrapolating from just four data points spanning 1962 to 1965, Moore showed integrated circuits nearly doubling in density each year. “Integrated circuits will lead to such wonders as home computers – or at least terminals connected to a central computer – automatic controls for automobiles, and personal communications equipment,” wrote Moore. Considering this was written in 1965, before even the first digital watch, this was a considerable example of foresight. Dr. Carver Mead, my advisor at Cal Tech, dubbed this continuous doubling of density as Moore’s Law, and the name stuck forever.
A couple of things struck me during my rereading of Moore’s paper. One was his focus on power density, and his belief that power density would be manageable as device geometries shrunk. Remember, these were the days of bipolar logic devices, not CMOS. It was the CMOS revolution that would continue Moore’s extrapolation beyond the 1975 horizon of his paper.
A second observation focuses on his final comments regarding analog circuitry. He predicted a slower pace of change, but significant leaps regardless. His insight that differential amplifier design benefited by the matched components inherent in integrated circuits would lead to the concept of the op amp (operational amplifier), a staple of analog design. “Even in the microwave area,” wrote Moore, “structures included in the definition of integrated electronics will become increasingly important.”
The electronic industry was booming. And with it came higher volumes and a need to automate testing, particularly in manufacturing. Perhaps the biggest change in test equipment was the addition of automation interfaces, most notably IEEE-488, also known as GP-IB.
Figure 2 shows the plethora of new test product types and categories driven by Moore’s Law. Expect 5G wireless and Internet of Things to drive additional product types.
Moore’s law enabled the processor and memory revolution. With it came the semiconductor test industry, with giants like Teradyne and Advantest duking it out in this new product category. The pin-electronics feature of “big-iron” testers proved essential for high-speed digital semiconductor test. A whole new industry was born.
As wireline speeds increased, a new category of testers emerged, called BERTs (Bit Error Ratio Testers). Many had optical interfaces to test the DUTs associated with fiber optic communication.
By the late 1990s, the internet, driven by the perfect storm of Moore’s Law, deregulation, the optical amplifier, led to even more test product categories. Load testers, such as those from Spirent or IXIA, stressed switches and routers in the lab, before they would be deployed into the enterprise or internet, evaluating their behavior under extreme loads or with specific protocols.
Some new categories are emerging, though not yet named.
Tomi Engdahl says:
Insecure radio links and the end of Moore’s Law discussed at DAC 2015
http://www.edn.com/electronics-blogs/benchtalk/4439670/Insecure-radio-links-and-the-end-of-Moore-s-Law-discussed-at-DAC-2015?_mc=NL_EDN_EDT_EDN_today_20150616&cid=NL_EDN_EDT_EDN_today_20150616&elq=9ebbdd84e2f44b8595dccd06965132df&elqCampaignId=23462&elqaid=26475&elqat=1&elqTrackId=860123c9a6bf418cacd9dfbb76f58490
Moore forever?
The Moore naysayers have been around for decades, predicting the demise of Moore’s Law, but so far, they’ve been proven wrong. But these days, more and more people are agreeing the end is nigh. But not Intel’s Vivek Singh. Despite oft-heard claims of flat or even increasing cost per transistor, Singh showed that transistor cost was actually continuing its exponential ride down to the zero limit. The 7nm node is already on track. His background is computational lithography, and he closed his talk with a pattern right out of a “magic eye” book.
Tomi Engdahl says:
Exponential Growth In Linear Time: The End Of Moore’s Law
http://hackaday.com/2015/09/09/exponential-growth-in-linear-time-the-end-of-moores-law/
Moore’s Law states the number of transistors on an integrated circuit will double about every two years. This law, coined by Intel and Fairchild founder [Gordon Moore] has been a truism since it’s introduction in 1965. Since the introduction of the Intel 4004 in 1971, to the Pentiums of 1993, and the Skylake processors introduced last month, the law has mostly held true.
The law, however, promises exponential growth in linear time. This is a promise that is ultimately unsustainable.
In 2011, the Committee on Sustaining Growth in Computing Performance of the National Research Council released the report, The Future of Computing Performance: Game Over or Next Level? This report provides an overview of computing performance from the first microprocessors to the latest processors of the day.
Although Moore’s Law applies only to transistors on a chip, this measure aligns very well with other measures of the performance of integrated circuits. Introduced in 1971, Intel’s 4004 has a maximum clock frequency of about 700 kilohertz.
Motorola 6800 processors, introduced in 1974, ran at 1MHz. In 1976, RCA introduced the 1802, capable of 5MHz. In 1979, the Motorola 68000 was introduced, with speed grades of 4, 6, and 8MHz. Shortly after Intel released the 286 in 1982, the speed was quickly scaled to 12.5 MHz.
There was never any question Moore’s Law would end. No one now, or when the law was first penned in 1965, would assume exponential growth could last forever. Whether this exponential growth would apply to transistors, or in [Kurzweil] and other futurists’ interpretation of general computing power was never a question; exponential growth can not continue indefinitely in linear time.
Even before 2011, when The Future of Computing Performance was published, the high-performance semiconductor companies started gearing up for the end of Moore’s Law. It’s no coincidence that the first multi-core chips made an appearance around the same time TDP, performance, and clock speed took the hard turn to the right seen in the graphs above.
A slowing of Moore’s Law would also be seen in the semiconductor business
While the future of Moore’s Law will see the introduction of exotic substrates such as indium gallium arsenide replacing silicon, this much is clear: Moore’s Law is broken, and it has been for a decade. It’s no longer possible for transistor densities to double every two years, and the products of these increased densities – performance and clock speed – will remain relatively stagnant compared to their exponential rise in the 80s and 90s.
Tomi Engdahl says:
John Markoff / New York Times:
As Moore’s Law slows, engineers look to new approaches and opportunities in chip innovation
Smaller, Faster, Cheaper, Over: The Future of Computer Chips
http://www.nytimes.com/2015/09/27/technology/smaller-faster-cheaper-over-the-future-of-computer-chips.html
At the inaugural International Solid-State Circuits Conference held on the campus of the University of Pennsylvania in Philadelphia in 1960, a young computer engineer named Douglas Engelbart introduced the electronics industry to the remarkably simple but groundbreaking concept of “scaling.”
Sitting in the audience that day was Gordon Moore, who went on to help found the Intel Corporation, the world’s largest chip maker. In 1965, Dr. Moore quantified the scaling principle and laid out what would have the impact of a computer-age Magna Carta. He predicted that the number of transistors that could be etched on a chip would double annually for at least a decade, leading to astronomical increases in computer power.
His prediction appeared in Electronics magazine in April 1965 and was later called Moore’s Law. It was never a law of physics, but rather an observation about the economics of a young industry that ended up holding true for a half-century.
In recent years, however, the acceleration predicted by Moore’s Law has slipped. Chip speeds stopped increasing almost a decade ago, the time between new generations is stretching out, and the cost of individual transistors has plateaued.
Technologists now believe that new generations of chips will come more slowly, perhaps every two and a half to three years.
To put the condition of Moore’s Law in anthropomorphic terms, “It’s graying, it’s aging,” said Henry Samueli, chief technology officer for Broadcom, a maker of communications chips. “It’s not dead, but you’re going to have to sign Moore’s Law up for AARP.”
“Look at automobiles, for example,” Dr. Colwell said. “What has driven their innovations over the past 30 years? Moore’s Law.” Most automotive industry innovations in engine controllers, antilock brakes, navigation, entertainment and security systems have come from increasingly low-cost semiconductors, he said.
The Limits of Physics
Chips are produced in a manufacturing process called photolithography. Since it was invented in the late 1950s, photolithography has constantly evolved. Today, ultraviolet laser light is projected through glass plates that are coated with a portion of a circuit pattern expressed in a metal mask that looks like a street map.
The masks are used to expose hundreds of exact copies of each chip, which are in turn laid out on polished wafers of silicon about a foot in diameter.
Machines called steppers, which currently cost about $50 million each, move the mask across the wafer, repeatedly exposing each circuit pattern to the surface of the wafer, alternately depositing and etching away metal and semiconducting components.
A finished computer chip may require as many as 50 exposure steps, and the mask must be aligned with astonishing accuracy. Each step raises the possibility of infinitesimally small errors.
To build devices that are smaller than the wavelength of light, chip makers have added a range of tricks like “immersion” lithography, which uses water to bend light waves sharply and enhance resolution. They also have used a technique called “multiple pattern” lithography, which employs separate mask steps to sharpen the edges and further thin the metal wires and other chip components.
As the size of components and wires have shrunk to just a handful of molecules, engineers have turned to computer simulations that require tremendous computational power. “You are playing tricks on the physics,”
Silicon could also give way to exotic materials for making faster and smaller transistors and new kinds of memory storage as well as optical rather than electronic communications links
There are a number of breakthrough candidates, like quantum computing, which — if it became practical — could vastly speed processing time, and spintronics, which in the far future could move computing to atomic-scale components.
Recently, there has been optimism in a new manufacturing technique, known as extreme ultraviolet, or EUV, lithography.
But the technology still has not been proved in commercial production.
Intel executives, unlike major competitors such as Samsung and Taiwan Semiconductor Manufacturing Company, or TSMC, insist the company will be able to continue to make ever-cheaper chips for the foreseeable future.
Tomi Engdahl says:
What does Moore’s Law mean for power system design?
http://www.edn.com/electronics-blogs/power-forward/4440793/What-does-Moore-s-Law-mean-for-power-system-design-?_mc=NL_EDN_EDT_EDN_today_20151111&cid=NL_EDN_EDT_EDN_today_20151111&elq=600f583a5c39442e923dd4ee2b78e501&elqCampaignId=25662&elqaid=29205&elqat=1&elqTrackId=3eb63c73b1684d2cbbde47c17fe93b66
In the year that marks the 50-year anniversary of Moore’s Law comes the eager announcement from IBM of its breakthrough 7 nm test chip, beating founding father Intel to the latest holy grail of ever increasing density at an atomic level.
Although the announcement represents an industry milestone in the quest for miniaturization, such advances in density and performance come at a cost. A particular challenge is the increasingly complex power requirements demanded by the lower core voltages, higher currents and tighter tolerances of such new chips. This is magnified at the board level, where it is forcing power system engineers to seek out novel solutions to a problem that’s not going to go away anytime soon
Massive increases in transistor count have now made it possible to implement multiple high-speed processors on a single die, each running at speeds of up to 3 GHz. Such advanced processors and logic devices may be exceptionally powerful, but they’re also very delicate with supply voltages being driven below 1 V. With today’s processors running at 100 W or more, this means currents are starting to exceed the 100 A mark at the point of load.
As well as dropping core voltages, and soaring current values, the reduced geometry has a considerable impact on voltage tolerances. For example, a deviation in voltage of just 2% could result in a processor shutting down. Consequently, maintaining ever tighter transient response specifications on the voltage rails supplying these atomic chips is becoming a big issue for engineers.
The pressure to deliver energy efficiency from these high-current, low-voltage systems means that the processors and support logic need to move into lower-power modes frequently, whilst being able to restore full capability extremely quickly without suffering from voltage deviations. Transient response coupled with accurate power delivery is therefore vital in such high reliability systems.
So IBM’s announcement of its 7nm test chip has shown that Moore’s Law is not done yet. The challenge now for power designers in meeting the complexities of greater functionality in a smaller space that these chips bring, is in coming up with novel ways to offset the requirements of their low core voltage, coupled with the high currents needed to drive them, and voltage tolerances that are tighter than ever before. As ever, the power industry will innovate…
Tomi Engdahl says:
How Supercomputing Can Survive Beyond Moore’s Law
http://spectrum.ieee.org/tech-talk/computing/hardware/how-supercomputing-can-survive-beyond-moores-law
Tomi Engdahl says:
After a lapse, Intel looks to catch up with Moore’s Law again | PCWorld
http://www.pcworld.com/article/3008531/components-processors/after-a-lapse-intel-looks-to-catch-up-with-moores-law-again.html
Aims to achieve scaling and cost savings with upcoming 10-nanometer and 7-nm processes
For Intel, the temporary inability to keep pace with Moore’s Law—the foundation of its business—was a bit of an embarrassment, but the company is trying hard to catch up.
Moore’s Law is an observation that has led to faster, cheaper and smaller computers, and a concept that Intel has followed for decades. It states that the density of transistors doubles every two years, while cost per transistor declines.
Until recently, the company released chips every two years like clockwork. But making smaller chips is becoming challenging and more expensive, said Bill Holt, executive vice president and general manager for Intel’s Technology and Manufacturing Group, during the company’s annual investor day last week.
Holt acknowledged that the company could not keep up with Moore’s law, at least temporarily. Chip advancements and cost savings slowed down with the current 14-nanometer process, which is used to make its latest PC, server and mobile chips.
That was just a blip, though, and Intel will be back on track with Moore’s Law in relation to the economics and advancements in chip making, Holt said.
Intel first encountered problems advancing chip technology with a troubled transition to its 14-nm process. Manufacturing issues led to product delays, and Intel slowed chip advancement to a 2.5-year time frame.
As a result, Intel had to break away from its traditional “tick tock” model, which calls for two generations of chip technologies per manufacturing process. The company is now releasing three microarchitectures with the 14-nanometer process
Intel, however, hopes to achieve better scaling and cost savings with the upcoming 10-nanometer and 7-nm processes, Holt said. The first 10-nm chips, code-named Cannonlake, will ship in 2017.
Experts have sounded alarm bells regarding the possible collapse of Moore’s Law, and even Gordon Moore, who made the original observation in 1965, said keeping up was becoming more difficult.
“There is an increase in cost of research and development, but it’s not going to be the thing that stops us from pursuing Moore’s Law,” Holt said.
In addition, the research pipeline is full of technologies that could advance computing and chip making. Intel’s future mobile chips may have some components based on gallium nitride (GaN), which is considered a faster and more power-efficient alternative to silicon. Gallium nitride belongs to a family of exotic III-V materials, based on elements from the third and fifth columns of the periodic table.
Nanowires and new forms of memory like RRAM (resistive random access memory) and spintronics are also being researched, and could help scale down chips.
Tomi Engdahl says:
M. Mitchell Waldrop / Nature:
Semiconductor industry roadmap to abandon pursuit of Moore’s law for the first time as computing becomes increasingly mobile
The chips are down for Moore’s law
http://www.nature.com/news/the-chips-are-down-for-moore-s-law-1.19338
The semiconductor industry will soon abandon its pursuit of Moore’s law. Now things could get a lot more interesting.
Next month, the worldwide semiconductor industry will formally acknowledge what has become increasingly obvious to everyone involved: Moore’s law, the principle that has powered the information-technology revolution since the 1960s, is nearing its end.
A rule of thumb that has come to dominate computing, Moore’s law states that the number of transistors on a microprocessor chip will double every two years or so — which has generally meant that the chip’s performance will, too. The exponential improvement that the law describes transformed the first crude home computers of the 1970s into the sophisticated machines of the 1980s and 1990s, and from there gave rise to high-speed Internet, smartphones and the wired-up cars, refrigerators and thermostats that are becoming prevalent today.
None of this was inevitable: chipmakers deliberately chose to stay on the Moore’s law track. At every stage, software developers came up with applications that strained the capabilities of existing chips; consumers asked more of their devices; and manufacturers rushed to meet that demand with next-generation chips. Since the 1990s, in fact, the semiconductor industry has released a research road map every two years to coordinate what its hundreds of manufacturers and suppliers are doing to stay in step with the law — a strategy sometimes called More Moore. It has been largely thanks to this road map that computers have followed the law’s exponential demands.
Not for much longer. The doubling has already started to falter, thanks to the heat that is unavoidably generated when more and more silicon circuitry is jammed into the same small area. And some even more fundamental limits loom less than a decade away. Top-of-the-line microprocessors currently have circuit features that are around 14 nanometres across, smaller than most viruses. But by the early 2020s, says Paolo Gargini, chair of the road-mapping organization, “even with super-aggressive efforts, we’ll get to the 2–3-nanometre limit, where features are just 10 atoms across. Is that a device at all?” Probably not — if only because at that scale, electron behaviour will be governed by quantum uncertainties that will make transistors hopelessly unreliable. And despite vigorous research efforts, there is no obvious successor to today’s silicon technology.
The industry road map released next month will for the first time lay out a research and development plan that is not centred on Moore’s law. Instead, it will follow what might be called the More than Moore strategy: rather than making the chips better and letting the applications follow, it will start with applications — from smartphones and supercomputers to data centres in the cloud — and work downwards to see what chips are needed to support them. Among those chips will be new generations of sensors, power-management circuits and other silicon devices required by a world in which computing is increasingly mobile.
Tomi Engdahl says:
Moore’s Law is Over (Again)
http://hackaday.com/2016/03/01/moores-law-is-over-again/
According to this article in Nature, Moore’s Law is officially done. And bears poop in the woods.
The chips are down for Moore’s law
http://www.nature.com/news/the-chips-are-down-for-moore-s-law-1.19338
The semiconductor industry will soon abandon its pursuit of Moore’s law. Now things could get a lot more interesting.
Tomi Engdahl says:
Much more Moore’s Law, as boffins assemble atom-level transistor
We laugh at your puny 10nm process
http://www.theregister.co.uk/2015/07/21/much_more_moores_law_as_boffins_assemble_atomlevel_transistor/
The end times for Moore’s Law aren’t quite at hand, but we now know what the silicon-killer might look like: single-molecule transistors that can switch at the single electron level.
That’s what a multinational team of boffins working with the US Naval Research Laboratory (NRL) say they’ve created.
The transistor consists of a single molecule of phthalocyanine (a carbon/hydrogen/nitrogen compound) surrounded by 12 positively-charged iridium atoms, on an indium-arsenic substrate.
Tomi Engdahl says:
Graphene spintronics crowned latest Moore’s Law extender contender
It’s not just politicians and PRs who are powered by spin
http://www.theregister.co.uk/2015/04/16/graphene_spintronics_to_extend_moores_law/
Wonder material graphene could provide the basis for the future of circuitry, by using a technique known as spintronics, boffins have mused.
Spintronics uses the spin of individual electrons as the encoding method for data. This is significantly smaller than using charge, which requires thousands of electrons. Unfortunately, impurities in metal limit the size of components.
By substituting graphene for metal, Chalmers University of Technology in Sweden believes it can overcome the limitations and extend the area of a spintronics device from nanometres to millimetres. Data can be transferred from electron to electron by the magnetic effect of the spin.
Spintronics is already used in some hard drives and memory, and the University of Cambridge has investigated 3D processor design using the tech and aims to create spintronics devices by improving the purity of metals through advanced chemistry.
The short-term aim is to construct a logical component that, not unlike a transistor, is made up of graphene and magnetic materials. In the longer term things are more ambitious. Professor Dash told El Reg:
Electrons, with their spin magnetic moments aligned in one direction, can be used to store information and can be communicated over long distances as our results show. Spin magnetic moments act like memory and we can integrate memory and processor in a single device in future. ITRS is projecting spin logic and memory technology. This is called All Spin Logic.
Tomi Engdahl says:
Moore on his Law and More
Imec shares video interview from Hawaii
http://www.eetimes.com/document.asp?doc_id=1329753&
In a video interview from his home in Hawaii, Gordon Moore shared his views on the future of technology including the future of his landmark prediction that has fueled the semiconductor industry since 1965. He also showed at 87 the humble engineer can still laugh at himself.
“It would not surprise me at all if we come to end of scaling in this coming decade, but I’m impressed by engineers who keep overcoming what looks like insurmountable barriers,” he said in a video shown at the Imec Technology Forum here.
Tomi Engdahl says:
Rachel Courtland / IEEE Spectrum:
Semiconductor Industry Association: transistors to stop shrinking in 2021, but processors can continue to fulfill Moore’s Law with increased vertical density
Transistors Will Stop Shrinking in 2021, Moore’s Law Roadmap Predicts
http://spectrum.ieee.org/tech-talk/computing/hardware/transistors-will-stop-shrinking-in-2021-moores-law-roadmap-predicts
After more than 50 years of miniaturization, the transistor could stop shrinking in just five years. That is the prediction of the 2015 International Technology Roadmap for Semiconductors, which was officially released earlier this month.
After 2021, the report forecasts, it will no longer be economically desirable for companies to continue to shrink the dimensions of transistors in microprocessors. Instead, chip manufacturers will turn to other means of boosting density, namely turning the transistor from a horizontal to a vertical geometry and building multiple layers of circuitry, one on top of another.
These roadmapping shifts may seem like trivial administrative changes. But “this is a major disruption, or earthquake, in the industry,” says analyst Dan Hutcheson, of the firm firm VLSI Research. U.S. semiconductor companies had reason to cooperate and identify common needs in the early 1990’s, at the outset of the roadmapping effort that eventually led to the ITRS’s creation in 1998.
“The industry has changed,”
chip buyers and designers—companies such as Apple, Google, and Qualcomm—are increasingly dictating the requirements for future chip generations. “Once upon a time,” Gargini says, “the semiconductor companies decided what the semiconductor features were supposed to be. This is no longer the case.”
This final ITRS report is titled ITRS 2.0. The name reflects the idea that improvements in computing are no longer driven from the bottom-up, by tinier switches and denser or faster memories. Instead, it takes a more top-down approach, focusing on the applications that now drive chip design, such as data centers, the Internet of Things, and mobile gadgets.
In the coming years, before 3-D integration is adopted, the ITRS predicts that leading-edge chip companies will move away from the transistor structure used now in high-performance chips: the FinFET.
According to the roadmap, chipmakers will leave that in favor of a lateral, gate-all-around device that has a horizontal channel like the FinFET but is surrounded by a gate that extends underneath as well. After that, transistors will become vertical, with their channels taking the form of pillars or nanowires standing up on end. The traditional silicon channel will also be replaced by channels made with alternate materials, namely silicon germanium, germanium, and compounds drawn from columns III and V of the periodic table.
These changes will allow companies to pack more transistors in a given area and so adhere to the letter of Moore’s Law.
Tomi Engdahl says:
28nm Was Last Node of Moore’s Law
http://www.eetimes.com/author.asp?section_id=36&doc_id=1330366&
The industry is at a crossroads: some designs pursue scaling to 7nm while the majority stay on 28nm or older nodes.
As we have predicted more than two years back, the industry is bifurcating, and just a few products pursue scaling to 7nm while the majority of designs stay on 28nm or older nodes.
Our 2014 blog 28nm — The Last Node of Moore’s Law has now been confirmed. At the time we wrote: “After the 28nm node, we can continue to make transistors smaller, but not cheaper.” It is illustrated in the following slide, presented by Samsung at the recent Semicon West 2016.
Tomi Engdahl says:
Focus Shifts To Architectures
http://semiengineering.com/focus-shifts-to-architectures/
As chipmakers search for the biggest bang for new markets, the emphasis isn’t just on process nodes anymore. But these kinds of changes also add risks.
Chipmakers increasingly are relying on architectural and micro-architectural changes as the best hope for improving power and performance across a spectrum of markets, process nodes and price points.
While discussion about the death of Moore’s Law predates the 1-micron process node, there is no question that it is getting harder for even the largest chipmakers to stay on that curve.
“Architects used to be instrumental in defining a new family of chips,” said Mike Gianfagna, vice president of marketing at eSilicon. “Now they’re instrumental in defining new chips. The difference is that a new family of chips happens every few years. A new chip is every few months.”
There is clear evidence this shift is in well underway within big chip companies such as Intel, Samsung, AMD, and Nvidia, all of which have been wrestling with dwindling power/performance returns for several process nodes.
Nvidia’s new Parker SoC is one example. The company is pitching as a compute platform for autonomous machines of all sorts. The device is built for throughput and speed. So while it includes a 16nm finFET-based CPU, with two 64-bit “Denver” ARM cores and four A57s, it also includes a number of other chips, including a 256-core GPU, display and audio engines, a safety engine, a secure boot processor, and DDR4 memory, which is just starting to be used in servers.
At the other end of the scale, Intel rolled out a new microcontroller chip for the embedded IoT market based on the Quark architecture and designed for “duty cycle use cases,” according to Peter Barry, principal engineer at Intel.
“This is designed to run up to 10 years off a coin-cell battery,” said Barry. “The power target is 1 milliwatt active power.”
Tomi Engdahl says:
Anticipating a More Virtual Moore’s Law
http://www.eetimes.com/document.asp?doc_id=1330750&
Nicky Lu, executive director of the Taiwan Semiconductor Industry Association, is looking forward to the coming era of a “virtual” Moore’s Law, leading to a resumption of growth and profitability in the chip industry.
“There will be another 30 years of growth for the semiconductor industry,” Lu predicted in an interview with EE Times. “We are going to see ‘effective’ 1nm. Moore’s Law will become a ‘virtual’ Moore’s Law.
There is evidence that linear scaling has already reached its physical limits. “People say they are doing 10nm process modes, but you will not find any line widths at that level,” Lu says.
Departing Flatland
That’s why technology development has gone non-linear. In 2011, Intel announced its Tri-gate technology, leading the way from planar development of transistors on silicon into three dimensions. With 3D, even scaling by a factor of 0.85 results in a transistor density that is more like 0.5 scaling in two dimensions, Lu says.
Other companies have followed that trend. Toshiba built 3D NAND in 48 layers, and that memory has been used in Apple’s iPhone 7. Samsung has taken the idea a step further with the creation of a 64-layer flash memory device. The technology level was only 32nm, yet it was the virtual equivalent of 13nm, Lu notes.
Tomi Engdahl says:
Time For New Rules
Trying to fit everything into a discussion about Moore’s Law is getting ridiculous.
http://semiengineering.com/time-for-new-rules/
Is Moore’s Law dead? Brigadier General Paul Fredenburgh, commandant of the Dwight D. Eisenhower School for National Security and Resource Strategy, asked that question to four industry CEOs last week while visiting Silicon Valley with some of his students. He received four highly nuanced, if not different, answers.
From one perspective or another, all of the CEOs were all correct. It’s taking longer to move from one process node to the next, but there is significantly more compute power being offered at each new node. While that isn’t technically a doubling of transistors every two years or so, performance continues to increase an average of 30% every couple of years, either through architectural changes, new materials or different packaging approaches.
Moreover, there is no end in sight to how long this will continue. 2.5D, fan-out wafer-level packaging and full 3D will radically improve performance and lower power.
What is becoming obvious, though, is that Moore’s Law as it was originally written is getting tougher to follow. There are several reasons for this:
1. Quality is becoming a bigger issue as semiconductors begin making inroads in safety-critical and industrial markets, including autonomous vehicles, robotics and personalized medicine.
2. Market demand for moving to the next process node will continue, but the number of high-volume markets is shrinking. Companies such as Samsung, Intel and Xilinx all need increased transistor density. But for other companies, density isn’t the only way to solve their power/performance/cost issues.
3. Despite the fact that EUV is moving forward after years of delays, the big challenge with advanced nodes is time. EUV will help. But that’s only one piece of the puzzle. It takes longer to design chips at advanced nodes
While Moore’s Law is continuing in one way, it also has ended in another. And while collectively this is referred to as Moore’s Law, it bears only glimmers of resemblance to the observation first penned by Gordon Moore.
Tomi Engdahl says:
Moore’s Law: A Status Report
http://semiengineering.com/moores-law-a-status-report/
The ability to shrink devices will continue for at least four more nodes as EUV begins to ramp, but it’s just one of a growing number of options.
Moore’s Law has been synonymous with “smaller, faster, cheaper” for the past 52 years, but increasingly it is viewed as just one of a number of options—some competing, some complementary—as the chip industry begins zeroing in on specific market needs.
This does not make Moore’s Law any less relevant. The number of companies racing from 16/14nm to 7nm is higher than the initial rush to finFETs at 16/14nm, according to numerous industry sources. But that migration also needs to be put in perspective:
• Node naming became meaningless after 20nm, when foundries leveraged the same back-end of line measurements using 16/14nm finFETs. Consequently, there is no agreed upon definition for what is 10nm or 7nm. A more useful number is a comparison of performance and power by individual foundries.
• Even the strongest proponents of Moore’s Law are slowing from one node ever two years to a node every three or four years. But industry sources say a number of companies plan to skip nodes due to rising cost and complexity, so rather than turn out a production chip at every node
• Big systems companies, such as Apple and Google, are developing chips that defy standard measurements because they are application-specific and heterogeneous. In comparison, most node-specific measurements are based on ASICs, not ASSPs.
As a result, how much of the semiconductor industry is truly following Moore’s Law is no longer a straightforward exercise in counting. Logic devices are still shrinking, but not at consistent or comparable rates.
“For the past 50 years, the cheapest and easiest way to increase complexity was to shrink the feature size and grow the wafer diameter,” said Wally Rhines, chairman and CEO of Mentor, a Siemens Business. “It’s not the easiest way anymore. There is a tradeoff. We will do the things that are most economic for the capabilities we want.”
Lithography
Ever since double patterning became a requirement on the critical metal layers—namely metal 1 and metal 2 at 20nm—most experts assumed that the primary limiting factor for device shrinking would be lithography.
Fortunately, though, chipmakers have been able to extend traditional optical lithography. Using various multiple patterning schemes, chipmakers are able to split the mask and pattern each one separately. In doing so, they can extend today’s 193nm wavelength lithography to 16nm/14nm, 10nm, and even 7nm.
But at 7nm or 5nm, the pattern complexity and mask counts are becoming limiting factors for immersion/multi-patterning. A 28nm device has 40 to 50 mask layers. In comparison, a 14nm/10nm device has 60 layers, with 7nm expected to jump to 80 to 85. At 5nm, there could be 100 layers.
To simplify the flow at 7nm and/or 5nm, chipmakers have been waiting for extreme ultraviolet (EUV) lithography, a 13.5nm wavelength technology. EUV was expected at 45nm, but ran into a number of issues that only recently have been resolved.
Conclusion
Tying this all back into Moore’s Law may or may not make sense. The original observation was fairly straightforward, but it has been reinterpreted so many times that it’s hard to say what is or isn’t Moore’s Law anymore.
Tomi Engdahl says:
After Moore’s Law — What?
http://www.eetimes.com/author.asp?section_id=36&doc_id=1331698
The semiconductor industry must, at last, outgrow its obsession with pitch shrinkage, and go creative with the “heterogeneous integration of different technologies” to push economic growth.
The Intel people might as well keep insisting that Moore’s Law isn’t dead, and that their 14-nm chip can pack more transistors than their rivals. That’s Intel being Intel, with a narrative that serves its purpose.
But this story doesn’t necessarily apply to other chip companies looking for a better valuation.
The semiconductor industry must, at last, outgrow its obsession with pitch shrinkage, and go creative with the “heterogeneous integration of different technologies” to push economic growth, according to Nicky Lu, chairman, CEO and founder of Etron Technology.
In short, it’s time to stop using Moore’s Law as a security blanket.
Lu suspects that Intel wouldn’t appreciate him calling Moore’s Law “virtual.” But Moore’s Law, in his opinion, long ago stopped serving chip engineers as a technology guide. Instead, Moore’s Law has been serving the investment community as “an economic law that justifies return on investment,” he explained.
As long as investors use it as a yardstick for the semiconductor industry’s growth, chip vendors feel they can’t afford to acknowledge the obsolescence of Moore’s Law. Even Lu doesn’t exactly declare Moore’s repeal.
But it’s important for the semiconductor industry to acknowledge that the industry “changed the rules of the game” when Intel — followed by TSMC and Samsung — opted for a tri-gate structure [known as FinFET], Lu noted. “The semiconductor industry replaced line scaling (transistor size) with area scaling (miniaturizing the unit area),” thus fundamentally changing the very nature of Moore’s Law, Lu said.
In Lu’s view, it’s critical to recognize that the semiconductor industry is no longer following the original template. Moore’s Law survived not by the shrinkage of the traditional transistor, but by riding variety of techniques — including advancements in packaging.
Shift to area, volume scaling
The FinFET structure, by standing taller, created a 3D space that allows a unit area to accommodate two transistors, thus triggering semiconductor engineers to transition their focus from “transistor size to the unit area.”
Lu calls such an era of area scaling “Silicon 2.0.” In the Silicon 2.0 era, chip designers replaced the conventional planar transistor with a new 3D tri-gate transistor structure. This allowed each die area to continue to increase the number of transistors by 2X.
Memory chip companies also took up the idea of area scaling. Toshiba built 3D NAND in 48 layer. Samsung pushed further, creating a 64-layer flash memory device. By going 3D, chip makers achieved the virtual equivalent of 13nm, although the technology level they used was only 32nm, Lu explained.
Silicon 2.0 was made possible by either 3D transistors or 3D cell structures.
While area scaling became prevalent for process nodes from 22/20nm to 7nm process in the Silicon 2.0 age, the semiconductor industry also developed new ideas such as SiP (system in package), MCM (multi-chip module) and 3D stacked dice. Lu describes this as a period of “volume scaling” (as opposed to “area scaling”), and calls it “Silicon 3.0.”
The concept of heterogeneous integration, especially “a stack of chips built using different technologies,” makes Silicon 3.0 promising.
Making Lu confident of the eventual arrival of Silicon 4.0 is the integrated fan-out (InFO) wafer-level packaging technology recently achieved by the Taiwan Semiconductor Manufacturing Co.
Traditionally, chip designers placed a bond pad onto a die for external communication. In contrast, TSMC’s InFO put bonding pads outside the die to create a fan-shaped structure, eliminating the need for an interconnecting substrate.
In short, TSMC’s InFO is what enabled Apple to offer a very thin package-on-package, with a high number of I/O pads and better thermal management in the A10 applications processor in the iPhone 7. As Lu put it, TSMC’s InFO is the reason the Taiwan foundry behemoth has been able to lock Apple in as its customer for nearly all A10 processors.
How to bring back value to chips
The eternal question facing the semiconductor industry is how to regain the system and application ends’ value. Lu hopes the industry will find the answer in the age of Silicon 4.0 by pursuing heterogeneous integration technologies that work together with non-semiconductor-based applications systems.
Etron Technology is in a way already practicing what Lu preaches.
While running Etron, a leading manufacturer of buffer memories and SoCs including USB 3.0 host controller ICs, Lu has been obsessed with developing a spherical 360-degree video capture device called “Lyfie.”
The human field of view — typically limited to about 160-degrees — can be extended to a spherical 360 degrees, capturing everything around the user. With a new app, one can also record “VR-3D scenery,” thus allowing AR/VR content to be easily shared on YouTube and Facebook.
Tomi Engdahl says:
Moore’s Law: Toward SW-Defined Hardware
https://semiengineering.com/moores-law-toward-software-defined-hardware/
Part 2: Heterogeneity and architectures become focus as scaling benefits shrink; IP availability may be problematic.
Tomi Engdahl says:
Nvidia CEO Says Moore’s Law Is Dead
http://www.eetimes.com/document.asp?doc_id=1331836&
Nvidia CEO Jensen Huang has become the first head of a major semiconductor company to say what academics have been suggesting for some time: Moore’s Law is dead.
The enablers of an architectural advance every generation — increasing the size of pipelines, using superscalar tweaks and speculative execution — are among the techniques that are now lagging in the effort to keep pace with the expected 50 percent increase in transistor density each year, Huang told a gathering of reporters and analysts at the Computex show in Taipei.
“Microprocessors no longer scale at the level of performance they used to — the end of what you would call Moore’s Law,” Huang said. “Semiconductor physics prevents us from taking Dennard scaling any further.”
Dennard scaling, also known as MOSFET scaling, is based on a 1974 paper co-authored by Robert H. Dennard, after whom it is named. Originally formulated for MOSFETs, it states, roughly, that as transistors get smaller their power density stays constant, so that power use stays in proportion with area.
The diminishing returns from Moore’s Law and Dennard scaling have seen the semiconductor industry enter a mature stage in which just a handful of chipmakers can afford the multibillion dollar investments required to push the process technology forward. By now, only a few chip designers have the deep pockets to double down on fabricating silicon at the 16nm and 14nm nodes, design rules where the distinction has become increasingly blurred.
That stagnation in the progress of technology has also led to rapid industry consolidation in recent years that’s resulted in a flurry of multi-billion dollar mergers and acquisitions.
Even so, Huang suggested a modus vivendi for the semiconductor industry that plays into graphics processors, the products that Nvidia expects will enable continuing advances for years to come. Deep learning will use the processing power of GPUs that Nvidia makes as part of a new architecture that will take the company into artificial intelligence, outside the computer gaming business Nvidia has dominated, according to Huang.
Nvidia has highlighted its Volta GPU on 12nm at an 815mm die size, taking up the same surface area as 7 iPhone processors, and connected to 16GB of high bandwidth memory using Taiwan Semiconductor Manufacturing Co.’s (TSMC) silicon interposer technology. A configuration of eight of these chips in Nvidia’s DGX-1 deep learning / high performance computing machine sells for $149,000.
Tomi Engdahl says:
When Less is Moore
https://www.eetimes.com/author.asp?section_id=40&doc_id=1332671&
Remember the good old days when blindly following Moore’s Law was the blueprint to success in the semiconductor industry? These days, migrating to the next node is much more complicated — and expensive. Today’s chip companies actually have to think.
Soothsayers have been predicting its death since the ink was still drying on Gordon Moore’s 1965 paper, aptly titled “The Future of Integrated Electronics.” Yet, here it is more than 50 years later and Moore’s Law is still the governing principle of the semiconductor industry. Sort of.
The prediction that the number of transistors on a chip will double every 18 months is still taken largely as an article of faith, even though there is some debate about how long the industry can afford to keep up the pace. Virtually everyone agrees that keeping the pace with Moore’s Law is getting more difficult. And expensive.
A new paper by Syed Alam and Greg Douglass of Accenture Strategy examines the issues surrounding maintaining compliance with Moore’s Law and poses the question: Should we be blindly following it?
“It used to be that when you reduced the die size and moved on to the leading edge node you were getting the benefit of economies of scale. Now, we we get into sub-10nm, the cost is very high,”
“Our point of view is this: If you are going from 65nm to 45nm, the cost increase was marginally high. But now if you are going from 16nm to 10nm, the cost is significantly high,”
https://www.accenture.com/us-en/insight-manufacturing-sourcing-strategy-competitiveness
Tomi Engdahl says:
Do Spectre, Meltdown Mean the Death of Moore’s Law?
https://www.extremetech.com/computing/262787-spectre-meltdown-mean-death-moores-law
Spectre and Meltdown are two of the most significant security issues to surface since the beginning of this millennium. Spectre, in particular, is going to be difficult to mitigate. Both AMD and Intel will have to redesign how their CPUs function to fully address the problem. Even if the performance penalties fall hardest on older CPUs or server workloads, instead of workstation, gaming, or general-purpose compute, there are going to be cases where certain customers have to eat a performance hit to close the security gap. All of this is true. But in the wake of these revelations, we’ve seen various people opining that the flaws meant the end of either the x86 architecture or, now, that it’s the final death knell for Moore’s law.
That’s the opinion of The Register, which has gloomily declared that these flaws represent nothing less than the end of performance improvements in general purpose compute hardware. Mark Pesce writes: “[F]or the mainstay of IT, general purpose computing, last month may be as good as it ever gets.”
A short-term decline in performance in at least some cases is guaranteed. But the longer-term case is more optimistic, I’d argue, than Pesce makes it sound.
Sharpening the Argument
Before we can dive into this any further, we need to clarify something. Pesce refers to this potential end of general compute performance improvements as the end of Moore’s Law, but that’s not really true. Moore’s Law predicts that transistor density will double every 18-24 months. The associated “law” that delivered the performance improvements that went hand-in-hand with Moore’s Law was known as Dennard Scaling, and it stopped working in 2005. Not coincidentally, that’s when frequency scaling slowed to a crawl as well.
Why Meltdown, Spectre, Aren’t the End of CPU Performance Improvements
The history of computing is definitionally a history of change. Spectre and Meltdown aren’t the first security patches that can impact performance; when Data Execution Prevention rolled out with Windows XP SP2 and AMD’s Athlon 64, there were cases where users had to disable it to make applications perform properly or at desired speed. Spectre in particular may represent a larger problem, but it’s not so large as to justify concluding there are few-to-no ways of improving performance in the future.
Furthermore, the idea that general purpose compute has stopped improving is inaccurate. It’s true that the pace of improvements has slowed and that games, in particular, don’t necessarily run faster on a Core i7-8700K than on a Core i7-2600K, despite the five years between them. But if you compare CPUs on other metrics, the gaps are different.
An 18 percent average improvement over several years is a far cry from the gains we used to see, but it isn’t nothing, either. And there’s no sign that these types of gains will cease in future CPU architectures. It may take a few years to shake these bugs off, particularly given that new CPU architectures take time to design, but the long-term future of general computing is brighter than it may appear. CPU improvements may have slowed, but there’s still some gas in the tank.
Business
Death notice: Moore’s Law. 19 April 1965 – 2 January 2018
Done in by the weaponisation of optimisation, and now 2017 may be as good as it ever got
http://www.theregister.co.uk/2018/01/24/death_notice_for_moores_law/
Tomi Engdahl says:
Intel hits a wall on Moore’s Law; growth in computing power finally slows
http://www.oregonlive.com/silicon-forest/index.ssf/2018/05/intel_hits_a_wall_on_moores_la.html
Intel has been pushing the laws of physics for years. Now, physics is pushing back.
The chipmaker has again delayed the rollout of its 10-nanometer technology, the next generation of smaller, smarter, faster microprocessors. Originally expected in 2015, Intel now says the chips won’t be widely available before 2019 – and maybe not until late in the year.
A high percentage of the 10nm chips – produced at Intel’s Hillsboro research factories — are plagued with defects that render them useless. As chip features shrink to scales measured in just a few atoms, manufacturing techniques have proven unable to keep up with the rapid pace of advancement Intel has always promised.
Moore’s Law has hit a wall.
Tomi Engdahl says:
What the GlobalFoundries’ Retreat Really Means
Things will never be the same for consumer devices
https://spectrum.ieee.org/nanoclast/semiconductors/devices/what-globalfoundries-retreat-really-means
For most of our lives, the idea that computers and technology would get better, faster, and cheaper every year was as assured as the sun rising every morning. The story “GlobalFoundries Halts 7-nm Chip Development” doesn’t sound like the end of that era, but for you and anyone who uses an electronic device, it most certainly is.
Technology innovation is going to take a different direction.
GlobalFoundries was one of the three companies that made the most advanced silicon chips for other companies, such as AMD, IBM, Broadcom, Qualcomm, STM and the Department of Defense.) The other foundries are Samsung in South Korea and TSMC in Taiwan. Now there are only two pursuing the leading edge. (Intel too is pursuing these advanced chips, but its business making chips for other companies is relatively small.)
This is a big deal.
Moore’s Law ended a decade ago. Consumers just didn’t get the memo.
So, what does this mean for consumers? First, high performance applications that needed very fast computing will continue their move from your local device to the cloud, further enabled by new 5G networks. Second, while computing devices we buy will not be much faster on today’s off-the-shelf software, new features– facial recognition, augmented reality, autonomous navigation, and apps we haven’t even thought about—are going to come from software using new displays, sensors, and other still-in-prototype technology.
The world of computing is moving into new and uncharted territory. For desktop and mobile devices, the need for a “must have” upgrade won’t be for speed, but for new capabilities.
Tomi Engdahl says:
3D-Stacked CMOS Takes Moore’s Law to New Heights
https://spectrum.ieee.org/3d-cmos
When transistors can’t get any smaller, the only direction is up
Perhaps the most far-reaching technological achievement over the last 50 years has been the steady march toward ever smaller transistors, fitting them more tightly together, and reducing their power consumption. And yet, ever since the two of us started our careers at Intel more than 20 years ago, we’ve been hearing the alarms that the descent into the infinitesimal was about to end. Yet year after year, brilliant new innovations continue to propel the semiconductor industry further.
Along this journey, we engineers had to change the transistor’s architecture as we continued to scale down area and power consumption while boosting performance. The “planar” transistor designs that took us through the last half of the 20th century gave way to 3D fin-shaped devices by the first half of the 2010s. Now, these too have an end date in sight, with a new gate-all-around (GAA) structure rolling into production soon. But we have to look even further ahead because our ability to scale down even this new transistor architecture, which we call RibbonFET, has its limits.
So where will we turn for future scaling? We will continue to look to the third dimension. We’ve created experimental devices that stack atop each other, delivering logic that is 30 to 50 percent smaller. Crucially, the top and bottom devices are of the two complementary types, NMOS and PMOS, that are the foundation of all the logic circuits of the last several decades. We believe this 3D-stacked complementary metal-oxide semiconductor (CMOS), or CFET (complementary field-effect transistor), will be the key to extending Moore’s Law into the next decade.
Continuous innovation is an essential underpinning of Moore’s Law, but each improvement comes with trade-offs. To understand these trade-offs and how they’re leading us inevitably toward 3D-stacked CMOS, you need a bit of background on transistor operation.
Stacked CMOS
One commonality of planar, FinFET, and RibbonFET transistors is that they all use CMOS technology, which, as mentioned, consists of n-type (NMOS) and p-type (PMOS) transistors. CMOS logic became mainstream in the 1980s because it draws significantly less current than do the alternative technologies, notably NMOS-only circuits. Less current also led to greater operating frequencies and higher transistor densities.
To date, all CMOS technologies place the standard NMOS and PMOS transistor pair side by side. But in a keynote at the IEEE International Electron Devices Meeting (IEDM) in 2019, we introduced the concept of a 3D-stacked transistor that places the NMOS transistor on top of the PMOS transistor. The following year, at IEDM 2020, we presented the design for the first logic circuit using this 3D technique, an inverter. Combined with appropriate interconnects, the 3D-stacked CMOS approach effectively cuts the inverter footprint in half, doubling the area density and further pushing the limits of Moore’s Law.
Taking advantage of the potential benefits of 3D stacking means solving a number of process integration challenges, some of which will stretch the limits of CMOS fabrication.
We built the 3D-stacked CMOS inverter using what is known as a self-aligned process, in which both transistors are constructed in one manufacturing step. This means constructing both n-type and p-type sources and drains by epitaxy—crystal deposition—and adding different metal gates for the two transistors.
The process might seem complex, but it’s better than the alternative—a technology called sequential 3D-stacked CMOS. With that method, the NMOS devices and the PMOS devices are built on separate wafers, the two are bonded, and the PMOS layer is transferred to the NMOS wafer. In comparison, the self-aligned 3D process takes fewer manufacturing steps and keeps a tighter rein on manufacturing cost, something we demonstrated in research and reported at IEDM 2019.
Importantly, the self-aligned method also circumvents the problem of misalignment that can occur when bonding two wafers. Still, sequential 3D stacking is being explored to facilitate integration of silicon with nonsilicon channel materials, such as germanium and III-V semiconductor materials. These approaches and materials may become relevant as we look to tightly integrate optoelectronics and other functions on a single chip.
The new self-aligned CMOS process, and the 3D-stacked CMOS it creates, work well and appear to have substantial room for further miniaturization. At this early stage, that’s highly encouraging. Devices having a gate length of 75 nm demonstrated both the low leakage that comes with excellent device scalability and a high on-state current. Another promising sign: We’ve made wafers where the smallest distance between two sets of stacked devices is only 55 nm. While the device performance results we achieved are not records in and of themselves, they do compare well with individual nonstacked control devices built on the same wafer with the same processing.
The Future of Moore’s Law
With RibbonFETs and 3D CMOS, we have a clear path to extend Moore’s Law beyond 2024.
With the move to FinFETs, the ensuing optimizations, and now the development of RibbonFETs and eventually 3D-stacked CMOS, supported by the myriad packaging enhancements around them, we’d like to think Mr. Moore will be amazed yet again.