Electronics trends for 2016

961 Comments

1. October 7, 2016 at 12:47 pm

   Tomi Engdahl says:

   Passive probes work up to 9 GHz
   http://www.edn.com/electronics-products/other/4442794/Passive-probes-work-up-to-9-GHz?_mc=NL_EDN_EDT_EDN_today_20161006&cid=NL_EDN_EDT_EDN_today_20161006&elqTrackId=a746df7f23f34174bfd62301019cb798&elq=940ea477aa64463d9a9d75d00ac8fe3e&elqaid=34232&elqat=1&elqCampaignId=29884

   PicoConnect 900 series passive test probes from Pico Technology allow minimally invasive browsing of broadband signals or data streams out to 9 GHz or 18 Gbps. With tip capacitance of less than 0.4 pF and ground-referred loading of 220 Ω to 910 Ω, the devices are overall less invasive than most existing and more costly probes, according to the manufacturer.

   Able to interface with oscilloscopes and spectrum analyzers with 50-Ω inputs, the PicoConnect probes allow engineers to browse circuitry, backplanes, interconnects, and systems, typically without interrupting their function. They are ratio-compensated for their typical application—the probing of transmission lines and ports between 40 Ω and 100 Ω (80 Ω to 200 Ω differential)—and achieve measurement accuracy down to a few percent.

   Probe division ratios of divide-by 5, divide-by 10, and divide-by 20 are available in 12 probe models.

   Prices start at $699.

   Reply
2. October 10, 2016 at 9:58 am

   Tomi Engdahl says:

   Researchers use novel materials to build smallest transistor with 1-nanometer carbon nanotube gate
   http://phys.org/news/2016-10-materials-smallest-transistor-nanometer-carbon.html

   For more than a decade, engineers have been eyeing the finish line in the race to shrink the size of components in integrated circuits. They knew that the laws of physics had set a 5-nanometer threshold on the size of transistor gates among conventional semiconductors, about one-quarter the size of high-end 20-nanometer-gate transistors now on the market.

   Some laws are made to be broken, or at least challenged.

   A research team led by faculty scientist Ali Javey at the Department of Energy’s Lawrence Berkeley National Laboratory (Berkeley Lab) has done just that by creating a transistor with a working 1-nanometer gate. For comparison, a strand of human hair is about 50,000 nanometers thick.

   “We made the smallest transistor reported to date,” said Javey, a lead principal investigator of the Electronic Materials program in Berkeley Lab’s Materials Science Division. “The gate length is considered a defining dimension of the transistor. We demonstrated a 1-nanometer-gate transistor, showing that with the choice of proper materials, there is a lot more room to shrink our electronics.”

   The key was to use carbon nanotubes and molybdenum disulfide (MoS2), an engine lubricant commonly sold in auto parts shops.

   Read more at: http://phys.org/news/2016-10-materials-smallest-transistor-nanometer-carbon.html#jCp

   Reply
3. October 10, 2016 at 12:13 pm

   Tomi Engdahl says:

   X-Fab to Swallow Altis Semiconductor
   http://www.eetimes.com/document.asp?doc_id=1330569&

   Analog, mixed-signal and MEMS foundry group X-Fab Silicon Foundries AG (Erfurt, Germany) is set to announced the assets of Altis Semiconductor (Corbeil-Essonne, France) out of insolvency proceedings.

   The price being paid was not disclosed.

   Altis is a former IBM wafer fab in the Paris region about 40 kilometers south of the center of Paris. Altis runs 200mm diameter wafers down to about 130nm CMOS process.

   Reply
4. October 10, 2016 at 12:14 pm

   Tomi Engdahl says:

   TSMC Staffing R&D for 3nm Process
   http://www.eetimes.com/document.asp?doc_id=1330570&

   Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC) will actively develop 5-nanometer process technology, while dedicating between 300 and 400 R&D personnel in developing a 3-nanometer process, ultimately aiming at the 1-nanometer manufacturing process, reports Taiwanese magazine CTimes.

   In an interview, Dr. Mark Liu, President and Co-Chief Executive Officer of TSMC, said the company will use its three-dimensional stacked architecture technology to break the limitation of Moore’s law and move toward the 3nm manufacturing node.

   Liu stressed that TSMC has established the complete ecosystems

   Reply
5. October 10, 2016 at 12:20 pm

   Tomi Engdahl says:

   Nobel Prize: Why Superconductivity?
   Topological material phases targeted
   http://www.eetimes.com/author.asp?section_id=36&doc_id=1330586&

   Why you should care about superconductivity and this year’s Nobel Prize in Physics.

   The importance of research on topological phase changes of matter — such as the instantaneous quantum-state change to superconductivity — has been recognized by the Nobel Prize committee of The Royal Swedish Academy of Sciences (Stockholm). Professor David Thouless at the University of Washington (Seattle) received half the $932 thousand, while the remaining $466 thousand was split between professor Duncan Haldane at Princeton University (NJ) and professor Michael Kosterlitz at Brown University (Providence, RI).

   “Essentially what these Nobel prize winners did was squish down to two-, and in some cases even one-dimension, problems in superconductivity thereby making it possible to solve some of these problems that were too complicated to understand in three-dimensions,”

   Today semiconductors are explained and manipulated according to their crystalline lattice structure, according to Greene, by which you can calculate their electrical properties. However, this kind of analysis does not work when the important properties are the result off electron-to-electron interactions.

   “High temperature superconductors are unconventional because they have the electrons interacting with each other in a way that is not well understood — its a hard problem,”

   “Topological materials are more conductive than normal metal and their magnetic properties make them a possibility for new types of higher density memory devices. There are over 50 families of topological materials, some of them organic,”

   Reply
6. October 11, 2016 at 7:53 am

   Tomi Engdahl says:

   MRAM moves to 20nm
   http://www.edn.com/electronics-products/other/4442796/MRAM-moves-to-20nm?_mc=NL_EDN_EDT_EDN_productsandtools_20161010&cid=NL_EDN_EDT_EDN_productsandtools_20161010&elqTrackId=77b4c9c1766a476983ac1d073ea10ae9&elq=6b2f8884a03e4535a665b413950ea62d&elqaid=34286&elqat=1&elqCampaignId=29922

   Spin Transfer Technologies Inc. (Fremont Calif.), a developer of MRAM technology, has announced it has developed magnetic tunnel junctions down to 20nm in width and has initiated a sampling program.

   STT has been pioneering something called orthogonal spin transfer (OST) MRAM in which the magnetic fields of the pinned and variable magnetic layers are perpendicular to the plane of the surface of the wafer. One of STT’s developments is to put an additional spin polarizing filter above the variable magnetic field layer.

   MRAM is also being investigated elsewhere and is now being tipped as the prime embedded non-volatile memory option at 28nm (see MRAM is leading embedded NVM race, says IMEC researcher, and, Globalfoundries offers embedded MRAM on 22nm FDSOI).

   ST-MRAM beats DRAM & SRAM for cache in many applications and is superior to embedded flash at 28nm and below where it demonstrates 1000x lower write energy and can be implemented in BEOL for easy integration with analog, high-voltage and RF. Resistive RAM (ReRAM) alternatives have yet to demonstrate reliability.

   Reply
7. October 11, 2016 at 7:57 am

   Tomi Engdahl says:

   RMS detector computes real power of an RF signal
   http://www.edn.com/electronics-products/electronic-product-reviews/other/4442820/RMS-detector-computes-real-power-of-an-RF-signal?_mc=NL_EDN_EDT_EDN_productsandtools_20161010&cid=NL_EDN_EDT_EDN_productsandtools_20161010&elqTrackId=492ceb8e49f84f8a9573867b7706cfb3&elq=6b2f8884a03e4535a665b413950ea62d&elqaid=34286&elqat=1&elqCampaignId=29922

   The fast-evolving wireless network market is speeding toward 5G access that will bring far larger internet traffic than ever imagined before. LTE-A and 4G can’t even come close to providing the needed bandwidth requirements. Microwave wireless backhaul links will need to advance as well in bandwidth because of this large increase in data capacity that will come with 5G.

   Frequency bands for 5G access will be 8, 14, 18, 24, 28 GHz and far higher, especially in the higher frequency microwave backhaul needs. Bandwidths will need to be in the 1 and 2 GHz regions, pushing radio designs to the edge of the envelope.

   In addition, high order QAM modulation in the region of 2048QAM will be realized. Multi-tone OFDM (Orthogonal Frequency Division Multiplexing) will also help make more efficient use of the spectrum. High order QAM modulation has its problems, like very high peak-to-average waveforms. If you try to measure only the peak power, even adding correction, you will not have a very accurate reading because this does not give you the true power in the waveform. Also, if there are multiple carriers, the peak power does not account for the tonal power in a multi-carrier signal. Errors can add up to several dB. So the need for adding lots of extra headroom for the actual peaks leads to lower transmission power available to the RF amplifier which reduces range and poor reception.

   Traditionally, microwave Schottky diodes were employed in designs to measure the peak power at frequencies above 10 GHz.

   Schottky diodes perform well from 0 dBm to +20 dBm, but since Schottkys have an exponential response, lower signals will be less accurate.

   Linear Technology, soon to be a part of Analog Devices.

   an RMS detector saves the day because they use a root-mean-square function internal to the chip that computes real power of an RF signal. The averaging is done and the DC output will accurately represent the true power of the RF signal within a few tenths of a dB even down to low signal levels–no correction factors, no extra headroom. This solves the need for a Schottky at lower levels.

   Linear Technology’s LTC5596, a high frequency, wideband and high dynamic range RMS power detector, will give accurate, true power measurement of RF and microwave signals independent of modulation and waveforms. The IC responds in an easy-to-use log-linear 29mV/dB scale to signal levels from –37dBm to –2dBm, with an accuracy better than ±1dB error over the full operating temperature range and RF frequency range, good for 5G wireless access from 200MHz to 30GHz with a flat response of ±1dB. Designers can get a wider frequency range from 100MHz to 40GHz with slightly reduced accuracy at the frequency extremes. The IC’s RF input is internally matched at 50Ω from 100MHz to 40GHz.

   RMS detector shines by performing an analog root-mean-square computation of the waveform, and then averages the result to derive a true power representation of the input signal, regardless of its modulation, number of carriers, and varying amplitudes. The ability to measure the true power is critical for equipment manufacturers to set the proper transmit power to ensure maximum transmission distance and improved transmit range while remaining compliant with regulatory power limits.

   Due to a wide bandwidth, the detector can work seamlessly with a minimum calibration being necessary across multiple frequency bands using a common design.

   The IC operates from a single 3.3V supply, while drawing a nominal supply current of 30mA

   Reply
8. October 11, 2016 at 8:20 am

   Tomi Engdahl says:

   Xilinx bolsters low-end & midrange offerings
   http://www.edn.com/electronics-products/other/4442780/Xilinx-bolsters-low-end—midrange-offerings?_mc=NL_EDN_EDT_EDN_today_20161010&cid=NL_EDN_EDT_EDN_today_20161010&elqTrackId=40199c9bc9884558b86897658e14ff37&elq=db66a391d2644c798950cb756a5e6d9a&elqaid=34281&elqat=1&elqCampaignId=29917

   Aiming at applications including embedded vision and industrial IoT, Xilinx has added parts in what it terms its cost-optimized offering, across its Spartan, Artix, and Zynq families, for any-to-any connectivity, sensor fusion, precision control, image processing, analytics, safety, and security.

   Return of the Spartans
   The company says that this portfolio expansion, “…now including the Spartan-7 family, additional Artix-7 products, and Zynq-7000 single core devices, offers the most compelling performance-per-watt solutions in the industry and expanded processor scalability all at lower cost entry points.”

   The Spartan-7 family is positioned as the only 28nm-based FPGA in an 8 × 8 mm package, enabling the portfolio’s most cost-efficient connectivity solution for both legacy and cutting-edge interfaces, while delivering the highest performance-per-watt sensor fusion and precision control in a small form factor. The new Spartans use half the power yet provide 30% more performance compared to the previous generation, and come in 6 – 102 kLE sizes with up to 400 I/Os.

   Reply
9. October 11, 2016 at 9:02 am

   Tomi Engdahl says:

   The first integrated into the FPGA chip

   Achronix is ​​known as a small FPGA manufacturer, a high-speed Speedster22i circuits have been delivered on the market since 2013. Now, however, the company makes a revolutionary takeover of the area by presenting the world’s first embeddable system circuit FPGA.

   When the FPGA portion embedded into the system circuit, achieved significantly better performance than when using separate chips. Signals travel faster than 10 per cent, 10 per cent of the delay is shortened, power consumption will shrink by as much as half the cost of manufacturing are reduced to 90 percent.

   - The main reason is probably the market. Altera and Xilinx wanted to focus on large, monolithic FPGA development, because it is they perform.

   There is a definite reason why many heavy calculation of a shift device-based acceleration. Microprocessors are falling in, and, for example, many complex functions have to be divided into smaller parts. Whipped up what accounting can be divided into parallel cores, which significantly improves performance. In particular, this applies to all DSP-intensive computation, such as, say, the processing of data packets in a data center cards.

   For acceleration of calculations has been used, for example, modified graphics processors and now also increasingly FPGA-circuits due to their programmability. The processor speed integrated server core block is a sort of ideal accelerator, because it increases the performance with low power consumption and a very low added cost.

   Source: http://etn.fi/index.php?option=com_content&view=article&id=5198:ensimmainen-sulautettava-fpga-piiri&catid=13&Itemid=101

   More:
   Introducing Speedcore™ eFPGAs
   http://www.achronix.com/product/speedcore/

   Reply
10. October 11, 2016 at 2:09 pm

    Tomi Engdahl says:

    Solving signal integrity problems at very high data rates
    http://www.edn.com/design/pc-board/4442805/Solving-signal-integrity-problems-at-very-high-data-rates?_mc=NL_EDN_EDT_EDN_today_20161011&cid=NL_EDN_EDT_EDN_today_20161011&elqTrackId=9f3e4d964ac14e25a81d03fc1e68d857&elq=88cece835f3042909dbb0b1389f87c6c&elqaid=34303&elqat=1&elqCampaignId=29932

    The good news about the Internet of Things (IoT) is that it demonstrates just how pervasive high-speed communication technology has become. Addressing software issues within the IoT is pretty straight forward—create some code that people can readily download to their hardware devices to maintain the operating integrity of their various communication devices.

    Addressing hardware issues is not so simple. Even experienced hardware developers are challenged in addressing these issues. Part of the problem is attributable to the nature of hardware technology itself. Printed circuit boards (PCBs) and the various other pieces of hardware associated with them have essentially “run out of gas”. Moreover, wringing the last ounce of performance capability out of these devices often requires unprecedented and very creative engineering efforts.

    The state of technology

    At the start of 21st century, providers of equipment for the Internet struggled to design large routers and switches containing backplanes and plug-in line cards that had long internal connections running at 3.125 Gb/s. The primary concern was how to manage loss in those long paths.

    Fast forward to 2016 and the picture has changed radically. Manufacturers of the semiconductors used in route processors and switch ICs have managed to engineer them so they operate at speeds as high as 32 Gb/s with a very high tolerance for loss along the signal paths. The ICs of 2001 could tolerate as little as 10 dB of loss in the signal path at 3.125 Gb/s. The ICs of 2016 can tolerate as much as 38 dB of loss at 32 Gb/s.

    The first problem (excess capacitance in the plated through holes) has been dealt with by using a technique called back-drilling to remove the excess capacitance of the connector plated through holes that extend below the layer in which the signal traces are routed. I

    The second problem (excess crosstalk) has been dealt with by routing the signals farther and farther apart from each other so this problem is minimized. However, when receive signals can be only 2 or 3% the amplitude of transmit signals this becomes mechanically very difficult to accomplish when routing signals on the same layer in the vicinity of the connectors.

    The third of these (skew or difference in travel time in the two sides of a differential pair), is a result of the uneven distribution of the glass in the woven cloth and the resin used to bind the composite together.

    Many techniques have been proposed to minimize the effect of skew. The two most common methods in use are:

    Routing the signals at an angle to the glass weave hoping that the irregularities are evened out between the two sides of the pair.

    Using a glass weave style that has the glass evenly spread out to minimize variation in the glass weave over which signals travel.

    Conclusion

    Advances in semiconductor technology are making it possible to connect components in products such as switches and routers at rates as high as 56 Gb/s. As these higher speeds are achieved, micro-scale variations in the materials used to fabricate PCBs and backplanes can significantly degrade signals. Among the problems encountered are loss, skew, crosstalk, and degradation due to the parasitic capacitance of the plated-though holes required to mount the connectors to the backplanes and daughter cards.

    By using twinax cables to make these connections instead of implementing them in PCBs and backplanes with traditional traces, skew, crosstalk, and degradation from the plated-though holes can be virtually eliminated. Due to the ultra-low loss of the twinax cables, path lengths can be longer, or the frequency of operation can extend much higher than is possible with the laminate systems currently available.

    Reply
11. October 11, 2016 at 3:23 pm

    Tomi Engdahl says:

    Intel is shipping an ARM-based FPGA. Repeat, Intel is shipping an ARM-based FPGA
    Nobody tell Linux, okay?
    http://www.theregister.co.uk/2016/10/10/intel_stratix_10_arm_based_fpga/

    Intel’s followed up on its acquisition of Altera by baking a microprocessor into a field-programmable gate array (FPGA).

    The Stratix 10 family is part of the company’s push beyond its stagnating PC-and-servers homeland into emerging markets like high-performance computing and software-defined networking.

    Intel says the quad-core 64-bit ARM Cortex-A53 processor helps position the device for “high-end compute and data-intensive applications ranging from data centres, network infrastructure, cloud computing, and radar and imaging systems.”

    Compared to the Stratix V, Altera’s current generation before the Chipzilla slurp, Intel says the Stratix 10 has five times the density and twice the performance; 70 per cent lower power consumption at equivalent performance; 10 Tflops (single precision); and 1 TBps memory bandwidth.

    The devices will be pitched at acceleration and high-performance networking kit.

    The Stratix 10 “Hyperflex architecture” uses bypassable registers – yes, they’re called “Hyper-Registers”, which are associated with individual routing segments in the chip, and are available at the inputs of “all functional blocks” like adaptive logic modules (ALMs), embedded memory blocks, and digital signal processing (DSP) blocks.

    https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/wp/wp-01220-hyperflex-architecture-fpga-socs.pdf

    Reply
12. October 11, 2016 at 3:46 pm

    Tomi Engdahl says:

    Better DRAM with No New Materials
    http://www.eetimes.com/document.asp?doc_id=1330611&

    Many innovations in memory, whether it’s a new technology or an existing one, come as a result of new materials, but one company is looking to improve on current DRAM technology without new materials or complex process flows.

    Kilopass Technology, Inc., maker of one-time programmable (OTP) memory and provider of intellectual property for semiconductor embedded non-volatile memory (NVM), has introduced its Vertical Layered Thyristor (VLT) technology for DRAM applications. VLT eliminates the need for DRAM refresh, is compatible with existing process technologies and offers significant other benefits including lower power, better area efficiency and compatibility, company CEO Charlie Cheng said in an interview with EE Times.

    Since VLT does not require complex performance- and power-consuming refresh cycles, he said the main benefit of a VLT-based DDR4 DRAM is that it lowers standby power by 10 time when compared with conventional DRAM at the same process node.

    Reply
13. October 12, 2016 at 10:17 am

    Tomi Engdahl says:

    Too Fast to See—Exploring Propagation Delay
    https://www.eeweb.com/blog/eeweb/too-fast-to-seeexploring-propagation-delay

    When you flick a light switch, the lights turn on instantaneously because electricity moves at the speed of light, right? Anyone who has taken a basic circuits or physics class knows this isn’t the case—the actual movement of electrons is quite slow. The electromotive force moves quickly, meaning those electrons start and stop moving quickly but even that is not at the speed of light.

    Propagation delay is the time it takes for a signal to move from one point to another, usually measured in picoseconds per inch. This delay is dependent on the material through which the signal is being propagated, as well as the dielectric surrounding it, but is not related to frequency in any way. So, using the light switch as an example, if we assume a 200 picosecond/inch delay between the switch and the light, 30 feet of wire between switch and light, there will be a 30 feet x 12 inches x 200 picosecond delay, giving a 72 nanosecond delay. While this is based on some assumptions about length and propagation delay of the wire, it gives at least a general timeframe that it takes for the signal to reach the light bulb.

    On high frequency boards, it is very common to see traces that seem to zigzag for no apparent reason. This is purely for propagation delay.

    Reply
14. October 12, 2016 at 10:40 am

    Tomi Engdahl says:

    Power/Performance Bits: Oct. 11
    http://semiengineering.com/powerperformance-bits-oct-11/

    Getting to 1nm

    Researchers at the Lawrence Berkeley National Laboratory, UC Berkeley, University of Texas at Dallas, and Stanford University created a transistor with a working 1nm gate from carbon nanotubes and molybdenum disulfide (MoS2).

    “The semiconductor industry has long assumed that any gate below 5 nanometers wouldn’t work, so anything below that was not even considered,” said first author Sujay Desai, a graduate student at Berkeley Labs. “This research shows that sub-5-nanometer gates should not be discounted. Industry has been squeezing every last bit of capability out of silicon. By changing the material from silicon to MoS2, we can make a transistor with a gate that is just 1nm in length, and operate it like a switch.”

    Both silicon and MoS2 have a crystalline lattice structure, but electrons flowing through silicon are lighter and encounter less resistance compared with MoS2. That is a boon when the gate is 5nm or longer. But below that length, a quantum mechanical phenomenon called tunneling kicks in, and the gate barrier is no longer able to keep the electrons from barging through from the source to the drain terminals.

    The work is still a proof of concept, said Berkeley Lab faculty scientist Ali Javey. “We have not yet packed these transistors onto a chip, and we haven’t done this billions of times over. We also have not developed self-aligned fabrication schemes for reducing parasitic resistances in the device. But this work is important to show that we are no longer limited to a 5nm gate for our transistors. Moore’s Law can continue a while longer by proper engineering of the semiconductor material and device architecture.”

    Quantum photonic circuits

    Scientists at the Westphalian Wilhelm University of Münster (WWU) and the Karlsruhe Institute of Technology (KIT) succeeded in placing a complete quantum optical structure on a chip.

    “Experiments investigating the applicability of optical quantum technology so far have often claimed whole laboratory spaces,”

    Reply
15. October 12, 2016 at 10:43 am

    Tomi Engdahl says:

    System Bits: Oct. 11
    http://semiengineering.com/system-bits-oct-11/

    Carbon Is So 2015
    Researchers at MIT have created a supercapacitor that relies on a material other than carbon.

    This new class of materials, called metal-organic frameworks (MOFs), are a porous and sponge-like, according to MIT, tthereby providing a much larger surface area than carbon. As with most things electrical, more surface area is essential for superconductors.

    The problem the research team faced was that MOF materials by nature are not electrically conductive, but they do conduct ions that carry an electric charge. Moreover, they can be manufactured at a much lower temperature than carbon nanotubes or graphene, which are the current favorites in the superconductor world.

    New kind of supercapacitor made without carbon
    Energy storage device could deliver more power than current versions of this technology.
    http://news.mit.edu/2016/supercapacitor-made-without-carbon-1010

    Reply
16. October 12, 2016 at 10:47 am

    Tomi Engdahl says:

    System Bits: Oct. 11
    http://semiengineering.com/system-bits-oct-11/

    Cleaner Renewable Energy
    Unless you’ve been hiding deep in the shadows you’ve probably heard about perovskite materials. They’re cheap, relatively easy to work with, and they are almost as good as silicon in capturing solar energy.

    A big problem, though, is toxicity. Until now, all of the materials used as solvents have been highly toxic. But scientists at Oxford University say they have made a breakthrough, based on a combination of methylamine and acetonitrile, which can be developed at a low boiling point with low viscosity and still quickly crystalize perovskite films at room temperature. They say this could be used to help coat large solar panels at a much lower cost than vapor deposition, which is the other alternative.

    Non-toxic solvent removes barrier to commercialisation of perovskite solar cells
    http://www.ox.ac.uk/news/2016-10-05-non-toxic-solvent-removes-barrier-commercialisation-perovskite-solar-cells

    Scientists at Oxford University have developed a solvent system with reduced toxicity that can be used in the manufacture of perovskite solar cells, clearing one of the barriers to the commercialisation of a technology that promises to revolutionise the solar industry.

    Reply
17. October 12, 2016 at 1:26 pm

    Tomi Engdahl says:

    ‘Edible’ Electronics Can Be Powered by Melanin
    http://www.designnews.com/author.asp?section_id=1386&doc_id=281761&

    Medical devices are becoming smaller and more advanced, with researchers inventing tiny nano-scale devices that can even be ingested for internal monitoring or medication release. These devices wil,l of course, require power sources that also are safe for ingestion or implantation, and engineers are eyeing new forms of batteries and energy-harvesting methods to solve this problem.

    One of the latest solutions comes from researchers at Carnegie Mellon University, who have discovered that melanin—a natural pigment found in the human skin—demonstrates a chemical structure well-suited to creating batteries based on natural melanin pigments. These batteries could become future power sources for a new class of medical devices called “edible electronics,” said Chris Bettinger, Carnegie Mellon associate professor and one of the researchers on the project.

    Reply
18. October 12, 2016 at 2:42 pm

    Tomi Engdahl says:

    The ever-moving goalposts of efficiency standards for external power supplies
    http://www.edn.com/electronics-blogs/power-forward/4442819/The-ever-moving-goalposts-of-efficiency-standards-for-external-power-supplies?_mc=NL_EDN_EDT_EDN_today_20161012&cid=NL_EDN_EDT_EDN_today_20161012&elqTrackId=223114ce4ae84a1cbed183acac3dbe1a&elq=56eaa3fff0144487b1eb76c9f31f701a&elqaid=34321&elqat=1&elqCampaignId=29947

    In February this year, the US Department of Energy (DoE) enacted legislation requiring external power adapters marketed in the USA to comply with international Level VI eco-design specifications. The dust has barely settled, and already the EU is upping the ante by publishing its Code of Conduct (CoC) Tier 2 efficiency standards.

    There is some history behind this leapfrog-style progress in environmental legislation. About two years ahead of the US move to Level VI, the EU in 2014 introduced CoC Tier 1 as a voluntary standard. CoC Tier 1 specifies efficiency and power limits that are only slightly less stringent than Level VI, but also requires an extra efficiency measurement to be taken at 10% of full load.

    For the full story, we have to look back to the early 1990s and the US ENERGY STAR initiative.

    In practice this means that OEMs who want to avoid the complexity of having different product configurations for different geographic markets need to ensure their external power supplies meet the latest and most stringent standards worldwide. EPS manufacturers, for their part, must employ leading-edge design techniques to comply with evolving standards and keep their product lines ahead of the game.

    The CoC Tier 2 standard significantly tightens the limits defined by DoE Level VI. A supply with a nameplate rating between 49 W and 250 W, which has a maximum no-load power of 210 mW under Level VI rules and 250 mW under CoC Tier 1, will have to consume less than 150 mW to satisfy Tier 2.

    Reply
19. October 13, 2016 at 12:18 pm

    Tomi Engdahl says:

    AC/DC Power Supplies: Four Questions to Ask
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1330587&

    1. Can you connect the power supplies in parallel to provide higher output power or configure them to provide multi-phase or split phase outputs?

    2. What voltages and currents can I expect from modern power supplies?

    Voltage ranges have increased, particularly in military/avionics applications. Examples include:

    Standard avionics power plant simulation, which currently runs from 360 Hz to about 800 Hz.
    Simulation of next-generation avionics power plants already requires 1200 Hz and that will increase. Power at these frequencies is needed to test the electronics that will connected to those power plants.
    Torpedo alternator simulation, 3 kHz-4kHz, is needed to test the downstream power converters and electronics that will be connected to those alternators.

    Instead of the traditional 150 and 300 VAC ranges, the latest generation of AC/DC supplies now produce voltage ranges of 200 and 400 VAC, as well as DC voltages of 250 VDC and 500 VDC. These higher DC voltages come in handy in many applications. For example, MIL-STD-704, Test Method HDC302 requires voltage transients up to 475 VDC.

    3. I need to test my equipment at multiple ranges. What do I need?

    4. What features should I look for?
    Many of today’s AC/DC power sources have features that make testing easier and more effective. These include touchscreen displays dashboards and control panels where you can save your GPIB address or set your RS-232 parameters, or set up your LAN connection.

    Reply
20. October 13, 2016 at 3:25 pm

    Tomi Engdahl says:

    Silicon Labs Acquires Leading RTOS Company Micrium
    http://news.silabs.com/press-release/corporate-news/silicon-labs-acquires-leading-rtos-company-micrium?utm_source=newsletter&utm_medium=email&utm_campaign=september2016newsletter&mkt_tok=eyJpIjoiWVRRNE1XTXpOV1poWmpBdyIsInQiOiJEQmVqYlwvZ3NRR09yMXlBVTdMc2oxaDZQcEEwbDI0QjcrZkxwTVBsOXNzR1ozWjRZa3JKUHJNNmZSS1NrTmttZWhYNndtM3lQbEhvSnJXdnBWY2V0QTJ5XC9LdzE1ZDRVb2x3WnR4bTdBOVNvPSJ9

    Developers Gain Complete Embedded Solution for the IoT Combining RTOS with Multiprotocol Silicon, Tools and Software Stacks

    acquisition of Micrium, a leading supplier of real-time operating system (RTOS) software for the Internet of Things (IoT). This strategic acquisition helps simplify IoT design for all developers by combining a leading, commercial-grade embedded RTOS with Silicon Labs’ IoT expertise and solutions. Micrium’s RTOS and software tools will continue to be available to all silicon partners worldwide, giving customers a wide range of options, even when using non-Silicon Labs hardware. Micrium will continue to fully support existing as well as new customers.

    “With an installed base of millions of devices, Micrium’s RTOS software has established itself as one of the most reliable and trusted platforms over the last 10 years,”

    Micrium’s widely deployed RTOS software has been ported to more than 50 microcontroller architectures and has a global footprint with more than 250,000 downloads across all embedded vertical markets, with solutions certified to meet safety-critical standards for medical electronics, avionics, communications, consumer electronics and industrial control.

    Reply
21. October 14, 2016 at 10:06 am

    Tomi Engdahl says:

    Kif Leswing / Business Insider:
    Apple has hired several high-level employees, including the COO, from GPU maker Imagination Technologies since July, after backing out of an acquisition — Apple is hiring a lot of talent from British chip designer Imagination Technologies, the company that provides the graphics processor for the iPhone 7.

    One of Apple’s most important technology partners is suffering a brain drain — to Apple
    http://www.businessinsider.com/apple-poaches-imagination-technologies-coo-2016-10?op=1%3fr=US&IR=T&IR=T

    Apple is hiring a lot of talent from British chip designer Imagination Technologies, the company that provides the graphics processor for the iPhone 7.

    Apple confirmed in March through the London Stock Exchange that it had discussions to buy Imagination Technologies but that it ultimately did not make an offer for the chip company.

    Reply
22. October 14, 2016 at 10:38 am

    Tomi Engdahl says:

    Power Limits Of EDA
    http://semiengineering.com/power-limits-of-eda/

    Tools aid with power reduction, but they can only tackle small savings in a locality. To do more would require a new role for the EDA industry.

    But there are limits to the amount of help that EDA can provide with power optimization. Power is not just an optimization problem. It is a design problem, and EDA has never been much help with design. The value of EDA comes from the automation and optimization of implementing a design once it has been designed. For power, that could be too late.

    “Anyone building big chips will hit thermal walls just due to leakage,” says Drew Wingard, chief technology officer at Sonics. “They have to do more aggressive things than they have done in the past. Smaller chips that are battery-powered have to do it for other reasons because they want ever smaller form factors with lighter batteries to support those form factors. So it is inevitable. Intel ran into the power wall 10 or more years ago, and we all said we would focus on power. But we didn’t really do it. The honeymoon is over.”

    Reply
23. October 14, 2016 at 11:53 am

    Tomi Engdahl says:

    Putting power forward
    http://www.edn.com/design/power-management/4442818/Putting-power-forward?_mc=NL_EDN_EDT_EDN_today_20161013&cid=NL_EDN_EDT_EDN_today_20161013&elqTrackId=afab5c0c5c24479da138a39526b2a519&elq=6ebf6405b46546cb90f26f0714d1a943&elqaid=34344&elqat=1&elqCampaignId=29968

    Designers of advanced computing systems are no longer able to consider the power supply as a “black box” that can be plugged in at the end of the project. Giving due consideration to power design at an early stage is essential given the growing complexity of server boards, demands for greater power and efficiency, and the need to plan for multiple product generations. On the other hand, engineers also need flexible power solutions in order to respond to system design changes and adopt a platform approach to the power design, which can help streamline future development. The ability to easily configure, control and monitor power delivery functions is a valuable characteristic enabled by digitally configurable power modules.

    Designers of advanced computing systems are no longer able to consider the power supply as a “black box” that can be plugged in at the end of the project. Giving due consideration to power design at an early stage is essential given the growing complexity of server boards, demands for greater power and efficiency, and the need to plan for multiple product generations. On the other hand, engineers also need flexible power solutions in order to respond to system design changes and adopt a platform approach to the power design, which can help streamline future development. The ability to easily configure, control and monitor power delivery functions is a valuable characteristic enabled by digitally configurable power modules.

    Pressure on power design

    High-performance computer boards such as data-center servers present increasingly complex routing and component-placement challenges as designers seek to maximize data-processing and storage capabilities in the minimum possible area to comply with the standard rack dimensions. With a mix of advanced processors, ASICs and FPGAs that feature large numbers of I/Os and multiple power domains, the PCB can incorporate 20 layers or more for timing-critical high-speed signal traces and power distribution.

    Up to 40 or 50 power rails can be needed, which call for a large number of point-of-load (POL) converters that are powered by intermediate bus converters (IBCs) fed by an AC/DC front-end power supply

    The design of the power-delivery infrastructure is becoming increasingly exacting.

    While it makes sense to establish the power distribution architecture early in the project, designers also need flexibility to be able to modify aspects such as POL output power, rail voltages or power-up and power-down sequencing as the system design evolves.

    A common reason this situation occurs is that the load current increases beyond the original specifications and thus the need for electrically larger components to supply the additional load current. One advantage of using power modules is the impact of the design upgrade to the complex and expensive host PCB can be minimized.

    Moreover, digital power supports an efficient “platform” approach, recognizing that system power demands will become more complicated in the future

    Paying attention to power supply design early helps optimize thermal management. In addition, digital modules simplify monitoring of power performance in real-time, which permits on-the-fly adjustment to optimize energy efficiency.

    The PMBus specification provides a common language for configuring, controlling and monitoring digital power modules in a power system. The AMP Group (Architects of Modern Power) consortium has simplified the design-in and interchangeability of digital power modules by standardizing the behavior of digital power modules in response to PMBus commands.

    Conclusion

    As the power requirements of high-performance computing and data equipment become increasingly stringent, engineers must engage with the power supply design at an earlier stage of system development. Today’s systems require increasing numbers of power rails, and impose exacting demands in terms of sequencing, regulation and transient performance. Maximizing energy efficiency is also increasingly important.

    Reply
24. October 14, 2016 at 12:01 pm

    Tomi Engdahl says:

    CMOS Isolated Gate Drivers (ISOdrivers) Enhance Power Delivery Systems
    http://www.silabs.com/products/power/isodrivers/Pages/cmos-isolated-gate-drivers-enhance-power-delivery-systems.aspx?utm_source=newsletter&utm_medium=email&utm_campaign=september2016newsletter&mkt_tok=eyJpIjoiWVRRNE1XTXpOV1poWmpBdyIsInQiOiJEQmVqYlwvZ3NRR09yMXlBVTdMc2oxaDZQcEEwbDI0QjcrZkxwTVBsOXNzR1ozWjRZa3JKUHJNNmZSS1NrTmttZWhYNndtM3lQbEhvSnJXdnBWY2V0QTJ5XC9LdzE1ZDRVb2x3WnR4bTdBOVNvPSJ9

    Fully integrated isolated gate drivers can significantly increase the efficiency, performance, and reliability of switch-mode power supplies compared to legacy solutions.

    Reply
25. October 15, 2016 at 8:35 pm

    Tomi Engdahl says:

    Graphene Refractions
    http://hackaday.com/2016/10/14/graphene-refractions/

    Researchers recently observed negative refraction of electrons in graphene PN junctions. The creation of PN junctions in graphene is quite interesting, itself. Negative refraction isn’t a new idea. It was first proposed in 1968 and occurs when a wave bends–or refracts–the opposite way at an interface compared to what you would usually expect. In optics, for example, this can allow for refocusing divergent waves and has been the basis for some proposed invisibility cloaking devices.

    Negative refraction of electrons spotted in graphene
    http://physicsworld.com/cws/article/news/2016/oct/03/negative-refraction-of-electrons-spotted-in-graphene

    The negative refraction of electrons in graphene has been seen for the first time in experiments done by physicists in the US. The work represents an important advance in the fabrication of graphene electronic devices, and could lead to new applications of graphene such as low-power transistors.

    Negative refraction can occur when light or other waves cross an interface between two different materials. The term “negative” is used when the direction of the light is bent in the opposite direction to that which occurs for conventional materials such as glass and water. Negative refraction is a property of some artificial metamaterials and can be used to bring diverging rays back to a focus – allowing for the creation of a perfect lens.

    Reply
26. October 17, 2016 at 10:57 am

    Tomi Engdahl says:

    Salaries Rise, Gaps Widen for EEs
    IEEE survey shows uneven advances
    http://www.eetimes.com/document.asp?doc_id=1330629

    Last year was a good year for most, but not all electrical engineers. Salaries for EEs rose 3.85% on average in 2015, but gender and racial gaps in salaries widened, according to an annual survey published this week by the IEEE.

    EEs earned a median pre-tax income of $138,285 last year including base salary, commissions, bonuses and net self-employment. Strip away overtime pay, profit sharing, and other supplemental earnings, and the 2015 figure drops to $135,000, up from $130,000 in 2014.

    Reply
27. October 17, 2016 at 11:25 am

    Tomi Engdahl says:

    TSMC Grows Share of Foundry Business
    Repercussions of Samsung’s burning batteries
    http://www.eetimes.com/document.asp?doc_id=1330621&

    Taiwan Semiconductor Manufacturing Co. (TSMC) increased its share of the foundry business to 55 percent this year on better than expected demand for smartphones during the third quarter.

    “In the third quarter, we gained market share across most technology nodes,” according to TSMC Co-CEO Mark Liu, speaking at a Taipei event to announce the company’s quarterly results.

    TSMC, which counts Apple as its largest buyer, said that sales growth was driven by its mobile customer’s new product launch. TSMC makes the A10 processor for Apple’s latest smartphone, the iPhone 7 Plus, introduced in September.

    In the third quarter, TSMC’s sales of chips made with its most advanced 16nm/20nm process technology increased to 31 percent of overall revenue from 23 percent during the second quarter. The quarter marks the first time for 16nm/20nm to account for the largest portion of its overall revenue.

    The company’s previous cash cow, 28nm technology, dropped to 24 percent of its total wafer revenue

    Reply
28. October 17, 2016 at 11:26 am

    Tomi Engdahl says:

    Samsung Making 10nm SoCs
    http://www.eetimes.com/document.asp?doc_id=1330632

    Samsung announced its foundry operations are in “mass production” of 10nm FinFET SoCs. The news comes as Samsung is projected to fall behind this year in the business of making chips for other companies and is reeling from a decision to take its Galaxy Note 7 smartphone off the market.

    The so-called 10LPE process uses triple-patterning lithography to deliver up to a 30% area shrink, 27% higher performance or 40% lower power than its 14nm process, Samsung said in a press statement. First devices to use the 10nm chips should appear early next year with a follow-on 10LPP process ramping late next year, it added.

    The Korean giant took a similar approach at 14nm, delivering a fast-to-market, first-generation FinFET process followed by an optimized version. Process and IP design kits for the 10nm node are available now, Samsung said. The company described a 10nm SRAM cell at a technical conference in January.

    Reply
29. October 17, 2016 at 12:17 pm

    Tomi Engdahl says:

    Frost and Sullivan: PXI dominates modular market, AXIe rising
    http://www.edn.com/electronics-blogs/test-cafe/4442730/Frost-and-Sullivan–PXI-dominates-modular-market–AXIe-rising

    In a study entitled VXI, PXI, and AXIe Test and Measurement Market Disrupts Automated Test, Sparking New Growth Opportunities, Frost and Sullivan reported the market size and growth rates of the various instrument standards, updated to include 2015

    Frost and Sullivan reported the size of the open modular market (VXI, PXI, and AXIe) to be $810M in 2015, now over 20% of the entire automated test market for the first time, excluding dedicated semiconductor test. Modular instruments grew at a combined 7.5% rate last year. A close examination of the figures showed that modular instruments were responsible for all the growth in automated test. That is, traditional instruments slightly declined last year.

    However, the three standards each have different dynamics. VXI, the granddaddy of modular standards, declined 15% over the year before, but still achieved $105M of sales. VXI is in the twilight of its lifecycle, with continued sales driven largely by mil/aero legacy business.

    PXI, including the PXI Express variant, dominates the modular market with $705M of sales in 2015, representing 8.7% growth.

    The fastest growing of the standards was AXIe, which grew at an impressive 61%. Much of the AXIe growth can be credited to having the smaller base, with total 2015 sales of $63M.

    Reply
30. October 19, 2016 at 4:23 am

    Tomi Engdahl says:

    What’s The Deal With Atmel And Microchip?
    http://hackaday.com/2016/10/18/whats-the-deal-with-atmel-and-microchip/

    It’s been nearly a year since Microchip acquired Atmel for $3.56 Billion. As with any merger, acquisition, or buyout, there has been concern and speculation over what will become of the Atmel catalog, the Microchip catalog, and Microchip’s strategy for the coming years.

    Broad Strokes

    In broad strokes, the Microchip PR team wanted to emphasize a few of the plans regarding their cores, software, and how Microchip parts are made obsolete. In simple, bullet point terms, this is what Microchip passed on to me, to pass on to you:

    Microchip will continue their philosophy of customer-driven obsolescence. This has historically been true – Microchip does not EOL parts lightly, and the state of the art from 1995 is still, somewhere, in their catalog.
    We plan to support both Atmel Studio 7 and MPLAB® X for the foreseeable future.
    Microchip has never focused on “one core”, but rather on the whole solution providing “one platform.” This is also true. A year ago, Microchip had the MIPS-based PIC-32 cores, a few older PIC cores, and recently Microchip has released a few ARM cores. Atmel, likewise, has the family tree of 8 and 32-bit AVR cores and the ARM-based SAM cores.
    We will continue to support and invest in growing our 8-bit PIC® and AVR MCU product families.

    How will the 32-bit products complement each other? Atmel has a few 32-bit microcontrollers, like the SAM and AT32 series. Microchip has the PIC-32. The answer to this question is, “Many of the 32-bit MCU products are largely complementary because of their different strengths and focus. For example, the SAM series has specific families targeting lower power consumption and 5 volts where PIC32 has families more optimally suited for audio and graphics solutions. We plan to continue investing in both SAM and PIC32 families of products.”

    Will Atmel’s START support 8-bit AVRs? “Yes, although it is too early to commit to any specific dates at this stage, we consider modern rapid prototyping tools, such as START and the MPLAB Code Configurator, strategic for the our customers to deliver innovative and competitive solutions in this fast-paced industry.”

    Now that Microchip has a complete portfolio of low-power, inexpensive 32-bit microcontrollers, will the focus on 8-bit product be inevitably reduced? “No, we see that in actual embedded control applications there is still a large demand for the type of qualities that are uniquely provided by an 8-bit product such as: ease-of-use, 5V operation, robustness, noise immunity, real-time performance, long endurance, integration of analog and digital peripherals, extremely low-static power consumption and more.”

    What is the future of Microchip post-Atmel acquisition? From what I’m seeing, not much. Microchip is falling back on their philosophy of ‘customer-driven obsolescence’. What does that mean? Any non-biased assessment of Microchip’s EOL policy is extremely generous. The chip found in the Basic Stamp 1, from 1993, is still available. It’s not recommended for new designs, but you can still buy it. That’s impressive any way you look at it.

    Reply
31. October 19, 2016 at 8:08 am

    Tomi Engdahl says:

    Eugene Kim / Business Insider:
    Intel reports record quarterly revenue of $15.8B, up 9% YoY; Client Computing Group had revenue of $8.9B, up 5% YoY; Q4 guidance is weak at $15.7B

    Intel slips after guidance miss
    http://www.businessinsider.com/intel-earnings-q3-2016-2016-10?op=1%3fr=US&IR=T&IR=T

    Intel just reported its third quarter earnings after the bell on Tuesday.

    It’s a beat on earnings and revenue, but a miss on fourth quarter guidance. Investors aren’t too impressed and Intel’s stock is down ~3.5% in after hours.

    Intel reported record-high quarterly revenue, but gave fourth quarter revenue guidance of $15.7 billion, below analyst estimates of $15.86 billion.

    Intel’s Client Computing Group, which includes its PC and mobile business, had revenue of $8.9 billion, up 5% year-over-year, while its data center business saw revenue of $4.5 billion, up 10% from a year-ago period.

    That 10% growth in the data center is a big jump from last quarter’s 5% year-over-year growth, but still a bit disappointing given that the company’s forecast to record “double-digit” growth for the full year

    Reply
32. October 19, 2016 at 10:47 am

    Tomi Engdahl says:

    Kilopass Technology uncorked its new eNVM, which includes vertical layered thyristor DRAM technology. The key advantages, according to the company, is that it eliminates the need for DRAM refresh, can be manufactured using existing processes, and improves power and area efficiency.

    Source:
    The Week In Review: IoT
    http://semiengineering.com/the-week-in-review-iot-22/

    Reply
33. October 19, 2016 at 12:57 pm

    Tomi Engdahl says:

    Flex primer for IoT & wearables
    http://www.edn.com/design/pc-board/4442806/Flex-primer-for-IoT—wearables?_mc=NL_EDN_EDT_EDN_today_20161017&cid=NL_EDN_EDT_EDN_today_20161017&elqTrackId=f6eb4f0654cb47298b5153984d7ebcf5&elq=39f464e080214302a5090f14b5da0cd3&elqaid=34387&elqat=1&elqCampaignId=30000

    Today, technology trends are increasingly toward flex circuits or a combination of rigid-flex circuits for wearable/IoT PCB designs.

    Therefore, it’s important to get a handle on new design terminology and things that need to be factored in as you move to this next level of embedded design.

    This includes the following:

    Low and high modulus boards
    Bend radius, ratio, and strains
    Dielectric thickness
    Via placement
    Board layers and associated copper amounts
    Regular copper versus annealed copper
    Copper thickness

    Board modulus refers to its structure — a low modulus means a softer structure, while high modulus refers to a harder board with stiffener.

    Stiffeners are an inexpensive way to rigidize certain areas on the flex boards, such as SMT areas, pin areas, or hole pattern locations for component mounting.
    SMT areas don’t always need stiffeners depending on the components being installed at that location. However, adding a stiffener is going to add very little cost to the assembly.

    Regardless of the application, a flex circuit must be pliable and bendable, but the question is: How pliable and bendable can it be?

    The best advice given is to rely on an experienced EMS Provider that has several wearable/IoT PCB designs under its belt and has a storehouse of critical nuances associated with flex circuit bendability.

    Flex Circuit Design Primer for Wearable/IoT Device
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1330571

    Reply
34. October 19, 2016 at 1:10 pm

    Tomi Engdahl says:

    10nm FinFET Market Heats Up
    http://semiengineering.com/10nm-finfet-market-heats-up/

    The 10nm finFET market is heating up in the foundry business amid the ongoing push to develop chips at advanced nodes.

    Not long ago, Intel announced its 10nm finFET process, with plans to ramp up the technology in 2017. Then, TSMC recently introduced its 10nm process, with plans to move into production by the fourth quarter of 2016.

    Now, Samsung Electronics said that it has commenced mass production of system-on-a-chip (SoC) products with its 10nm finFET technology. Another foundry vendor, GlobalFoundries, is skipping 10nm and moving directly to 7nm.

    Samsung, meanwhile, said it is the world’s first company to ship 10nm finFETs, beating its rivals to the punch. “For 10nm, we are announcing that we have started production,” said Hong Hao, senior vice president of the foundry business at Samsung Semiconductor. “We are the first one to production at the 10nm node.”

    Reply
35. October 19, 2016 at 2:30 pm

    Tomi Engdahl says:

    Full Color e-Posters Could Reach 10,000 DPI
    http://www.eetimes.com/document.asp?doc_id=1330638&

    Researchers from the Chalmers University of Technology (CUT) have demonstrated that plasmonic nanostructures combined with electrically-tuneable polymers could yield just any color on demand.

    Designing a flexible sheet of e-paper pixels as a proof-of-concept, the researchers claim the technology could cut today’s electrophoretic e-papers power consumption more than ten folds while allowing very high resolutions on large scale formats, for posters or foldable e-readers less than a micrometre thin.

    https://www.researchgate.net/publication/308694388_Plasmonic_Metasurfaces_with_Conjugated_Polymers_for_Flexible_Electronic_Paper_in_Color

    Reply
36. October 20, 2016 at 9:06 am

    Tomi Engdahl says:

    Oxygen Layer May Extend Moore’s Law
    In CMOS, boosting performance sans-scaling
    http://www.eetimes.com/document.asp?doc_id=1330636&

    Moore’s Law could be extended again sans scaling, according to Robert Mears. Mears invented the Erbium Doped Fiber Amplifier (EDFA) — the first commercial and still popular method of amplifying optical signals without having to convert them into electrical signals (and back again). Now Mears believes he has invented an equally industry-changing technology for CMOS called the Mears Silicon Technology (MST) at Atomera Inc. (Los Gatos, Calif., originally Nanovis LLC).

    Reply
37. October 20, 2016 at 9:13 am

    Tomi Engdahl says:

    FPGA-Controlled Test: What it is and why is it needed?
    http://www.techonline.com/electrical-engineers/education-training/tech-papers/4229805/FPGA-Controlled-Test-What-it-is-and-why-is-it-needed=NL_TOL_Edit_Subs_20161019_TechnicalPaper

    The role that FPGAs have played in computer and communications systems has grown in parallel with the number of gates and the capabilities of these devices. Now FPGAs are emerging as a likely platform for next-generation embedded board test and measurement capabilities which can be employed during design, development, manufacturing, and in the field following product launch. Without requiring a dedicated FPGA, a board-tester-in-a-chip can be easily inserted and removed as it is needed or it can remain in-system. This trend toward FPGA-controlled test (FCT) is a part of the larger shift toward embedded instrumentation as a more effective methodology for validating, testing and debugging circuit boards.

    Reply
38. October 21, 2016 at 8:19 am

    Tomi Engdahl says:

    Will There Be Enough Silicon Wafers?
    Market pressures shrink number of providers of basic building blocks for chips.
    http://semiengineering.com/silicon-wafer-consolidation-fallout/

    The silicon wafer industry, a critical part of the IC supply chain, is undergoing a new and perhaps alarming wave of merger and acquisition activity.

    While consolidation in this sector is not new, the pace of M&A activity is picking up and there are fewer companies left. Silicon wafer makers produce and sell raw silicon wafers to chipmakers, which process them into chips. But despite continued growth in semiconductor shipments, this remains a highly competitive market segment with severe pricing pressure.

    Silicon wafer customers should keep a close eye on this transaction, as well as this market in general, because the silicon wafer industry is ripe for more consolidation.

    To be sure, though, consolidation is needed in the industry. “We view industry consolidation to be positive, as it should enable stable pricing with rational supply addition,”

    Wafer madness
    Meanwhile, silicon wafers are a fundamental part of the semiconductor business—every chipmaker needs to buy them in one size or another. In the silicon wafer production flow, the process starts with polysilicon. Polysilicon is melted in a quartz crucible along with electrically active elements.

    A silicon seed crystal is lowered into the crucible. The resulting body is called an ingot, which is pulled and sliced into wafers. The sizes include 300mm, 200mm and smaller.

    The process is challenging

    Consolidation swept the industry for several reasons. For one thing, it requires a significant amount of capital to compete in the business. The smaller players are unable to keep up and many of them end up being acquired.

    But the biggest problem is that the silicon wafer industry has suffered from a period of excess capacity, price pressures and low margins.

    Today, 300mm wafers account for 60% of area sold, while 200mm represents 31%, according to Sage. The remaining output is 150mm and smaller sizes.

    In total, 300mm silicon wafer capacity grew from 43 million wafers per year in 2009 to 76 million wafers in 2015

    “In 2015, the semiconductor industry had the capacity to consume 76 million wafers per year, but only consumed 57 million wafers,”

    So there is no need to add any new capacity. On the contrary, the trend among vendors has been to shutter under-utilized or older plants to cut costs.

    “Wafer prices on a per-square inch basis were at an all-time low last year even as volumes reached an all-time high,”

    The biggest challenge, according to Thong, has been the inability to raise prices despite sustained demand growth. “Wafer vendors need to convince buyers to accept price increases,” he said. “This is a struggle. In a time of strong profitability for chipmakers, only an outright shortage may succeed to allow wafer producers to claw back their fair share of value.”

    In total, the silicon wafer market is projected to reach around $7 billion in 2016, down 1% from 2015

    Still, there are some positive signs in the industry. “Supply-demand is very much in balance, and more in balance than it has been in a long time,”

    Reply
39. October 21, 2016 at 8:25 am

    Tomi Engdahl says:

    What Happened To Inverse Lithography?
    Technology resurges as industry pushes to 7nm and 5nm.
    http://semiengineering.com/what-happened-to-inverse-lithography/

    Nearly 10 years ago, the industry rolled out a potentially disruptive technique called inverse lithography technology (ILT). But ILT was ahead of its time, causing the industry to push out the technology and relegate it to niche-oriented applications.

    Today, though, ILT is getting new attention as the semiconductor industry pushes toward 7nm, and perhaps beyond. ILT is not a next-generation lithography (NGL) tool technology. Instead it falls into the field of computational lithography and is used for the production of advanced photomasks.

    ILT is a next-generation reticle enhancement technique (RET) that enables an optimal photomask pattern for both optical and extreme ultraviolet (EUV) lithography reticles. Using a complex mathematical formula, ILT improves the latitude of a process and the depth of focus for a lithography tool.

    Ultimately, the industry hopes to devise “full-chip ILT masks,” which involves the integration of the technology for all layers, not just for some isolated features on the reticle.

    Today, ILT is used in niche applications, mainly for hot spot repair on the mask. But now, the industry is finally moving closer toward full-chip ILT masks for advanced IC designs at 7nm and/or 5nm.

    To be sure, full-chip ILT is a key enabler. “ILT is another RET,” said Vivek Singh, a fellow and director of computational lithography at Intel. “So, it’s a technique to sharpen the image somewhat for specific conditions of layout pitches. It obviously works better when you are pushing the density. It also works better when you are trying to make small features like vias.”

    But there are still some challenges to implement full-chip ILT. “(The challenge is) to translate those masks into manufacturable ones,”

    Is ILT ready?
    ILT is heating up again, though, and for good reason.

    There are other factors. At 28nm and above, for example, the features and shapes on optical masks are more simple and rectangular. Starting at 20nm, the shapes began to move toward more complex and curvilinear features.

    As a result of mask complexity, the write times for a photomask have increased by about 25% a year since 2011. This, in turn, impacts mask turnaround times and cost.

    EUV and ILT?
    At 7nm, meanwhile, the industry is moving in two directions. Some chipmakers will extend 193nm immersion and multiple patterning to 7nm, while others hope to insert EUV. Based on 13.5nm wavelength technology, EUV promises to simplify the patterning flow, thereby reducing the mask count.

    But EUV is still not in production. There are persistent issues with the power source, resists and mask infrastructure.

    With optical lithography and multi-patterning, the mask count is expected to reach about 80 to 85 layers at 7nm, compared to 60 at 16nm/14nm. “We think maybe one or two companies can afford this technology (at 7nm),”

    But if EUV does happen at 7nm, the technology will still require a multiple patterning scheme. “We think EUV and multi-patterning are complementary,”

    “ILT technology actually supplements EUV since the initial hardware is being shipped with a low numerical aperture (NA),”

    Reply
40. October 24, 2016 at 8:35 am

    Tomi Engdahl says:

    Qualcomm Said to Be Near Final NXP Deal, May Announce Next Week
    http://www.bloomberg.com/news/articles/2016-10-20/qualcomm-said-to-be-near-final-nxp-deal-may-announce-next-week

    Qualcomm Inc. is reaching the final stages of negotiations to acquire NXP Semiconductors NV and the two chipmakers may announce a deal as early as next week, according to people familiar with the process.

    The purchase would be the largest transaction in the history of the semiconductor industry. It’s part of a wave of deals that has seen chipmakers merge at a record rate to keep up with increasing costs and a shrinking list of customers that are demanding more from their component suppliers. Qualcomm is trying to reduce its dependence on the slowing smartphone market and find ways to sell its modems and processors for other applications, such as cars, one of NXP’s strengths.

    Reply
41. October 24, 2016 at 8:40 am

    Tomi Engdahl says:

    The Week In Review: Manufacturing
    http://semiengineering.com/the-week-in-review-manufacturing-134/

    At upcoming the 2016 IEEE International Electron Devices Meeting (IEDM) in San Francisco, TSMC will square off against the alliance of IBM, GlobalFoundries and Samsung at 7nm. IEDM will take place Dec. 3-7, 2016.

    TSMC will present a paper on 7nm finFET technology. Using 193nm immersion and multi-patterning, the 7nm technology features more than three times the gate density and either a speed gain (35-40%) or power reduction (>65%) versus the company’s 16nm finFET process. TSMC built a low-voltage 256-Mb SRAM test chip with full read/write functionality down to 0.5V, and the smallest SRAM cells ever reported (0.027µm2).

    Not to be outdone, the trio of IBM, GlobalFoundries and Samsung technology will also present a paper on 7nm. It will use extreme ultraviolet (EUV) lithography. With EUV, the 7nm technology will feature a contacted polysilicon pitch of 44nm/48nm and metallization pitch at 36nm.

    Samsung plans to use EUV for production at 7nm. Initially, GlobalFoundries won’t use EUV at 7nm. It plans to extend optical, according to the company.

    Samsung has commenced mass production of system-on-chip (SoC) products, based on 10nm finFET technology. Others have also announced 10nm. In addition, Samsung has rolled out the industry’s first 8-gigabyte LPDDR4 mobile DRAM. The 8-GB mobile DRAM package utilizes four of 16-gigabit LPDDR4 memory chips and 10nm-class process technology.

    Reply
42. October 24, 2016 at 10:54 am

    Tomi Engdahl says:

    400 mA Step-down DC/DC Converter with Built-in Inductor
    https://www.eeweb.com/company-news/ixys/400-ma-step-down-dcdc-converter-with-built-in-inductor/

    The IXD9208/09 is a 400 mA step-down DC/DC converters featuring built-in inductor and transistors operating at input voltage range of 2.0 V to 6.0 V. It has an oscillation frequency of 3 MHz operating at PWM or PWM/PFM auto select modes typically used in various portable and office automation equipment.

    The IXD9208/09 series are synchronous step-down DC/DC converters with an inductor and a control IC in one tiny (2.5 × 2.15 × 1.0 mm) package. A stable power supply with an output current of 600 mA requires only two capacitors connected externally.

    Output voltage is internally set in a range from 0.8 V to 4.0 V in 0.05 V increments.

    Reply
43. October 24, 2016 at 11:54 am

    Tomi Engdahl says:

    Supercapacitor Uses No Carbon
    http://hackaday.com/2016/10/22/supercapacitor-uses-no-carbon/

    Researchers announced a new type of supercapacitor that uses no carbon and could have advantages over conventional technologies. The new research focuses on metal-organic frameworks, or MOFs. This material is extremely porous with a sponge-like structure. Since supercapacitors require large surface areas, that makes MOFs an interesting material for that application. However, MOFs are not very electrically conductive, which is a disadvantage.

    New kind of supercapacitor made without carbon
    Energy storage device could deliver more power than current versions of this technolog
    https://news.mit.edu/2016/supercapacitor-made-without-carbon-1010

    Reply
44. October 25, 2016 at 10:24 am

    Tomi Engdahl says:

    IP Market: CPU Still The Largest But Security Leads In Growth
    What does the future hold for different types of IP?
    http://semiengineering.com/ip-market-cpu-still-the-largest-but-security-leads-in-growth/

    The 3rd Party Semiconductor Intellectual Property (SIP) market has seen great innovation in the products it offers to System-on-a-Chip (SoC) designers over the last ten years. If any market segment in the semiconductor industry typifies the intense evolutionary pressures that the entire electronics market has undergone, it is the 3rd Party SIP market.

    As the semiconductor industry enters the latter half of the second decade of the 21stcentury, substantial changes to the System-on-a-Chip (SoC) design methodology are taking shape. These changes will create a new standard for how these very complex silicon solutions are conceptualized, designed and implemented for at least the rest of this decade and possibly longer.

    Overall, the market growth rate for revenues from 2015 – 2020 is somewhat lower than in previous forecasts. This is due more to the law of large numbers than to a slowing of demand. Market consolidation will undoubtedly have some impact on revenues and growth rates in the future.

    Reply
45. October 25, 2016 at 10:25 am

    Tomi Engdahl says:

    GaN Power Semi Biz Heats Up
    http://semiengineering.com/gan-power-semi-biz-heats-up/

    Technology makes inroads in power supply market, with electric vehicles and fast-charging adapters on the horizon.

    The market for devices based on gallium nitride (GaN) technology is heating up amid the push for faster and more power efficient systems.

    Today, GaN is widely used in the production of LEDs. In addition, it is gaining steam in the radio-frequency (RF) market. And the GaN-based power semiconductor market finally appears ready to take off, after several false starts and disappointing results in the arena.

    In 2010, vendors announced the first wave of GaN-based power semiconductors. But until recently, product availability was scarce, prices were high, and the technology was in search of an application.

    Now, though, GaN-based power semis are making inroads in the power supply market. And over time, the devices are expected to move into electric vehicles, fast-charging adapters for mobile devices, wireless charging and other systems.

    Reply
46. October 25, 2016 at 10:27 am

    Tomi Engdahl says:

    Watch Out For 200mm Fabs: Fab Outlook To 2020
    http://semiengineering.com/watch-out-for-200mm-fabs-fab-outlook-to-2020/

    Don’t dismiss 200mm as outdated or “old technology.” This mighty wafer size is making a remarkable comeback.

    One year after the debut of the industry’s first 200mm Fab Outlook report, SEMI has just issued an October 2016 update with the improved and expanded report forecasting 200mm fab trends out to 2020.

    This extensive report features trends from 2009 to 2020, showing how 200mm fab activities and capacity change worldwide.

    Examining 200mm capacity over the years, the highest level of 200mm capacity was recorded in 2007 and the lowest following this peak in 2009 (See figure 1). The capacity decline from 2007 to 2009 is driven by the 2008/2009 global financial crisis, which caused the closure of many facilities, and to the transition of memory and MPU fabrication to 300mm fabs from 200mm.

    Since 2009, installed 200mm fab capacity has increased, and by 2020, 200mm capacity is expected to reach 5.5 million wafers per month (wpm), though still less than the 2007 peak. According to SEMI’s data, by 2019, installed capacity will reach close to 5.38 million wpm, almost as high as capacity in 2006.

    From 2015 to 2020, 200mm facilities are forecast to add 618,000 wpm net capacity.

    Two applications account for the growing demand for 200mm: mobile devices and IoT. The main product types with rising fab capacity from 2015 to 2020 will be MEMS devices, Power, Foundry and Analog. By region, greatest increases in capacity will be seen in China, SE Asia, Americas, and Taiwan.

    Another trend is also observed: 200mm fabs are increasing the capacity to provide process capability below 120nm.

    Between 2015 to 2020, SEMI reports that 27 new 200mm fabs/lines will start operations; in the same time frame, only 9 facilities are currently projected to close.

    Reply
47. October 25, 2016 at 10:34 am

    Tomi Engdahl says:

    Qualcomm is known as the number one smartphone circuits sovereign name, but this image should be checked probably already this week. According to data from the American announced soon left the store with Qualcomm to buy the former Philips semiconductor side, now NXP Semiconductors.

    The purchase price is estimated at more than 30, up to 40 billion dollars. As a result, mobile phones, the number one name will also be the largest manufacturer of automotive electronics components. In addition, Qualcomm will increase the world’s third largest semiconductor company right after Intel and Samsung.

    Source: http://etn.fi/index.php?option=com_content&view=article&id=5279:qualcommista-tulossa-kolmanneksi-suurin&catid=13&Itemid=101

    Reply
48. October 25, 2016 at 10:36 am

    Tomi Engdahl says:

    Quickly tailor-made lithium-ion battery for your device

    Lithium-ion battery is the most popular battery chemistry technology for portable devices. However, the battery design of your device may be difficult.

    Vartan Cellpac BLOX platform is actually a service, where the equipment manufacturer can quickly and cheaply to design your application and its precise requirements of a suitable LiIon battery. The manufacturer may choose from a wide range of different cells, security modules and connectors.

    These specs allow Varta service can quickly design and manufacture of the battery in mAh 150-7800 for demanding applications. Finished battery is delivered by 12 to 16 per week.

    The service is available through Varta distributors across Europe.

    Source: http://etn.fi/index.php?option=com_content&view=article&id=5276:nopeasti-raataloity-litiumioniakku-omaan-laitteeseen&catid=13&Itemid=101

    Reply
49. October 25, 2016 at 12:40 pm

    Tomi Engdahl says:

    2016 has been a garbage fire. But 2017′s looking up – there’ll be loads of IPOs, beams Intel
    Head of chip giant’s VC arm bullish about exits
    http://www.theregister.co.uk/2016/10/24/lots_of_tech_ipos_in_2017_says_intel/

    Pretty much everyone can agree that 2016 has been awful all round, but hey here’s something we can look forward come January 1: 2017 is going to be the year of new tech IPOs, according to the CEO of Intel’s venture capital arm.

    Giving the keynote at the Intel Capital Global Summit in San Diego, Wendell Brooks was bullish about what the new year will bring, arguing that the “backlog is building” of tech companies that want to access public markets.

    He put the sluggish 2016 market – where fewer tech IPOs than any time in the past decade took place – down to two factors: a shake-out of the privately valued “unicorns” and fears brought about by the US election cycle.

    Where we’re going

    As for the next few years of tech and tech investment, Brooks highlighted four main areas: drones; automated driving; “new experiences” – largely VR; and “verticals.”

    During the presentation, a number of demonstrations highlighted new virtual reality technologies – and in particular live-streamed VR, often tied into sports. There was a lot of technical work to be done to build up the VR ecosystem, Brooks noted, and it was still in its infancy but the possibilities were enormous.

    Both high-end and low-end systems were demoed. The high-end Voke camera system captures everything at extremely high quality and could see use at big sports events, whereas the lower-end Altia Systems camera setup offers panoramic 4K video with real-time stitching of images for as little as $2,000.

    Brooks also spoke enthusiastically about the “drone economy,”

    Reply
50. October 25, 2016 at 12:54 pm

    Tomi Engdahl says:

    TSMC, GF/Samsung Battle at 7nm
    Intel may take back seat to foundries
    http://www.eetimes.com/document.asp?doc_id=1330657

    TSMC will go head-to-head with the partnership of IBM, Globalfoundries and Samsung to publicly detail rival 7nm processes at a technical conference in December. The trio’s process will use extreme ultraviolet lithography to achieve impressive gains, but TSMC likely will get to market first due to challenges getting EUV into production.

    Using EUV, GF and Samsung claim they will deliver “the tightest contacted polysilicon pitch (44/48nm) and metallization pitch (36nm) ever reported for FinFETs,” in an abstract for the International Electron Devices Meeting (IEDM).

    The pitches leapfrog the 56nm gate pitch Intel announced in August for its 10nm process, claiming industry-leading density for the node it aims to have in production next year. Observers have started to suggest both TSMC and Samsung might leapfrog Intel which has slowed the pace of releasing new process technologies as progress in Moore’s law becomes more complex and costly.

    Reply