Electronics trends for 2016

961 Comments

1. December 1, 2016 at 8:46 am

   Tomi Engdahl says:

   Multi-Patterning Issues At 7nm, 5nm
   http://semiengineering.com/multi-patterning-problems-grow/

   Variations in different masks, alignment problems and the physical limits of immersion add up to serious issues at 7nm and 5nm.

   Continuing to rely on 193nm immersion lithography with multiple patterning is becoming much more difficult at 7nm and 5nm.

   With the help of various resolution enhancement techniques, optical lithography using a deep ultraviolet excimer laser has been the workhorse patterning technology in the fab since the early 1980s. It is so closely tied with the continuation of Moore’s Law that it is difficult to think of one without the other. But how much longer this technology can continue isn’t clear, given the magnitude and breadth of the problems expected at upcoming nodes.

   The semiconductor industry has been banking on extreme ultraviolet (EUV) lithography for the past decade to circumvent the problems that 193i is beginning to encounter. For example, immersion lithography requires double patterning at 16nm/14nm and quadruple patterning at 7nm. Both schemes work, but they present some new and major challenges. Extra patterning increases the cycle time and cost in both the photomask shop and in the fab. And that’s just the tip of the iceberg.

   But if chipmakers extend immersion/multi-patterning to 5nm, they may need to resort to the unthinkable—octuple patterning, described almost universally as a nightmarish scheme that is considered unwieldy and too costly.

   At 7nm and/or 5nm, the alternative is EUV, which supposedly simplifies the patterning flow. With a 13.5nm wavelength, EUV would be able to pattern even the finest detail with a single pass at a 22nm half-pitch. If EUV is ready, chipmakers likely would use EUV to pattern some of the critical features, such as contacts and vias, at 7nm with a single exposure. But at 5nm, they would require EUV, plus a multiple patterning scheme.

   Still to be seen, however, is when or whether EUV will become commercially viable.

   Reply
2. December 1, 2016 at 8:46 am

   Tomi Engdahl says:

   7nm Design Success Starts With Multi-Domain Multi-Physics Analysis
   http://semiengineering.com/7nm-design-success-starts-with-multi-domain-multi-physics-analysis/

   Where the pitfalls are in advanced-node designs and multi-chip packages, and best practices for managing them.

   Companies can benefit from advancements in the latest semiconductor process technology by delivering smaller, faster and lower power products, especially for those servicing mobile, high performance computing and automotive ADAS applications. By using 7nm processes, design teams are able to add a lot more functionality onto a single chip and lower the power consumption by scaling operating voltage down to 500mV without sacrificing performance. However, the risk of design failure and its associated cost at this advanced node is significantly higher than ever before.

   Reply
3. December 1, 2016 at 9:47 am

   Tomi Engdahl says:

   Simulation Takes on Bigger Roles in Product Development
   Simulation tools are becoming part of the design engieneer’s workbench
   http://www.designnews.com/design-hardware-software/simulation-takes-on-bigger-roles-product-development/150004278546156?cid=nl.x.dn14.edt.aud.dn.20161129.tst004c

   The real world isn’t what it used to be when it comes to testing. Simulation has created a world of new product testing that puts products through scenarios that cannot be duplicated by prototypes in the real world. Instead of just testing an actual part physically, simulation can test an entire complex product – like a car – and see how each part performs in conjunction with the entire product – a form of accurate testing that can’t be done in the real world.

   The exception is with composites and some 3D-printed parts. There is not enough data on the new materials and 3D-printed shapes to provide accurate simulation. That’s temporary, however.

   Reply
4. December 1, 2016 at 10:09 am

   Tomi Engdahl says:

   Signal integrity and power integrity in high-speed design
   http://www.edn.com/design/designcon/4433827/Signal-integrity-and-power-integrity-in-high-speed-design?_mc=NL_EDN_EDT_pcbdesigncenter_20161128&cid=NL_EDN_EDT_pcbdesigncenter_20161128&elqTrackId=674ce327c070415dba447d459e4340df&elq=9a4e193c23ba431fb5a7beedf5f17d67&elqaid=34941&elqat=1&elqCampaignId=30505

   Editor’s Note: Signal integrity (SI) and power integrity (PI) are two critical topics in high-speed design and a major focus at DesignCon

   Signal integrity (SI) and power integrity (PI) are two distinct but related realms of analysis concerned with proper operation of digital circuits. In signal integrity, the main concern is making sure that transmitted 1s look like 1s at the receiver (and same for the 0s). In power integrity, the main concern is making sure that the drivers and receivers are provided with adequate current to send and receive 1s and 0s. So, power integrity could be considered a subset of signal integrity. Really, they are both analyses concerned with the proper analog operation of digital circuits.

   The Necessities for Analysis

   If computing resources were infinite, these different types of analysis might not exist. Entire circuits would be analyzed at once, and problems in one part of the circuit would be identified and eliminated. But other than being bound by the reality of what can practically be simulated, the advantage of having different realms of analysis is that specific problems can be addressed in groups without falling under the category of “anything that could possibly go wrong.”

   Reply
5. December 1, 2016 at 10:32 am

   Tomi Engdahl says:

   Silicon Wafer Transfer Machine Is Beautifully Expensive
   http://hackaday.com/2016/11/30/silicon-wafer-transfer-machine-is-beautifully-expensive/

   There’s nothing more freeing than to be an engineer with no perceptible budget in sight. [BrendaEM] walks us through a teardown of a machine that was designed under just such a lack of constraint. It sat inside of a big box whose job was to take silicon wafers in on one side and spit out integrated circuits on the other.

   Reply
6. December 2, 2016 at 12:06 pm

   Tomi Engdahl says:

   Utilizing GaN transistors in 48V communications DC-DC converter design
   http://www.edn.com/design/power-management/4443072/Utilizing-GaN-transistors-in-48V-communications-DC-DC-converter-design?_mc=NL_EDN_EDT_EDN_today_20161201&cid=NL_EDN_EDT_EDN_today_20161201&elqTrackId=e8be62395f8d460ba14dd599c1317a43&elq=9d044c620c3241b1b89ab9d34092c5ab&elqaid=34988&elqat=1&elqCampaignId=30543

   As the world’s demand for data increases seemingly out of control, a real problem occurs in the data communications systems that have to handle this traffic. Datacenters and base stations, filled with communications processing and storage handling, have already stretched their power infrastructure, cooling, and energy storage to their limits. However, as the data traffic continues to grow, higher density communications and data processing boards are installed, drawing even more power. In 2012, communications power consumptions of networks and datacenters added up to 35% of the overall electricity use in the ICT sector (Figure 1). By 2017, networks and datacenters will use 50% of the electricity, and it will continue to grow.

   One solution to this problem is to re-architect datacenter systems from distributing 12V power along the backplane to distributing 48V on the backplane. Just recently, in March 2016, in the USA, Google announced that it will join the Open Compute Project, and contribute its knowledge and experience (since 2012) of utilizing a 48V distributed power system. Though this helps to solve one problem, it creates another: How do the power designers of the communications and data processing cards increase the efficiency, decrease the size and increase the power levels of their DC-DC converters, provided from 48V?

   In today’s architectures, using 12V backplanes, the industry is able to use 40V MOSFETs

   Using a 48V backplane forces DC-DC designers to use 100V MOSFETs, which have significantly higher FOM values and therefore are inherently less efficient. 100V enhancement mode GaN devices, however, are able to meet the challenges of DC-DC designers by delivering a very high efficiency, high frequency solution

   One of the most critical design considerations to make for a 48V DC-DC converter using GaN transistors is to minimize the dead time between one transistor turning off, and the other turning on. This is because in a GaN E-HEMT transistor there is no intrinsic, parasitic diode, nor is there a need for one.

   The final analysis

   48V datacenters and communications systems will require DC-DC converter designers to learn how to maximize efficiency using 100V transistors. GaN E-HEMT transistors, when compared to Silicon MOSFETs at 100V and even at 40V, offer a significant improvement in FOM and gate drive performance, allowing designers to achieve high frequency, high power density designs at very high efficiency levels.

   Reply
7. December 2, 2016 at 12:45 pm

   Tomi Engdahl says:

   The new solar cell material power is approaching silicon

   Flexible, affordable and easy to prepare. No wonder that the perovskite is now being tested as rigorously material for the next generation of solar cells. Australia has recorded new record levels, with a basis of silicon, the gap is shrinking rapidly.

   Perovskite is still quite young material. For the first time it applied for the production of solar electricity in 2009, when efficiency was 3.8 per cent. However, progress has been rapid and Ho-Baillie believes that the benefit in relation to over 24 per cent over the next year.

   Is a perovskite compound, wherein the light-intercepting layer is composed of lead or a hybrid tin halid based active film.

   Source: http://etn.fi/index.php?option=com_content&view=article&id=5517:uuden-kennomateriaalin-teho-lahestyy-piita&catid=13&Itemid=101

   Reply
8. December 7, 2016 at 11:26 am

   Tomi Engdahl says:

   Scientists Develop the First Self-Destructing Battery
   https://www.eeweb.com/blog/eeweb/scientists-develop-the-first-self-destructing-battery

   Of the 21 batteries used per year by the average household, only 5% of rechargeable batteries and 2% of disposable batteries are recycled, resulting in an increasing amount of toxic waste without a sustainable mode of elimination. This issue will only be compounded by the global battery demand forecasted to rise 7.7% per year until 2019. Now, researchers from Iowa State University have built the world’s first stable transient battery that dissolves in water.

   “Unlike conventional electronics that are designed to last for extensive periods of time, a key and unique attribute of transient electronics is to operate over a typically short and well-de ned period, and undergo fast and, ideally, complete self-deconstruction and vanish. when transiency is triggered.” – —Reza Montazami in Journal of Polymer Science

   Reply
9. December 7, 2016 at 11:28 am

   Tomi Engdahl says:

   No, The Sky Is Not Falling
   http://www.eetimes.com/author.asp?section_id=36&doc_id=1330922&

   If Apple is slashing semiconductor orders, TSMC would bear the most impact. Is this what’s happening?

   TAIPEI — It’s comforting to know that the sky is not falling yet.

   Early this morning, I became alarmed when I saw a headline scrolling across my TV screen saying ‘Chipmakers Tumble Most Since June on Report Apple Cut Orders’. As a diligent reporter, I of course was skeptical and checked immediately with my sources.

   If Apple is slashing semiconductor orders, Taiwan Semiconductor Manufacturing Co. (TSMC) would bear the most impact. The world’s biggest foundry has Apple as its largest customer and is probably the sole supplier of Apple’s latest A10 processor.

   “Apple will no longer be a driver,” Lu said in a phone conversation with me. “There hasn’t been anything new coming from Apple since Steve Jobs passed away.”

   Reply
10. December 7, 2016 at 11:30 am

    Tomi Engdahl says:

    Can FPGA Fabric and an SoC Co-Exist on the Same Chip?
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1330936&

    Now that three vendors are chasing the embedded FPGA market, potential customers will have a wider choice, which has to be a good thing.

    At first glance, combining FPGA fabric with an SoC looks like a marriage made in heaven. The end-product will have the benefit of highly optimized functions built into the SoC portion coupled with the ability to be customized using the FPGA. In addition, the combined solution should have a higher performance at reduced power and lower cost than using two discrete devices. What could possibly go wrong?

    Let’s back up a little and look at Achronix and QuickLogic. Both offer stand-alone devices in the merchant market, where they’re up against the duopoly of Xilinx and Intel. These two giants account for close on 90% of the $4B annual FPGA market, leaving less than $500M for the other players. But the third largest FPGA vendor, Microsemi, takes around $300M, and Lattice fills the fourth spot with FPGA revenue of around $130M. These numbers might make uncomfortable reading for QuickLogic and Achronix, but they put into context the mountain they must climb. So, both companies have chosen to try to build a revenue stream using embedded fabric. This is the area where Flex Logix is operating, except it does not offer discrete devices and its business model is totally reliant on revenue from licenses followed by unit royalties once its customers start shipping product.

    What are the barriers to embedding FPGA fabric in an SoC? The first obstacle is that the fabric needs to be supported on the chosen SoC technology. For example, TSMC commands around 60% of the foundry market, but uses multiple process geometries and variants to service such a large customer base. Flex Logic supports some of the popular 28nm, 40nm, and 16FF TSMC processes. Achronix currently use a 22nm FinFET process from Intel, but offers a service to port to your chosen technology. (More on QuickLogic later).

    Reply
11. December 7, 2016 at 11:37 am

    Tomi Engdahl says:

    Lawmakers Urge Rejection of Lattice Semi Takeover
    http://www.eetimes.com/document.asp?doc_id=1330943&

    A group of U.S. lawmakers has written a letter to Treasury Dept. Secretary Jack Lew urging him to reject the proposed acquisition of programmable logic supplier Lattice Corp. by an investment firmed with ties to China’s central government, saying it represents a threat to U.S. semiconductor leadership.

    China has been growing increasingly aggressive in attempting to bolster its domestic semiconductor industry through the acquisition of Western firms. The U.S. government has been become increasingly wary of these deals. China’ announced last year it plans to invest $161 billion over the next 10 years to develop a domestic semiconductor industry.

    Reply
12. December 7, 2016 at 12:37 pm

    Tomi Engdahl says:

    TSMC, IBM Detail 7-nm Work
    Separate talks upbeat on EUV lithography
    http://www.eetimes.com/document.asp?doc_id=1330940

    Like presents under a Christmas tree, separate papers on 7-nm process technology from TSMC and IBM energized a packed ballroom on the first day of the International Electron Devices Meeting (IEDM). They showed results nudging forward both Moore’s law and extreme ultraviolet lithography (EUV).

    TSMC reported the smallest 6T SRAM to date in a process that it aims to put into risk production by April. IBM described the smallest FinFET made to date in a research device made with EUV.

    IBM showed FinFETs with contacted poly pitch of 44/48 nm, a metallization pitch of 36 nm, and a fin pitch of 27 nm. One device included a source-to-drain contact opening of about 10 nm and a gate length of about 15 nm.

    TSMC described a 256-Mbit SRAM test chip with the cell density of 0.027 mm2 with full read/write capabilities down to 0.5 V. The node should provide up to a 40% speed gain, a 65% power reduction, and a 3.3x routed gate density increase compared to TSMC’s 16FF+ process now in volume production

    Although it was not part of his formal paper, Wu also commented on work using the 7-nm process to validate EUV. The next generation lithography provided “comparable patterning fidelity” and “comparable yield” to the conventional immersion steppers it will use in the commercial 7-nm process next year.

    The EUV systems from ASML are still in a pre-production release. TSMC already announced its plans to start using EUV in its 5-nm node.

    Wu declined to give details of how the 7-nm process compares to its 10-nm node or nodes from rivals such as Samsung.

    Wu did say TSMC had reached 50% yields on its 7nm SRAM. That suggests it is on a path to have volume manufacturing in the process by late 2017, Kanter said.

    Reply
13. December 7, 2016 at 12:43 pm

    Tomi Engdahl says:

    RISC-V Expands its Audience
    Workshop attracts chip architects, execs
    http://www.eetimes.com/document.asp?doc_id=1330915

    The RISC-V movement is grabbing the attention of a growing set of chip architects and semiconductor executives. Several came to the group’s fifth workshop here to gauge whether the seeds planted by a handful of academics could grow into a disruptive, commercial reality.

    The group aims to spread support for its free instruction set architecture across a broad range of products. Talks at the event made clear it will take several years for the ambitious efforts to bear fruit.

    Many attendees said they felt exhilarated by the prospects of free, flexible cores unencumbered by patents with an ecosystem of innovations around them. Some feared the efforts could undermine existing markets in an industry already tightening its belt in a cold winter of consolidation.

    “RISC-V is the Linux of processor architectures,”

    “This event has the same feel to me as the early Linux gatherings in the 1990’s,” Minnich told EE Times. “You could tell something was happening, but you didn’t know where it was going to go, just that things were going to change,” he said.

    A graphics processor architect for AMD said RISC-V creates a welcome opportunity to try new ideas that would not fly in big companies. He noted a proposal at the event for RISC-V vector instructions contained useful concepts that were quite different from existing Intel and AMD approaches.

    Steve Wallach, a veteran system designer now at Micron, presented ways to use 128-bit addressing to create new levels of security.

    “But like the early days of Linux, [RISC-V] is not really real yet,” said Minnich. “You don’t know what DRAM controller or DRAM to use, and the current chips are tiny 32-bit embedded micros, so we’re still a few years off,” he said.

    The big news from the event was the release of a run of about 250 Arduino boards sporting a 32-bit RISC-V microcontroller from SiFive, a startup that released RTL code for its chip. A larger run is expected in February which may drive board costs down to $39.

    While a welcome milestone, several developers at the event said what they really longed for was a 64-bit processor that can run Linux.

    “We want real hardware,” said one Google developer presenting work on porting its Go language to RISC-V using FPGA simulators. “Don’t we all,” responded an audience member, sparking a round of laughs.

    SiFive is working on just such a board, likely to be unveiled next year. It demoed an FPGA version of its 64-bit, 28nm Freedom Unleashed design booting Linux and running “Doom.”

    A group at Cambridge University is not far behind. It aims to release in February an FPGA development board running its 64-bit Low RISC design and launch a crowd-funding campaign to pay for making an ASIC version.

    It’s unclear how the initial boards will compare with existing ARM and x86 products. Experts say an instruction set is relatively neutral, and implementation choices determine performance. One academic effort showed Coremark/MHz figures that surpassed an ARM Cortex A-15 and approached an Intel Ivy Bridge Xeon.

    Proponents also must port a wealth of existing software to RISC-V, a daunting task that has contributed to the slow advance of ARM’s effort to enable server-class SoCs. Much work on RISC-V software has already been done despite the lack of commercial hardware.

    A significant last mile hurdle stands in the way of anyone wanting a completely open source processor. There are no open source analog or mixed-signal blocks, and foundries have patents associated with their standard cell and I/O libraries.

    Given the costs of making chips, some wonder whether the comparison of RISC-V to Linux is a realistic one.

    Despite the issues, the movement is gaining traction. The RISC-V Foundation maintaining the spec has more than 50 paying members including companies such as AMD, Google, Hewlett Packard Enterprise, Huawei, IBM, Microsoft, Micron, Nvidia, NXP and Qualcomm.

    The latest event attracted 354 registrations from 107 companies.

    “Open source [hardware] is a new thing,”

    “If you lay back, this thing will fail,”

    Reply
14. December 7, 2016 at 1:01 pm

    Tomi Engdahl says:

    8-bit AVR® and PIC® MCUs
    Combined Strength
    http://www.microchip.com/design-centers/8-bit#utm_source=AspenCore_www.eeweb.com&utm_medium=epostcard&utm_term=FY17Q3&utm_content=MCU8&utm_campaign=epostcard

    The AVR and PIC MCU brands represent two dominant architectures in the embedded design universe.

    Our current lineup of AVR and PIC MCUs is the pinnacle of innovation in the 8-bit embedded space and incorporates the latest technologies to enhance system performance while reducing power consumption and development time.

    Reply
15. December 8, 2016 at 11:50 am

    Tomi Engdahl says:

    Passive Components Get Active
    http://electronicdesign.com/passives/passive-components-get-active?NL=ED-003&Issue=ED-003_20161207_ED-003_539_CPY1&sfvc4enews=42&cl=article_1_b&utm_rid=CPG05000002750211&utm_campaign=8814&utm_medium=email&elq2=ac31b514a07641f99f36d0df10b8c2ea

    While semiconductors and software continue to expand the capabilities of electronics products, a new kind of passive component is breaking into the fast lane. The memristor (short for memory varistor, or memory resistor) has been called the fourth type of passive component, with memristive characteristics distinctly different from the familiar resistance, capacitance, and inductance. Memristors were first formalized in 1971, followed by announcement of some of the first commercial-intent devices in 2008, and more recent developments which we reveal here. It seems clear that you will be hearing more about the memristor.

    Reply
16. December 9, 2016 at 9:05 am

    Tomi Engdahl says:

    Analog’s Rising Status
    http://semiengineering.com/analogs-rising-status/

    Uptick in demand low power and power-sensitive designs brings new challenges and opportunities.

    As more sensors and actuators are added into electronic devices, pressure is growing to more seamlessly move data seamlessly back and forth between analog and digital circuitry.

    Analog and digital always have fit rather uncomfortably together, and that discomfort has grown as SoCs are built using smaller feature sizes. While digital transistors can continue to scale to well below 28nm—there is debate now about just how far the digital roadmap will continue—analog is moving at its own pace. In fact, in many cases it isn’t moving at all.

    But if they don’t move at the same pace, at least they have to talk better. That helps explain why at 28nm and 16/14nm, standard “analog” IP includes a fair amount of digital content. And as the IoT pushes up demand for analog content, adding sensors to connect the physical world with electronic devices, the need for even greater interoperability and communication between these two worlds will continue to grow.

    “The demand for analog silicon has always existed in the embedded space, but the advent of the Internet of Things (IoT) is increasing the demand for connected mixed-signal content,”

    Reply
17. December 9, 2016 at 12:29 pm

    Tomi Engdahl says:

    Stanford engineers create prototype chip just three atoms thick
    http://news.stanford.edu/2016/11/29/stanford-engineers-create-prototype-chip-just-three-atoms-thick/

    Ever since scientists discovered that atomically thin materials could have useful electronic properties, engineers have been seeking ways to mass-produce so-called single-layer chips. A new technique shows how it might be done.

    Reply
18. December 12, 2016 at 11:22 am

    Tomi Engdahl says:

    At this week’s IEEE International Electron Devices Meeting (IEDM) in San Francisco, TSMC as well as the team of GlobalFoundries, IBM and Samsung separately presented papers on 7nm finFET technology.

    Qualcomm has begun sampling the world’s first 10nm server processor. As the first in the Qualcomm Centriq product family, the ARM-based processor has up to 48-cores and is built on 10nm finFET process technology, reportedly from Samsung.

    Source: http://semiengineering.com/the-week-in-review-manufacturing-141/

    Reply
19. December 12, 2016 at 12:31 pm

    Tomi Engdahl says:

    ARM Offers Support For TSMC 7nm Manufacturing
    http://www.eetimes.com/document.asp?doc_id=1330963&

    ARM Ltd. announced the availability for evaluation and licensing of its Artisan physical IP platform for the 7nm 7FF FinFET process from TSMC, as well as a design win at that level with Xilinx Inc.

    The IP set does not include support for extreme ultraviolet (EUV) lithography, which is expected to be deployed later.

    “The physical IP platform is available for tape outs in 1H17. We see some engineering samples in 2017,” Ron Moore, vice president of marketing in the physical design group at ARM, told EE Times Europe. However, it is not clear that there is a performance, power or area benefit in selecting the 7FF process over the 10FF process.

    The 10FF was a marked scaling over 16FF+ that could produce a 20 percent speed increase at the same power, or more than 40 percent power reduction at the same speed

    Reply
20. December 12, 2016 at 12:32 pm

    Tomi Engdahl says:

    Broadcom Posts Fiscal Q4 Loss
    http://www.eetimes.com/document.asp?doc_id=1330966&

    Chip vendor Broadcom Ltd. Thursday (Dec. 8) reported a net loss of $668 million on sales of $4.14 billion for the fiscal fourth quarter, which closed Dec. 1.

    The net loss was wider than the net loss of $315 billion Broadcom reported in the fiscal third quarter. Sales, however, increased by 9 percent, Broadcom said.

    The company did report a GAAP net income from continuing operations of $3.47, exceeding analysts expectations.

    Broadcom said it expects sales for the fiscal first quarter of 2017 to be between $3.9 billion and $4.8 billion. The company said it expects capital expenditures for the fiscal first quarter to be roughly $330 million.

    Reply
21. December 12, 2016 at 1:18 pm

    Tomi Engdahl says:

    Dean Takahashi / VentureBeat:
    Nantero raises $21M for ultra-dense carbon nanotube NRAM memory, brings total raised to date to $110M+

    Nantero raises $21 million for ultra-dense carbon nanotube memory
    http://venturebeat.com/2016/12/08/nantero-raises-21-million-for-carbon-nanotube-memory-that-is-50-times-stronger-than-steel/

    Nantero has raised $21 million in funding for its carbon nanotube memory devices, which are an alternative to mainstream semiconductor chips.

    The Woburn, Mass.-based company makes nonvolatile random access memory (NRAM), which can be used in a variety of products, such as smartphones, tablets, enterprise systems, and notebook and desktop computers, as well as applications in the automotive and industrial markets.

    Globespan Capital Partners was the lead investor in the round, which also included participation from new and existing strategic and financial investors.

    “The customer traction we’ve achieved at Nantero has been overwhelming, as evidenced by our recent announcement that NRAM had been selected by both Fujitsu Semiconductor and Mie Fujitsu Semiconductor,” said Greg Schmergel, cofounder and CEO of Nantero, in a statement. “With this additional funding, we will be able to help these existing customers speed their time to market while also supporting the many other companies that have approached us about using Nantero NRAM in their next generation products.”

    Reply
22. December 13, 2016 at 8:02 am

    Tomi Engdahl says:

    TSMC Plans New Fab for 3nm
    http://www.eetimes.com/document.asp?doc_id=1330971&

    Taiwan Semiconductor Manufacturing Co. (TSMC) said that it plans to build its next fab for chips made at the 5-nm to 3-nm technology node as early as 2022 as it aims for industry leadership.

    As the semiconductor industry consolidates, chipmakers TSMC, Samsung, and Intel are in a tight race to lead process technology development and grab profitable business from fabless customers such as Apple and Qualcomm. TSMC is looking more than five years ahead at a fab site in a new science park planned by the Taiwan government near the city of Kaohsiung, on the southern tip of the island.

    Reply
23. December 13, 2016 at 8:07 am

    Tomi Engdahl says:

    Vertically stacked GAA nanowire MOSFETs are a World first
    http://www.electropages.com/2016/12/vertically-stacked-gaa-nanowire-mosfets-world/?utm_campaign=&utm_source=newsletter&utm_medium=email&utm_term=article&utm_content=Vertically+stacked+GAA+nanowire+MOSFETs+are+a+World+first

    The CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs that feature a dual-work-function metal gate enabling matched threshold voltages for the n and p-type devices has been demonstrated for the first time by research centre IMEC.

    This breakthrough is expected to advance the development of GAA nanowire MOSFETs which could replace FinFETs in 7nm technology nodes.

    Reply
24. December 13, 2016 at 8:10 am

    Tomi Engdahl says:

    ACE Awards: AMD Wins Company of Year
    http://www.eetimes.com/document.asp?doc_id=1330959&

    The EE Times and EDN Annual Creativity in Electronics (ACE) Awards honored technology innovators

    This year’s ACE Awards winners and finalists by category are:

    Company of the Year
    Winner: Advanced Micro Devices
    Aquantia
    ON Semiconductor

    Design Team of the Year
    Winner: Palladium Z1 Enterprise Emulation Platform Design Team — Cadence Design Systems, Inc.
    CDNN2 Design Team — CEVA, Inc.
    MAX9286 Automotive Design Team — Maxim Integrated

    Innovator of the Year
    Winner: Bobby Littrell — Vesper
    David Hall — Velodyne LiDAR
    Desmond Wong — TransSiP, Inc.

    Internet of Things Product of the Year
    Winner: Battery Powered Mobile IoT Nursing Workstation — Onyx Healthcare USA, Inc.
    Cassia Hub Bluetooth Router — Cassia Networks
    Valor IoT Manufacturing Solution — Mentor Graphics Corporation

    Software
    Winner: Ultrahaptics Software Development Kit Version 2 — Ultrahaptics North America Incorporated
    Altium Designer 16 — Altium
    Xilinx SDSoC Development Environment — Xilinx

    Reply
25. December 13, 2016 at 8:17 am

    Tomi Engdahl says:

    Switching is Boring, but Essential for Automated Testing
    http://www.eetimes.com/author.asp?section_id=36&doc_id=1330972&

    EE Times Senior Technical Editor Martin Rowe interviews Keith Moore, founder and CEO of Pickering Interfaces, about the state of automated test and the need for switching.

    Switching is one of the test technologies that engineers don’t often think about. Let’s face it: Switching is hardly glamorous, but without it, testing would take far longer. Switches have issues, too. Mechanical switches have low RON resistance but limited lifetimes. Semiconductor switches can have long lives, but signal losses are higher than mechanical switches.

    Automated test stations depend heavily on switching to connect test equipment to DUTs, and many such systems use PXI modular instruments. Indeed, when PXI was first introduced in 1997, there were no switching cards available. It was clear to me even then that, for PXI to succeed, switching cards were needed. Switching cards now connect signals at frequencies from DC to microwave.

    Reply
26. December 13, 2016 at 12:11 pm

    Tomi Engdahl says:

    EDN Hot 100 products of 2016
    http://www.edn.com/electronics-products/other/4443101/EDN-Hot-100-products-of-2016?_mc=NL_EDN_EDT_EDN_productsandtools_20161212&cid=NL_EDN_EDT_EDN_productsandtools_20161212&elqTrackId=d3e3402da12f4ddd9510573557834abd&elq=756e0a28e8ab4cefa3338cf921751782&elqaid=35140&elqat=1&elqCampaignId=30697

    It’s time to recognize the year’s top products with EDN’s annual Hot 100 Products!

    Reply
27. December 13, 2016 at 12:46 pm

    Tomi Engdahl says:

    EU dings Sony, Panasonic over rechargeable battery cartel
    Supergrass Samsung walks free
    http://www.theregister.co.uk/2016/12/13/eu_fines_sony_panasonic_over_battery/

    The great battery scam has reached a milestone in Europe. The European Commission this week imposed a settlement fine of €166m on a trio of Japanese manufacturers for operating the price-fixing cartel.

    Sony, Panasonic and Sanyo used an increase in the price of cobalt as a pretext to collude to fix prices, Competition Commissioner Margrethe Vestager said yesterday. Samsung was spared a fine (put at €57.7m) as it had turned evidence over “reveal[ing] the existence of the cartel to the Commission”. The price-fixing agreement covered lithium iron batteries used in mobile phones, computers and other portable electronic devices between 2004 and 2007.

    Reply
28. December 14, 2016 at 10:14 am

    Tomi Engdahl says:

    Growth Curve Accelerating for Flexible Displays
    http://www.eetimes.com/document.asp?doc_id=1330985&

    Shipments of flexible displays are expected to grow sharply next year as smartphone makers introduced more models with flexible screens. But the real growth trajectory for this technology remains in the immediate years ahead, according to a market research firm IHS Markit.

    Flexible display unit shipments are projected to equal 139 million units next year, comprising nearly 4% of all display shipments, according to IHS. The estimated total of flexible display represents an increase of 135% compared to 2016, the firm said.

    IHS expects flexible display shipments to increase exponentially in the coming years, reach 560 million units in 2023. While smartphones accounted for 76% of flexible display shipments in 2016, the real growth will come as more electronics devices utilize the technology on a widespread basis, including tablets, automotive monitors and TVs, according to IHS.

    “Consumer device manufacturers will eventually move from conventionally designed flat and rectangular form factors to the latest curved, foldable or rollable screens, but only once their product roadmap for newer, innovative devices becomes more mature,”

    Reply
29. December 14, 2016 at 10:15 am

    Tomi Engdahl says:

    Qualcomm Falters at Top Of Fabless Ranking
    http://www.eetimes.com/document.asp?doc_id=1330990&

    Qualcomm CDMA Technologies is set to remain the leading fabless chip company in 2016 despite falling revenue, according to a forecast from TrendForce Corp. (Taipei).

    Qualcomm and several other top ten fabless chip companies will experience declining revenue. Broadcom Ltd., now including Avago, is expected to be runner-up although revenue is down compared with the combined sales of Broadcom and Avago in 2015.

    The successful companies are MediaTek in third place and Nvidia and Realtek, further down the ranking. MediaTek’s success is based on strong penetration of the Chinese smartphone market. Nvidia has established itself in the gaming market and is also benefiting from revenues in datacenters and automotive. AMD has achieved some success with its semi-custom chip business and an expansion from the weak personal computer business into embedded applications.

    Reply
30. December 14, 2016 at 10:15 am

    Tomi Engdahl says:

    China Enters Top Chip Equipment Spenders
    http://www.eetimes.com/document.asp?doc_id=1330983&

    China, which is making a bid to become one of the world’s biggest chipmaking nations, is likely for the first time to be among the top-three spenders on chipmaking equipment in 2016, according to industry association SEMI.

    The big spenders this year will be Taiwan, South Korea and China, SEMI said in a press statement released at the annual SEMICON Japan exhibition in Tokyo. China, with a forecast expenditure of $6.7 billion, will overtake the number-three spot from Japan, coming in at $4.8 billion, according to SEMI.

    Total worldwide spending will increase by 8.7 percent to $39.7 billion, according to the chip industry association, which also forecast an increase in expenditures on chipmaking equipment in 2017 to $43.40 billion.

    Reply
31. December 14, 2016 at 12:21 pm

    Tomi Engdahl says:

    Lurking Behind Every M&A Is China
    http://www.eetimes.com/document.asp?doc_id=1330969

    here has been much buzz in the global semiconductor industry about the accelerated consolidation of chip vendors. But the biggest untold story this year is the presence at the negotiating table — in almost every M&A deal — of Chinese investors, or U.S.-based private equity funds whose money can be traced back to China.

    In deals involving Marvell Technology, Micron, Atmel, Anadigics, Micrel, Pericom Semiconductor, PMC-Sierra, Lattice Semiconductor, Western Digital, and more, Chinese bidders have lurked behind practically every attempted — or speculated — negotiation in the last two years.

    Although few Chinese investors have actually acquired big chip vendors thus far, Chinese bidders continue to swarm U.S. and European high-tech companies, according to several semiconductor company executives, academia, industry veterans, and observers interviewed by EE Times in recent weeks.

    Reply
32. December 15, 2016 at 3:52 pm

    Tomi Engdahl says:

    Non-invasive blood glucose monitoring using near-infrared spectroscopy
    http://www.edn.com/design/systems-design/4422840/Non-invasive-blood-glucose-monitoring-using-near-infrared-spectroscopy

    Blood glucose monitors are used to measure the amount of glucose in blood, especially of patients with symptoms or a history of abnormally high or low blood glucose levels. Most commonly, they enable diabetic patients to administer appropriate insulin doses. The availability of home-use glucometers, as opposed to clinical-use equipment, has greatly improved the quality of life of such individuals. However, such monitors require a blood draw through finger pricks for each test, which causes pain and inconvenience. Each test also requires a new test-strip, contributing to the recurring cost of such a device.

    Optimum insulin dosage, however, requires frequent/continuous monitoring of blood glucose, and currently available glucometers do not address this requirement. Continuous monitors do exist, but they need to be implanted under the skin, causing trauma while being implanted, and they need to be replaced every week. An alternative exists in non-invasive blood glucose monitors. This article introduces an architecture that uses Near Infrared (NIR) spectroscopy to determine blood glucose levels based on transmittance spectroscopy on the ear lobe. Using various body parameters, such as tissue thickness, blood oxygen saturation, and a linear regression-analysis based calibration system, an accurate and real-time architecture is proposed. An example implementation using full analog, digital, and mixed signal capabilities of a programmable system-on-chip, the PSoC-5LP controller from Cypress, is given as well.

    Operating Principle/System Design

    Near Infrared transmittance spectroscopy is used across the ear lobe to measure glucose. Transmittance spectroscopy involves a light source and a light detector positioned on either side of the ear lobe. The amount of near infrared light passing through the ear lobe depends on the amount of blood glucose in that region. The ear lobe was chosen due to the absence of bone tissues and also because of its relatively small thickness [1]. Near Infrared (NIR) light is applied onto one side of the ear lobe, while a receiver on the other side receives the attenuated light.

    Apart from the level of glucose in blood, the transmittance of NIR light also depends on the amount of blood in the path of the light. That is, for the same glucose level, a large amount of blood will result in lower transmittance, whereas less blood will result in a larger transmittance. The glucose value needs to be scaled according to the amount of blood residing inside the ear lobe at a time of measurement. The amount of blood can be estimated by measuring the blood oxygen levels [1]. Pulse Oximetry was used to measure blood oxygen. Pulse Oximetry uses Red and Infrared (IR) light to distinguish between Hemoglobin and Oxy-Hemoglobin in the blood, on which further processing is applied to get the oxygen saturation [2].

    Another physical parameter that affects the glucose measurement is the ear lobe tissue thickness

    All these variables are then amplified, sampled, and processed inside the PSoC5LP, after which they are communicated via Bluetooth to an Android application.

    Reply
33. December 16, 2016 at 12:07 pm

    Tomi Engdahl says:

    BEOL Issues At 10nm And 7nm
    http://semiengineering.com/beol-issues-at-10nm-and-7nm/

    Experts at the table, part 1: Lines blur with middle of line as RC delay increases, reliability and yield become more difficult to achieve, and costs skyrocket.

    Inside Advanced Patterning
    http://semiengineering.com/inside-advanced-patterning/

    What’s in store for chipmakers at 7nm, 5nm and beyond, and why atomic-level etch and deposition are getting new attention.

    Reply
34. December 16, 2016 at 12:08 pm

    Tomi Engdahl says:

    Etching Technology Advances
    http://semiengineering.com/etching-technology-advances/

    Atomic layer etch (ALE) moves to the forefront of chip-making technology—finally.

    That directive from leading semiconductor companies and their customers is forcing the whole semiconductor supply chain to come up with new ways to design and manufacture ever-shrinking dimensions for chips. The current push is to 10nm and 7nm, but R&D into 5nm and 3nm is already underway.

    To put this in perspective, there are roughly two silicon atoms in 1nm of line width in a chip. That helps explain why industry has adopted atomic layer deposition (ALD) first, and why it is now moving to atomic layer etch (ALE).

    Reply
35. December 20, 2016 at 9:00 am

    Tomi Engdahl says:

    SiFive Is Setting Silicon Free with Open-Source Chips
    https://www.designnews.com/electronics-test/sifive-setting-silicon-free-open-source-chips/10136142447173?cid=nl.x.dn14.edt.aud.dn.20161219.tst004c

    Moore’s Law is dead, just not in the way everyone thinks. SiFive believes open source hardware is the way forward for the semiconductor industry.

    Moore’s Law is dead…just not in the way everyone thinks. Technological advances keep allowing chips to scale, but the economics are another story – particularly for smaller companies that can’t afford chips in the volumes that the big chipmakers would like from their customers.

    The solution, according to San Francisco-based startup, SiFive, is open-source hardware, specifically an architecture developed by the company’s founders called RISC-V (pronounced “risk-five”). Done right SiFive, which was awarded Startup of the Year at the 2016 Creativity in Electronics (ACE) Awards, believes that RISC-V will do for the hardware industry what Linux has done for software.

    Reply
36. December 20, 2016 at 9:03 am

    Tomi Engdahl says:

    Global Chip Sales Could Be Flat This Year
    http://www.eetimes.com/document.asp?doc_id=1331024&

    The semiconductor industry may yet be flat in 2016, a remarkable possibility given the pessimism that colored industry forecasts earlier in the year.

    The World Semiconductor Trade Statistics (WSTS) group earlier this month revised its forecast for the year, saying that it now expects 2016 sales to be flat with 2015. The forecast was revised thanks to an industry rebound in recent months that culminated with October seeing the largest year-to-year sales increase since March 2015.

    Reply
37. December 20, 2016 at 9:58 am

    Tomi Engdahl says:

    Massive 20-oz. Copper PCB Enables Electric Racing
    http://hackaday.com/2016/12/16/massive-20-oz-copper-pcb-enables-electric-racing/

    Is twenty times the copper twenty times as much fun to work with? Ask [limpkin] and follow along as he fabricates a DC/DC block for a Formula E race car on 20-oz copper PCBs.

    I just received my 20 ounce PCB… soldering is going to be fun.
    https://www.reddit.com/r/electronics/comments/5i9wxd/i_just_received_my_20_ounce_pcb_soldering_is/

    Reply
38. December 20, 2016 at 12:28 pm

    Tomi Engdahl says:

    Uncertainty Grows For 5nm, 3nm
    http://semiengineering.com/uncertainty-grows-for-5nm-3nm/

    Nanosheets and nanowire FETs under development, but costs are skyrocketing. New packaging options could provide an alternative.

    As several chipmakers ramp up their 10nm finFET processes, with 7nm just around the corner, R&D has begun for 5nm and beyond. In fact, some are already moving full speed ahead in the arena.

    TSMC recently announced plans to build a new fab in Taiwan at a cost of $15.7 billion. The proposed fab is targeted to manufacture TSMC’s 5nm and 3nm processes, which are due out in 2020 and 2022, respectively. Other chipmakers, including GlobalFoundries, Intel and Samsung, also are looking at technologies for 5nm and beyond.

    Both 5nm and 3nm present a multitude of unknowns and challenges. For one thing, the specs of these technologies are murky, if not confusing. And not all of the technologies are alike.

    Regardless, based on the roadmaps from various chipmakers, Moore’s Law continues to slow as process complexities and costs escalate at each node.

    Reply
39. December 20, 2016 at 12:40 pm

    Tomi Engdahl says:

    Fab Tool Spending Grew in November
    http://www.eetimes.com/document.asp?doc_id=1331017&

    he book-to-bill ratio of North American semiconductor equipment vendors moved closer to parity in November thanks to stronger-than-expected fab tool spending as the year moved toward a close.The three-month average of bookings among North American vendors grew to $1.55 billion, up 4% compared to October and up 25% compared to November 2015, according to the semiconductor equipment and materials vendor trade group, SEMI.

    Reply
40. December 20, 2016 at 12:40 pm

    Tomi Engdahl says:

    Europe to Rethink 10/100/20 Chip Project
    http://www.eetimes.com/document.asp?doc_id=1331012&

    The European Commission intends to reconvene a high-level group of European CEOs and executives to exchange views on Europe’s 10/100/20 nanoelectronics and chip manufacturing project and make adjustments as necessary for a wave of European Union investment supposedly starting in 2020, according to industry body SEMI.

    Rania Georgoutsakou, SEMI’s director of public policy for Europe, has written that a recently held closed door meeting of company CEOs and national ministries and other participants came to the conclusion that the EU 10/100/20 strategy “was on track.”

    Europe’s 10/100/20 strategy was launched in 2013 with the goal of raising European chip production to 20% of the global total by 2020. At that time, Europe’s global share was less than 10 percent and had been falling for decades. The three numbers in the project title stand for €10 billion (about $10.4 billion) in public/private research funding, €100 billion spent by industry on manufacturing and achieving 20% of the global chip production market by 2020.

    Reply
41. December 21, 2016 at 9:00 am

    Tomi Engdahl says:

    Hacked Diamond Makes Two-Atom Radio
    http://hackaday.com/2016/12/20/hacked-diamond-makes-two-atom-radio/

    It used to be pretty keen to stuff a radio receiver into an Altoid’s tin, or to whip up a tiny crystal receiver from a razor blade and a pencil stub. But Harvard researchers have far surpassed those achievements in miniaturization with a nano-scale FM receiver built from a hacked diamond.

    When pumped by a green laser, incident FM radio waves in the 2.8 GHz range are transduced into AM fluorescent signals that can be detected with a photodiode and amplifier.

    World’s smallest radio receiver has building blocks the size of two atoms
    http://www.seas.harvard.edu/news/2016/12/world-s-smallest-radio-receiver-has-building-blocks-size-of-two-atoms

    Researchers from the Harvard John A. Paulson School of Engineering and Applied Sciences (SEAS) have made the world’s smallest radio receiver – built out of an assembly of atomic-scale defects in pink diamonds.

    This tiny radio — whose building blocks are the size of two atoms — can withstand extremely harsh environments and is biocompatible, meaning it could work anywhere from a probe on Venus to a pacemaker in a human heart.

    The radio uses tiny imperfections in diamonds called nitrogen-vacancy (NV) centers. To make NV centers, researchers replace one carbon atom in a tiny diamond crystal with a nitrogen atom and remove a neighboring atom — creating a system that is essentially a nitrogen atom with a hole next to it. NV centers can be used to emit single photons or detect very weak magnetic fields. They have photoluminescent properties, meaning they can convert information into light, making them powerful and promising systems for quantum computing, phontonics and sensing.

    Radios have five basic components — a power source, a receiver, a transducer to convert the high-frequency electromagnetic signal in the air to a low-frequency current, speaker or headphones to convert the current to sound and a tuner.

    In the Harvard device, electrons in diamond NV centers are powered, or pumped, by green light emitted from a laser.

    Reply
42. December 21, 2016 at 9:32 am

    Tomi Engdahl says:

    Chips Execs See Maturing Industry
    http://www.eetimes.com/document.asp?doc_id=1331043&

    he semiconductor industry appears to be gathering steam as 2016 comes to a close, but many chip company executives appear to be pessimistic about the prospects for the next few years, according to a recent survey by consulting firm KPMG LLP.

    Nearly half of the 153 semiconductor industry executives to participate in KPMG’s 2017 Global Semiconductor Industry Outlook survey said they believe their industry is in a late expansion phase and another 20% think the industry is currently at an inflection point from expansion to contraction.

    Only about half of the executives served expect revenue to grow and R&D spending to increase over the next three years, according to a summary of the results offered by KPMG. By contrast, the majority of respondents to last year’s survey expected revenue and R&D to grow over the three-year outlook, KPMG said.

    he semiconductor industry appears to be gathering steam as 2016 comes to a close, but many chip company executives appear to be pessimistic about the prospects for the next few years, according to a recent survey by consulting firm KPMG LLP.

    Nearly half of the 153 semiconductor industry executives to participate in KPMG’s 2017 Global Semiconductor Industry Outlook survey said they believe their industry is in a late expansion phase and another 20% think the industry is currently at an inflection point from expansion to contraction.

    Only about half of the executives served expect revenue to grow and R&D spending to increase over the next three years, according to a summary of the results offered by KPMG. By contrast, the majority of respondents to last year’s survey expected revenue and R&D to grow over the three-year outlook, KPMG said.

    According to Lincoln Clark, KPMG global semiconductor industry leader, such pessimism about immediate revenue and R&D growth is a sign of a maturing industry. Lower industry growth rates may be the theme over the next several years, Clark said

    Reply
43. December 21, 2016 at 9:34 am

    Tomi Engdahl says:

    ARM Bolsters HPC Position Through Acquisition
    http://www.eetimes.com/document.asp?doc_id=1331044&

    RM (Cambridge, UK) has announced that it has acquired Allinea Software (San Jose, CA), a leading provider of software tools for high performance computing (HPC); ARM says that this extends its range of development tools to HPC, machine learning and data analytics markets.

    Allinea Software specializes in development and performance analysis tools to maximize the efficiency of software for HPC systems, and claims that 20 of the world’s top 25 supercomputers use its tools, with key customers including the US Department of Energy, NASA, a range of supercomputing national labs and universities, and private companies using HPC systems for scientific computation.

    Allinea’s tools provide developers with the ability to deal with systems with hundreds, thousands (and hundreds of thousands) of cores. The product suite includes the developer tool suite Allinea Forge, which incorporates an application debugger called Allinea DDT and a performance analyzer called Allinea MAP, and an analysis tool for system owners, users and administrators called Allinea Performance Reports.

    “As systems and servers grow in complexity, developers in HPC are facing new challenges that require advanced tools designed to enable them to continue to innovate,” said Javier Orensanz, general manager, development solutions group, ARM. “Allinea’s ability to debug and analyze many-node systems is unique, and with this acquisition we are ensuring that this capability remains available to the whole ARM ecosystem, and to the other CPU architectures prevalent in HPC, as well as in future applications such as artificial intelligence, machine learning and advanced data analytics.”

    Reply
44. December 21, 2016 at 9:35 am

    Tomi Engdahl says:

    TDK in Talks to Buy InvenSense
    http://www.eetimes.com/document.asp?doc_id=1331045&

    DK Corp. (Tokyo) is in talks to acquire inertial and microphone MEMS company InvenSense Inc. (San Jose, Calif.) for about $1.1 billion, according to a Reuters report.

    InvenSense announced that it hired a financial advisor to evaluate indications of interest in the company in November (see Could Sony, ST, Intel or China acquire InvenSense? ).

    Reply
45. December 22, 2016 at 11:13 am

    Tomi Engdahl says:

    DIY Monolithic Power Management ICs
    http://powerelectronics.com/power-management/diy-monolithic-power-management-ics?NL=ED-003&Issue=ED-003_20161221_ED-003_458&sfvc4enews=42&cl=article_2_b&utm_rid=CPG05000002750211&utm_campaign=9019&utm_medium=email&elq2=2271cbd8ce024791a92e1f60703aafd5

    You may not be able to find a commercially-available power management IC (PMIC) that meets your application’s requirements, but there is a way to get the device you need. You can use a new “do-it-yourself” (DIY) design technique, developed by AnDAPT (www.andapt.com), that employs a library of selectable power component building blocks, which in turn are built using analog elementary blocks that can interface with each other. They are offered on an Adaptive Multi-Rail Power (AmP) platform IC. After you select all the desired power component building blocks, software interconnects the analog elementary blocks (called µAnalog by AnDAPT) and creates a ready-to-use monolithic IC tailored to the requirements of the particular application. It’s all transparent to you.

    Reply
46. December 23, 2016 at 9:22 am

    Tomi Engdahl says:

    RF energy: Measurements improve cooking, lighting, and more
    http://www.edn.com/design/test-and-measurement/4443086/RF-energy–Measurements-improve-cooking–lighting–and-more?_mc=NL_EDN_EDT_EDN_weekly_20161222&cid=NL_EDN_EDT_EDN_weekly_20161222&elqTrackId=8d00fa3f5d3f4190bdd47684e3f70341&elq=7f7a6655fed442a2b41fe04a57c5de92&elqaid=35276&elqat=1&elqCampaignId=30827

    A certain person in my household has been known to burn microwave popcorn—fortunately, without starting a fire. What’s really needed here is a microwave oven that detects the changes taking place in food as it cooks and makes the appropriate adjustments. Such an oven is now possible, though it might be a few years before it’s practical and affordable.

    RF energy is on the cusp of bringing changes to cooking, lighting, industrial heating, automotive spark plugs, and a host of other applications. It’s made possible through the development of RF transistors that can provide sufficient power at the right frequencies, namely the 2.45 GHz ISM band. Yes, the same band used by Wi-Fi and Bluetooth.

    Reply
47. December 23, 2016 at 11:22 am

    Tomi Engdahl says:

    Micron’s Successful Quarter Reflects 3D NAND Progress
    “Life is good” for Micron
    http://www.eetimes.com/document.asp?doc_id=1331053&

    Financial analysts attending yesterday’s quarterly update from Micron Technology were congratulating the company on its strong numbers, but the real story might be that it’s mastered 3D NAND.

    “What’s encouraging is where they are with their 3D NAND,”

    Reply
48. December 29, 2016 at 8:06 am

    Tomi Engdahl says:

    TDK Swears by Sensor Fusion in $1.3 Billion Deal for InvenSense
    http://electronicdesign.com/analog/tdk-swears-sensor-fusion-13-billion-deal-invensense?NL=ED-003&Issue=ED-003_20161228_ED-003_916&sfvc4enews=42&cl=article_2_b&utm_rid=CPG05000002750211&utm_campaign=9070&utm_medium=email&elq2=e9f675739f9149679be80121302afc44

    Sensor fusion, a technology that merges data from multiple sensors to make unique conclusions, was the hidden gem in TDK’s recent acquisition of InvenSense, a maker of gyroscopes and other motion sensors.

    TDK agreed last week to pay $1.3 billion for InvenSense, one of the largest makers of gyroscopes for measuring motion and rotation, sending a signal that it wants to prevent machines from ever losing their bearings. It plans to do so with technology that simulates how human senses work in tandem.

    The acquisition is one of the smaller deals in a semiconductor industry that has consolidated around slowing sales and the rising cost of product development. But it also marks a big bet on sensor fusion, a technology that coordinates different to compute something more than could be determined by a lone sensor.

    Reply
49. December 29, 2016 at 8:43 am

    Tomi Engdahl says:

    The actual father of electricity
    http://www.edn.com/electronics-blogs/all-things-measured/4441206/The-actual-father-of-electricity?_mc=NL_EDN_EDT_EDN_today_20161228&cid=NL_EDN_EDT_EDN_today_20161228&elqTrackId=9fa9233895ed443cb8ad674d9379aa3c&elq=f7ea26b1025a499698cbba99dafa41c6&elqaid=35324&elqat=1&elqCampaignId=30873

    The person widely considered the “Father of Electricity” is Sir William Gilbert.

    Sir William Gilbert was born on 24 May 1544 in Colchester, Essex.

    Sir Gilbert’s work led to the coining the term electricity, a term first used by Sir Thomas Browne in 1646. The word derives from Gilbert’s 1600 New Latin electricus, meaning “like amber” because of its attractive properties.

    To his credit, Sir Gilbert’s well-documented experiments, detailed observations, and logical conclusions in order to prove or disprove theories was famously celebrated by one of his contemporaries, who credits him with inventing the scientific method. That contemporary was no other than Galileo. In honor of Sir Gilbert’s many contributions in understanding electrical and magnetic phenomena, the unit for magnetomotive force, the gilbert, was named after him. The gilbert is defined in terms of centimeter-gram-second of magnetomotive force and is equal to 10/4×π ampere-turn.

    Reply
50. December 29, 2016 at 10:58 am

    Tomi Engdahl says:

    Monolithic JFETs are alive and well
    http://www.edn.com/electronics-products/electronic-product-reviews/other/4442559/Monolithic-JFETs-are-alive-and-well?_mc=NL_EDN_EDT_EDN_productsandtools_20161226&cid=NL_EDN_EDT_EDN_productsandtools_20161226&elqTrackId=dbe501d50407498fbe647cb8eb12fdb3&elq=db1acdd5067d4bc1b869906ae295442d&elqaid=35302&elqat=1&elqCampaignId=30849

    Reply