Here is my list of electronics industry trends and predictions for 2016:
There was a huge set of mega mergers in electronics industry announced in 2015. In 2016 we will see less mergers and how well the existing mergers went. Not all of the major acquisitions will succeed. Probably the the biggest challenge in these mega-mergers is “creating merging cultures or–better yet–creating new ones”.
Makers and open hardware will boost innovation in 2016. Open source has worked well in the software community, and it is coming more to hardware side. Maker culture encourages people be creators of technology rather than just consumers of it. A combination of the maker movement and robotics is preparing children for a future in which innovation and creativity will be more important than ever: robotics is an effective way for children as young as four years old to get experience in the STEM fields of science, technology, engineering, mathematics as well as programming and computer science. The maker movement is inspiring children to tinker-to-learn. Popular DIY electronics platforms include Arduino, Lego Mindstorms, Raspberry Pi, Phiro and LittleBits. Some of those DIY electronics platforms like Arduino and Raspberry Pi are finding their ways into commercial products for example in 3D printing, industrial automation and Internet of Things application fields.
Open source processors core gains more traction in 2016. RISC-V is on the march as an open source alternative to ARM and Mips. Fifteen sponsors, including a handful of high tech giants, are queuing up to be the first members of its new trade group for RISC-V. Currently RISC-V runs Linux and NetBSD, but not Android, Windows or any major embedded RTOSes. Support for other operating systems is expected in 2016. For other open source processor designs, take a look at OpenCores.org, the world’s largest site/community for development of hardware IP cores as open source.
GaN will be more widely used and talked about in 2016. Gallium nitride (GaN) is a binary III/V direct bandgap semiconductor commonly used in bright light-emitting diodes since the 1990s. It has special properties for applications in optoelectronic, high-power and high-frequency devices. You will see more GaN power electronics components because GaN – in comparison to the best silicon alternative – will enable higher power density through the ability to switch at high frequencies. You can get GaN devices for example from GaN Systems, Infineon, Macom, and Texas Instruments. The emergence of GaN as the next leap forward in power transistors gives new life to Moore’s Law in power.
Power electronics is becoming more digital and connected in 2016. Software-defined power brings to bear critical need in modern power systems. Digital Power was the beginning of software-defined power using a microcontroller or a DSP. Software-defined power takes this to another level. Connectivity is the key to success for software-defined power and the PMBus will enable the efficient communication and connection between all power devices in computer systems. It seems that power architectures to become software defined, which will take advantage of digital power adaptability and introduce software control to manage the power continuously as operating conditions change. For example adaptive voltage scaling (AVS) is supported by the AVSBus is contained in the newest PMBus standard V 1.3. The use of power-optimization software algorithms and the concept of the Software Defined Power Architecture (SDPA) are all being seen as part of a brave new future for advanced board-power management.
Nanowires and new forms of memory like RRAM (resistive random access memory) and spintronics are also being researched, and could help scale down chips. Many “exotic” memory technologies are in the lab, and some are even in shipping product: Ferroelectric RAM (FRAM), Resistive RAM (ReRAM), Magnetoresistive RAM (MRAM), Nano-RAM (NRAM).
Nanotube research has been ongoing since 1991, but there has been long road to get practical nanotube transistor. It seems that we almost have the necessary parts of the puzzle in 2016. In 2015 IBM reported a successful auto-alligment method for placing them across the source and drain. Texas Instruments is now capable of growing wafer scale graphene and the Chinese have taken the lead in developing both graphene and nanotubes according to Lux Research.
While nanotubes provide the fastest channel material available today, III-V materials like gallium arsenide (GaAs) and indium gallium arsenide (InGaAs) are all being explored by IBM, Intel, Imec and Samsung as transistor channels on silicon substrates. Dozen of researchers worldwide are experimenting with black phosphorus as an alternative to nanotubes and graphene for the next generation of semiconductors. Black phosphorus has the advantage of having a bandgap and works well alongside silicon photonics device. 3-Molybdenum disulphide MoS2 is also a contender for the next generation of semiconductors, due to its novel stacking properties.
Graphene has many fantastic properties and there has been new finding in it. I think it would be a good idea to follow development around magnetized graphene. Researchers make graphene magnetic, clearing the way for faster everything. I don’t expect practical products in 2016, but maybe something in next few years.
Optical communications is integrating deep into chips finally. There are many new contenders on the horizon for the true “next-generation” of optical communications with promising technologies in development in labs and research departments around the world. Silicon photonics is the study and application of photonic systems which use silicon as an optical medium. Silicon photonic devices can be made using existing semiconductor fabrication. Now we start to have technology to build optoelectronic microprocessors built using existing chip manufacturing. Engineers demo first processor that uses light for ultrafast communications. Optical communication could also potentially reduce chips’ power consumption on inter-chip-links and enable easily longer very fast links between ICs where needed. Two-dimensional (2D) transition metal dichalcogenides (TMDCs), which may enable engineers to exceed the properties of silicon in terms of energy efficiency and speed, moving researchers toward 2D on-chip optoelectronics for high-performance applications in optical communications and computing. To build practical systems with those ICs, we need to figure out how make easily fiber-to-chip coupling or how to manufacture practical optical printed circuit board (O-PCB).
Look development at self-directed assembly.Researchers from the National Institute of Standards and Technology (NIST) and IBM have discovered a trenching capability that could be harnessed for building devices through self-directed assembly. The capability could potentially be used to integrate lasers, sensors, wave guides and other optical components into so called “lab-on-a-chip” devices.
Smaller chip geometries are come to mainstream in 2016. Chip advancements and cost savings slowed down with the current 14-nanometer process, which is used to make its latest PC, server and mobile chips. Other manufacturers are catching to 14 nm and beyond. GlobalFoundries start producing a central processing chip as well as a graphics processing chip using 14nm technology. After a lapse, Intel looks to catch up with Moore’s Law again with with upcoming 10-nanometer and 7-nm processes. Samsung revealed that it will soon begin production of a 10nm FinFET node, and that the chip will be in full production by the end of 2016. This is expected to be at around the same time as rival TSMC. TSMC 10nm process will require triple patterning. For mass marker products it seems that 10nm node, is still at least a year away. Intel delayed plans for 10nm processors while TSMC is stepping on the gas, hoping to attract business from the likes of Apple. The first Intel 10-nm chips, code-named Cannonlake, will ship in 2017.
Looks like Moore’s Law has some life in it yet, though for IBM creating a 7nm chip required exotic techniques and materials. IBM Research showed in 2015 a 7nm chip will hold 20 billion transistors manufactured by perfecting EUV lithography and using silicon-germanium channels for its finned field-effect transistors (FinFETs). Also Intel revealed that the end of the road for Silicon is nearing as alternative materials will be required for the 7nm node and beyond. Scaling Silicon transistors down has become increasingly difficult and expensive and at around 7nm it will prove to be downright impossible. IBM development partner Samsung is in a race to catch up with Intel by 2018 when the first 7nm products are expected. Expect Silicon Alternatives Coming By 2020. One very promising short-term Silicon alternative is III-V semiconductor based on two compounds: Indium gallium arsenide ( InGaAs ) and indium phosphide (InP). Intel’s future mobile chips may have some components based on gallium nitride (GaN), which is also an exotic III-V material.
Silicon and traditional technologies continue to be still pushed forward in 2016 successfully. It seems that the extension of 193nm immersion to 7nm and beyond is possible, yet it would require octuple patterning and other steps that would increase production costs. IBM Research earlier this year beat Intel to the 7nm node by perfecting EUV lithography and using silicon-germanium channels for its finned field-effect transistors (FinFETs). Taiwan Semiconductor Manufacturing Co. (TSMC), the world’s largest foundry, said it has started work on a 5nm process to push ahead its most advanced technology. TSMC’s initial development work at 5nm may be yet another indication that EUV has been set back as an eventual replacement for immersion lithography.
It seems that 2016 could be the year for mass-adoption of 3D ICs and 3D memory. For over a decade, the terms 3D ICs and 3D memory have been used to refer to various technologies. 2016 could see some real advances and traction in the field as some truly 3D products are already shipping and more are promised to come soon. The most popular 3D category is that of 3D NAND flash memory: Samsung, Toshiba, Sandisk, Intel and Micron have all announced or started shipping flash that uses 3D silicon structure (we are currently seeing 128Gb-384Gb parts). Micron’s Hybrid Memory Cube (HMC) uses stacked DRAM die and through-silicon vias (TSVs) to create a high-bandwidth RAM subsystem with an abstracted interface (think DRAM with PCIe). Intel and Micron have announced production of a 3D crosspoint architecture high-endurance (1,000× NAND flash) nonvolatile memory.
The success of Apple’s portable computers, smartphones and tablets will lead to the fact that the company will buy as much as 25 per cent of world production of mobile DRAMs in 2016. In 2015 Apple bought 16.5 per cent of mobile DRAM.
After COP21 climate change summit reaches deal in Paris environmental compliance 2016 will become stronger business driver. Increasingly, electronics OEMs are realizing that environmental compliance goes beyond being a good corporate citizen. On the agenda for these businesses: climate change, water safety, waste management, and environmental compliance. Keep in mindenvironmental compliance requirements that include the Waste Electrical and Electronic Equipment (WEEE) directive, Restriction of Hazardous Substances Directive 2002/95/EC (RoHS 1), and Registration, Evaluation, Authorization and Restriction of Chemicals (REACH). It’s a legal situation: If you do not comply with regulatory aspects of business, you are out of business. Some companies are leading the parade toward environmental compliance or learning as they go.
Connectivity is proliferating everything from cars to homes, realigning diverse markets. It needs to be done easily for user, reliably, efficiently and securely.It is being reported that communications technologies are responsible for about 2-4% of all of carbon footprint generated by human activity. The needs for communications and faster speeds is increasing in this every day more and more connected world – penetration of smart devices there was a tremendous increase in the amount of mobile data traffic from 2010 to 2014.Wi-Fi has become so ubiquitous in homes in so many parts of the world that you can now really start tapping into that by having additional devices. When IoT is forecasted to be 50 billion connections by 2020, with the current technologies this would increase power consumption considerably. The coming explosion of the Internet of Things (IoT) will also need more efficient data centers that will be taxed to their limits.
The Internet of Things (IoT) is enabling increased automation on the factory floor and throughout the supply chain, 3D printing is changing how we think about making components, and the cloud and big data are enabling new applications that provide an end-to-end view from the factory floor to the retail store. With all of these technological options converging, it will be hard for CIOs, IT executives, and manufacturing leaders keep up. IoT will also be hard for R&D.Internet of Things (IoT) designs mesh together several design domains in order to successfully develop a product. Individually, these design domains are challenging. Bringing them all together to create an IoT product can place extreme pressure on design teams. It’s still pretty darn tedious to get all these things connected, and there’s all these standards battles coming on. The rise of the Internet of Things and Web services is driving new design principles as Web services from companies such as Amazon, Facebook and Uber are setting new standards for user experiences. Designers should think about building their products so they can learn more about their users and be flexible in creating new ways to satisfy them – but in such way that the user’s don’t feel that they are spied on what they do.
Subthreshold Transistors and MCUs will be hot in 2016 because Internet of Things will be hot in 2016 and it needs very low power chips. The technology is not new as cheap digital watches use FETs operating in the subthreshold region, but decades digital designers have ignored this operating region, because FETs are hard to characterize there. Now subthreshold has invaded the embedded space thanks to Ambiq’s new Apollo MCU. PsiKick Inc. has designed a proof-of-concept wireless sensor node system-chip using conventional EDA tools and a 130nm mixed-signal CMOS that operates with sub-threshold voltages and opening up the prospect of self-powering Internet of Things (IoT) systems. I expect also other sub-threshold designs to emerge. ARM Holdings plc (Cambridge, England) is also working at sub- and near-threshold operation of ICs. TSMC has developed a series of processes characterized down to near threshold voltages (ULP family for ultra low power are processes). Intel will focus on its IoT strategy and next-generation low voltage mobile processors.
FPGAs in various forms are coming to be more widely use use in 2016 in many applications. They are not no longer limited to high-end aerospace, defense, and high-end industrial applications. There are different ways people use FPGA. Barrier of entry to FPGA development have lowered so that even home makers can use easily FPGAs with cheap FPGA development boards, free tools and open IP cores. There was already lots of interest in 2015 for using FPGA for accelerating computations as the next step after GPU. Intel bought Altera in 2015 and plans in 2016 to begin selling products with a Xeon chip and an Altera FPGA in a single package – possibly available in early 2016. Examples of applications that would be well-suited for use of ARM-based FPGAs, including industrial robots, pumps for medical devices, electric motor controllers, imaging systems, and machine vision systems. Examples of ARM-based FPGAs are such as Xilinx’s Zynq-7000 and Altera’s Cyclone V intertwine. Some Internet of Things (IoT) application could start to test ARM-based field programmable gate array (FPGA) technology, enabling the hardware to be adaptable to market and consumer demands – software updates on such systems become hardware updates. Other potential benefits would be design re-use, code portability, and security.
The trend towards module consolidation is applicable in many industries as the complexity of communication, data rates, data exchanges and networks increases. Consolidating ECU in vehicles is has already been big trend for several years, but the concept in applicable to many markets including medical, industrial and aerospace.
It seems to be that AXIe nears the tipping point in 2016. AXIe is a modular instrument standard similar to PXI in many respects, but utilizing a larger board format that allows higher power instruments and greater rack density. It relies chiefly on the same PCI Express fabric for data communication as PXI. AXIe-1 is the uber high end modular standard and there is also compatible AXIe-0 that aims at being a low cost alternative. Popular measurement standard AXIe, IVI, LXI, PXI, and VXI have two things in common: They each manage standards for the test and measurement industry, and each of those standards is ruled by a private consortium. Why is this? Right or wrong, it comes down to speed of execution.
These days, a hardware emulator is a stylish, sleek box with fewer cables to manage. The “Big Three” EDA vendors offer hardware emulators in their product portfolios, each with a distinct architecture to give development teams more options. For some offerings emulation has become a datacenter resource through a transaction-based emulation mode or acceleration mode.
LED lighting is expected to become more intelligent, more beautiful, more affordable in 2016. Everyone agrees that the market for LED lighting will continue to enjoy dramatic year-on-year growth for at least the next few years. LED Lighting Market to Reach US$30.5 Billion in 2016 and Professional Lighting Markets to See Explosive Growth. Some companies will win on this growth, but there are also losers. Due currency fluctuations and price slide in 2015, end market demands in different countries have been much lower than expected, so smaller LED companies are facing financial loss pressures. The history of the solar industry to get a good sense of some of the challenges the LED industry will face. Next bankruptcy wave in the LED industry is possible. The LED incandescent replacement bulb market represents only a portion of a much larger market but, in many ways, it is the cutting edge of the industry, currently dealing with many of the challenges other market segments will have to face a few years from now. IoT features are coming to LED lighting, but it seem that one can only hope for interoperability
Other electronics trends articles to look:
Hot technologies: Looking ahead to 2016 (EDN)
CES Unveiled NY: What consumer electronics will 2016 bring?
Analysts Predict CES 2016 Trends
LEDinside: Top 10 LED Market Trends in 2016
961 Comments
Tomi Engdahl says:
Objects connected to the Internet devices require their own memory, but modern techniques tend to be too resource hungry to it. Adesto Technologies has developed a new memory that consumes 10-100 times the existing non-volatile memory technologies less power.
Adesto invites the Mavriq-Circles technology behind the acronym CBRAM (Conductive Bridging RAM). It is reportedly the world’s first commercial product had time to resistive or ReRAM memory technology.
CBRAM works so that it forms the link between the two electrodes.
One big advantage of CBRAM memory is compatible with the standard CMOS process.
Source: http://etn.fi/index.php?option=com_content&view=article&id=4013:uusi-muisti-kukistaa-flashin&catid=13&Itemid=101
Tomi Engdahl says:
Variable Instruction Computing: What Is Old Is New Again
http://hackaday.com/2016/02/19/variable-instruction-computing-what-is-old-is-new-again/
Every twenty to twenty-five years, trends and fads start reappearing. 2016 is shaping up to be a repeat of 1992; the X-files is back on the air, and a three-way presidential election is a possibility. Star Trek is coming back, again.
For the last few years, Soft Machines, a fabless semiconductor company running in stealth mode, released the first preview for an entirely new processor architecture. This new architecture, VISC, offers higher performance per Watt than anything available on the market. If you’ve been paying attention for the last decade or so, the future of computing isn’t 200-Watt space heaters that also double as powerful CPUs. The future is low power machines that are good enough to run Facebook or run some JavaScript. With servers, performance per Watt is possibly the most important metric. How will Soft Machines upend the semiconductor market with new processors and new architectures? If you know your history, it shouldn’t be a surprise.
Different ISAs mean different performance, and this also means different power requirements for certain applications running on different processors. ARM chips are making inroads into the server market simply because of a key metric: performance per Watt. This is the key factor behind Soft Machine’s research: to produce a CPU with the highest performance per Watt. Their ISA is called VISC. That’s technically not an acronym for Variable Instruction Set Computing, but it’s descriptive enough to tell you what it is. VISC is a completely new ISA that translates x86 and ARM instructions into something else that offers much more performance per Watt.
Yes, This Does Sound Familiar
Transmeta’s Crusoe and Efficeon CPUs weren’t x86 chips. Instead, the x86 instructions would be converted via ‘code-morphing software’ into native instructions. These native instructions would run more efficiently in low power devices, but at a cost: an interpreter, a runtime, and a translator for x86 instructions was required. This would need to be installed on every device with a Transmeta CPU.
Unfortunately, Transmeta was a victim of the dot-com bubble, eventually shutting down their engineering division in 2007.
History Doesn’t Repeat Itself, But It Does Rhyme
SoftMachineThere are significant differences between Soft Machine and Transmeta. Soft Machine is doing everything in silicon, and not relying on software translators to turn x86 into whatever VISC actually stands for. There’s another trick up Soft Machine’s sleeve: multiple, virtual cores. This is a lot like how hyperthreading on Intel CPUs make a quad-core CPU appear as an eight-core CPU.
Tomi Engdahl says:
ARM Unveils New, High Efficency CPU
http://hackaday.com/2016/02/23/arm-unveils-new-high-efficency-cpu/
ARM has announced their latest IP core the Cortex A32. This 32-bit chip brings the benefits of the ARMv8-A architecture to low-power devices, ostensibly ones that will be the backbone of the Internet of Things.
For the last few years, the state of ARM CPUs has been firmly planted in the world of ARMv7 instructions. These chips, the Cortex A5, A7, A9, A15, and A17 are divided into ‘good, better, best’ segments, with the A7 pulling its weight as the processor in the Raspberry Pi 2, and a dual-core A15 finding its way into the latest BeagleBoard.
So what does this announcement mean for the next generation of the Internet of Things, single board computers, and the wearable electronics of tomorrow? Absolutely nothing. Only the processor IP was released, and it will take at least a year for this core to make it into a chip. It will be 18 to 24 months until you can find this core in a consumer device.
New Ultra-efficient ARM Cortex-A32 Processor Expands Embedded and IoT Portfolio
https://www.arm.com/about/newsroom/new-ultra-efficient-arm-cortex-a32-processor-expands-embedded-and-iot-portfolio.php
Tomi Engdahl says:
Wall Street Journal:
Sharp and Foxconn extend talks at least a week past original Feb. 29 deadline as Sharp’s stock drops over 11% over uncertainty around takeover bid
Sharp Races to Save Foxconn Deal, as Share Price Plummets
Companies agree to extend deal’s deadline at least a week past original Feb. 29 date
http://www.wsj.com/article_email/sharp-says-foxconn-takeover-talks-are-ongoing-1456465632-lMyQjAxMTE2MTI2NjMyMzYwWj
Taiwanese electronics assembler Foxconn Technology Group and Japan’s Sharp Corp. scrambled to salvage their proposed marriage as investors questioned whether the companies could restore trust in each other after an 11th-hour breakdown in takeover talks.
On Friday, as Sharp’s shares tumbled in Japan, Chief Executive Kozo Takahashi flew to Shenzhen, China, to meet Foxconn Chairman Terry Gou, according to people familiar with the situation.
“We hope to reach a satisfactory agreement as soon as possible,” Foxconn said.
Tomi Engdahl says:
Small is beautiful: the most powerful 8-bit
Embedded World trade fair widely presents the new 32-bit driver circuits, but not the 8-bit not dead yet. Atmel introduced the 8-bit tinyAVR control of one kilo of flash memory, which it says the market efficient.
Where 8-bit driver is needed then? According to Atmel’s well in many devices, consumer electronics, industrial and home automation. Above all, the 8-bit is the possibility of replacing some of the logic circuits and to get the cheaper the unit cost.
Source: http://etn.fi/index.php?option=com_content&view=article&id=4028:pieni-on-kaunista-tehokkain-8-bittinen&catid=13&Itemid=101
Tomi Engdahl says:
Samsung Doubles UFS Capacity, Performance
http://www.eetimes.com/document.asp?doc_id=1329042&
Samsung has doubled the capacity and speed of its Universal Flash Storage (UFS) memory, announcing what it said is the industry’s first 256GB UFS aimed for use in high-end mobile devices.
The update coincided with this year’s Mobile World Congress in Barcelona, Spain. Samsung is now mass-producing the embedded memory based on the UFS 2.0 standard, the company said in a news release. To put its capacity into perspective, one 256GB UFS chip can store about 47 full HD movies.
Tomi Engdahl says:
February’s Top Medtech Megamergers
http://www.eetimes.com/author.asp?section_id=36&doc_id=1329046&
This month saw a slew of medical device M&A deals, though they were mostly only a “few” billion dollars a piece.
2015 was the biggest year for M&A in the history of the medical device industry. It is only February, but this year is looking similar.
February so far has seen at least five major medical device industry M&A deals—worth more than $13 billion.
Tomi Engdahl says:
Advances make MEMS sensors easier to integrate
http://www.edn.com/electronics-blogs/sensor-ee-perception/4441464/Advances-make-MEMS-sensors-easier-to-integrate?_mc=NL_EDN_EDT_EDN_today_20160225&cid=NL_EDN_EDT_EDN_today_20160225&elqTrackId=483c36a0237b4f649b21047ecfe5f775&elq=72592c709797475691759b7e664d1b2e&elqaid=31044&elqat=1&elqCampaignId=27138
The integration of microeletromechanical systems (MEMS) with classic CMOS processes has long been a challenge, with only incremental gains over the years. However, now that MEMS sensors are foundational to the IoT, there is a renewed sense of urgency around solving the MEMS integration conundrum.
Also, as wearables and the healthcare industries now turn to ultra-low-power devices with a smaller footprint, this only increases the pressure for sensor vendors to create smarter MEMS products that address the cost, footprint, and power issues facing the IoT industry at large.
To help with this, the MEMS industry is tackling the integration challenges head on at the package, wafer, and die levels, respectively, starting with multiple MEMS sensors that are now being integrated into either smart miniaturized modules or in system-in-package (SiP) devices.
Some companies are now looking into packaging bare-die MEMS sensors onto SiP devices. For now, however, more modest SiP solutions for MEMS parts are available, and they offer sensors like accelerometers and the interface chip housed in the same package.
These basic SiPs are mostly found in automotive safety applications.
However, medical and wearable devices are pushing for smaller and more efficient SiPs that support aggressive form factors and low-power operations
Tomi Engdahl says:
18-bit ADC touts multiplexed inputs
http://www.edn.com/electronics-products/other/4441496/18-bit-ADC-touts-multiplexed-inputs?_mc=NL_EDN_EDT_EDN_today_20160224&cid=NL_EDN_EDT_EDN_today_20160224&elqTrackId=6db9596bb33341b0af71cd50e171e833&elq=332d63f5118d4655b50ab2c909b9634a&elqaid=31025&elqat=1&elqCampaignId=27121
The LTC2335-18 from Linear Technology is an 18-bit, 8-channel SAR (successive approximation register) ADC with independently configurable input voltage ranges. Each SoftSpan input can be software-configured on a conversion-by-conversion basis to accept ±10.24-V, 0-V to 10.24-V, ±5.12-V, or 0-V to 5.12-V true bipolar input signals. Alternatively, the device can be programmed to cycle through a sequence of channels and ranges.
Differential analog inputs operate over a wide -16.50-V to 34-V common-mode range. This input signal flexibility combines with a signal-to-noise ratio of 96.7 dB and a throughput of 1 Msample/s.
http://www.linear.com/product/ltc2335-18
Tomi Engdahl says:
MCP6N16
http://www.microchip.com/wwwproducts/en/MCP6N16#utm_source=Aspen-Lab_EEWeb.com&utm_medium=ePostcard&utm_term=FY16Q4&utm_content=MSLD&utm_campaign=ePostcard
The MCP6N16 is a zero-drift instrumentation amplifier designed for single-supply operation with rail-to-rail input (no common mode crossover distortion) and output performance. The supply voltage range is low enough to support many portable applications. All devices are fully specified from -40ºC to +125ºC. Each device has EMI filters at the input pins, providing superior EMI rejection. This family has three minimum gain options (1, 10 and 100 V/V) in order to allow the user to optimize the input offset voltage and input noise for different applications.
Tomi Engdahl says:
ARM Cortex-R8 raises realtime performance
http://www.edn.com/electronics-products/other/4441459/ARM-Cortex-R8-raises-realtime-performance?_mc=NL_EDN_EDT_EDN_today_20160222&cid=NL_EDN_EDT_EDN_today_20160222&elqTrackId=fad6b099a8c84e17b9ee2f37dd1223b7&elq=6fa65dec2f994f9c8a02a3ca9e21f509&elqaid=30970&elqat=1&elqCampaignId=27073
The ARM Cortex-R8 processor unveiled by the Cambridge-based IP company is expected to help chip designers double the performance of ARM-based modem and mass storage device SoCs.
A quad-core configuration dramatically boosts the total Cortex-R8 performance, which when combined with its real time features and extended low-latency memory makes Cortex-R8 the highest performing processor in its class, says the company.
Tomi Engdahl says:
SensorTape Unrolls New Sensor Deployment Possibilities
http://hackaday.com/2016/02/29/sensortape-unrolls-new-sensor-deployment-possibilities/
An embedded MEMS sensor might be lots of fun to play with on your first foray into the embedded world–why not deploy a whole network of them? Alas, the problem with communicating with a series of identical sensors becomes increasingly complicated as we start needing to handle the details of signal integrity and the communication protocols to handle all that data. Fortunately, [Artem], [Hsin-Liu], and [Joseph] at MIT Media Labs have made sensor deployment as easy as unraveling a strip of tape from your toolkit. They’ve developed SensorTape, an unrollable, deployable network of interconnected IMU and proximity sensors packaged in a familiar form factor of a roll of masking tape.
For communications MIT Media labs picked a combination of I²C and peer-to-peer serial.
SensorTape
https://vimeo.com/155159411
SensorTape is a modular and dense sensor network in a form factor of a tape. It enables intuitive deployment of sensor arrays, as SensorTape is modular, it can be cut and joined in an arbitrary order.
SensorTape is just a research prototype at this point, but we may explore turning it into a product in the near future.
Tomi Engdahl says:
Startup, with Mixed-Signal ASICs, to Boost 4G Capacity
http://www.eetimes.com/document.asp?doc_id=1329054&
No doubt 5G is coming to save a mobile world that’s struggling to keep up with the explosion in data traffic. But mobile network operators must find a solution — not in 2020, but today.
Blue Danube Systems, a Mountain View, Calif.-based startup armed with a unique 3D beam-forming technology, came to the Mobile World Congress to pitch high-definition antenna systems that increase by tenfold the average LTE spectrum efficiency of a typical base station.
Historically, building new towers, adding more spectrum and bringing small cells were the options available for network service providers. However, Pinto said that small cells aren’t spreading as fast as initially thought, largely due to cost issues associated with siting and wiring. “There are also issues in managing interferences among small cells,” he added. Naturally, putting up new towers isn’t cheap, either.
5G is viewed as the answer to capacity issues, “But that [standardization] is going to be a while,” Pinto said. “We think we have a true breakthrough based on our proprietary VLSI design.”
Blue Danube Systems believes it can offer beam-forming solutions that integrate easily with LTE at “commercially viable cost.”
Pinto explained that there is nothing new about beam-forming itself.
The technique is used in sensor arrays for directional signal transmission or reception. It’s common in military radar. The 5G technical committee is also discussing the use of massive antennas for beam-forming.
The system, designed to form highly precise 3D beams by using a large number of array elements, deploys low-cost RF components.
Assume, for example, 100 elements inside a single box. The Blue Danube’s mixed-signal ASICs can keep them all synchronized and calibrated.
The real key to Blue Danube’s system, though, is that it can be used by mobile operators for capacity increase without making big changes in today’s 4G/LTE infrastructure.
More specifically, Blue Danube’s high definition antenna systems can be quickly installed at existing antenna locations using conventional mounting techniques. They are also fully compatible with LTE 3GPP Release 8 and above, said Pinto.
Tomi Engdahl says:
Designing in ESD ruggedness
http://www.edn.com/design/systems-design/4441444/Designing-in-ESD-ruggedness?_mc=NL_EDN_EDT_pcbdesigncenter_20160222&cid=NL_EDN_EDT_pcbdesigncenter_20160222&elqTrackId=8a36059bc0454cb68bd15212bfbc538a&elq=d432fd139dc541a385d9283877797c5c&elqaid=30960&elqat=1&elqCampaignId=27067
ESD panel at DesignCon 2016 provided attendees with some solid advice and cool demos regarding best practices for designing ESD-resistant products, and troubleshooting ones that are having problems.
Ken Wyatt kicked things off with a look at some basic ESD considerations like physical design and transient suppressor usage. For example, instead of relying on the PCB to conduct a discharge, a separate metal sheet, chassis or otherwise, is much more likely to keep you out of trouble.
Both Ken, and fellow consultant Doug Smith, showed a number of low-cost, DIY ESD generators and detectors. Ken’s generators included a piezo-powered Coleman-brand lighter (only that brand can spark without turning on the butane
Doug demonstrated another low-cost (if less tasty) ESD generator: a plastic rule with a foil spark-gap pattern glued onto it
Some of the design practices they espoused were: tablet/phone system grounding sponges & gaskets, software recovery from ESD events, guarding and caging of sensitive PCB traces, and proper placement of transient suppressors.
Tomi Engdahl says:
What good is state-of-the-art high-speed electronics without good connectivity?
http://www.edn.com/electronics-products/electronic-product-reviews/designcon/4441515/What-good-is-state-of-the-art-high-speed-electronics-without-good-connectivity-?_mc=NL_EDN_EDT_EDN_productsandtools_20160229&%3bcid=NL_EDN_EDT_EDN_productsandtools_20160229&%3b&elqTrackId=33d4470ff4904816b72a91944f06a939&elq=69807f184eeb44d0b7f85da4169dd3d7&elqaid=31086&elqat=1&elqCampaignId=27177
We often tend to forget about connectors and cables when we discuss the amazing speeds and bandwidths in today’s systems. Design engineers need speed, scalability, space-savings, reduced thermals, power and reach and the weakest link in the system can be the transmission media cables and PC board/Mother board. All the goodness of the super-speed FPGAs, processors and other ICs can be negated by an inferior architecture to carry those signals from place to place.
TE will be the first to develop microQSFP connectors and cages in accordance with the new specification released by the microQSFP Multi-Source Agreement (MSA) group on January 15, 2016. TE took the lead in forming the microQSFP MSA, and say they expect to have standards-compliant products in the market during the first half of 2016. See Figure 3 for the microQSFP, 200 Gbps, PAM-4 copper cable demo at DesignCon
ust when I thought it couldn’t get any better, we walked over to the microQSFP 72 port system thermal demo. This demo used a 1RU 19” form factor with 72 I/o ports—Quad channel x4 with three-high port stacking, and a power load of up to 75W per port with less than a 72oC module case temperature. There was 7.2 Tbps of external I/O throughput with the microQSFP form factor
Finally, we saw the advanced family of STRADA Whisper high speed backplane connectors, with an expanded range of configurations including direct plug orthogonal, mezzanine, and cables all delivering at least 50 Gigabit per second (Gbps).
So don’t underestimate the value of connectivity in your design; your system is only as good as the weakest link in the design and it does not have to be the high speed transmission system.
Tomi Engdahl says:
Resource-rich MCU targets wearable IoT
http://www.eetimes.com/document.asp?doc_id=1329059&
It seems like a contradiction in terms to talk about a resource-rich MCU in conjunction with the small, battery-powered application space that is wearables. But ARM aims to resolve that contradiction with its recent release of the Cortex-A32 processor. The combination of processor architecture and process technology in the new device does just that, boasting a 25% more efficient 32-bit core in as little as 0.25 mm2 of silicon.
The Cortex-A32 is built on ARM’s ARMv8-A architecture and represents an upgrade path for the popular A-5 and A7 architectures used in many 32-bit application processors
The A32 is designed for scalability to address a range of applications. At the high end, a quad-core device can operate at GHz clock speeds, consuming less than 75 mW per core. In its smallest configuration, a 100 MHz single-core A32 with AMBA interface and 8k each of instruction and data cache takes less than 4 mW of power.
Tomi Engdahl says:
Memory chips cut power in connected devices
http://www.edn.com/electronics-products/other/4441516/Memory-chips-cut-power-in-connected-devices?_mc=NL_EDN_EDT_EDN_today_20160229&cid=NL_EDN_EDT_EDN_today_20160229&elqTrackId=7697ea0b6eb9402584e6e4e3426dabcc&elq=edb34f689fce417a8a85f4c04c6d5805&elqaid=31079&elqat=1&elqCampaignId=27172
Adesto Technologies reports that its Moneta nonvolatile serial memories consume 50 to 100 times less power during read and write operations than comparable devices. Based on the company’s CBRAM (Conductive Bridging RAM) resistive technology, the parts reduce overall system energy use in connected devices, including Internet of Things, wearables, medical, and industrial products.
Moneta gives designers the flexibility to extend battery life and/or use smaller batteries to power their systems. Devices have an active read current of less than 10 µA at 500 kbps. Write current is 10 µA at 10 kbps. An automatic ultra-deep power-down mode reduces current consumption to just 35 nA.
http://www.adestotech.com/products/moneta-2/
Tomi Engdahl says:
Cisco Rolls 16nm ASICs
Switch chips chop Broadcom Tomahawk
http://www.eetimes.com/document.asp?doc_id=1329058&
Cisco Systems is shipping its first 16nm ASICs in switches that are part of new data center products announced today (Mar. 1). The ASICs leapfrog features offered by Broadcom whose 28nm chips are used in a wide swath of switches made by Cisco and its competitors.
The new ASICs enable a more flexible set of interfaces for ports carrying 100Mbit to 100 Gbit/second Ethernet and 32 Gbit/s Fibre Channel traffic. The company claims the chips are the first to pack 36 100G ports in a system that fits in a single rack unit. The ASICs also implement flow control tables to monitor all traffic running across leaf and spine switches.
Cisco designed a family of three closely related ASICs for its systems with aggregate bandwidth ranging from 3.6 to 1.6 Terabits/second. Two of the chips, made in TSMC’s 16FF+ process, started shipping in systems in February, a third will ship within two months.
“We wanted the performance and cost advantages” of going to 16nm, Thomas Scheibe, senior director of product management for Cisco’s data center switch group told EE Times.
The process helps Cisco pack 20 to 40 MBytes of memory into the ASICs, eliminating the need for external memory. The cost of external memory “is significantly higher with lower reliability and higher power consumption” than embedded memory, said Scheibe.
Cisco, long one of the world’s largest ASIC designers, has its own approach for dynamically parsing the memory into shared or private buffers as needed. The memory serves the flow tables which are the largest new blocks in the ASICs. The tables help calculate average flow completion times, a key metric to avoid data collisions and get full use from its computer networks.
“Today no top-of-rack switch has a flow table for cost reasons and most chips can’t export the flow data fast enough,” said Scheibe.
The ASICs also let users select the data rates at which they want to run Ethernet and Fibre Channel traffic. They support SFP interfaces for 10G or 25G traffic and QSFP links for 40G or 100G links.
The ASICs are relatively large, about the same size as Cisco’s prior 28nm switch chips
Cisco is making two versions of its new switch systems. One uses Broadcom’s Tomahawk chips as a system fabric and line card switch; the other uses the new ASICs.
Tomi Engdahl says:
x86 SoC Series Spans Wide Application Range
http://www.eetimes.com/document.asp?doc_id=1329071&
At Embedded World last week chip maker Advanced Micro Devices (AMD) announced an expansion of its Embedded G-series systems on chip (SoCs) to span a range of applications from “top to bottom” in gaming, imaging, industrial control, and other common x86 applications. In addition to the release of an entry-level G-series line — the LX family — AMD has announced two new 3rd-generation G-series lines that offer pin compatibility with AMD’s higher-performing Embedded R-series SoCs. The result is an ability for designers to scale their software across broad performance, price, and power alternatives.
The LX family targets applications that need high performance with advanced multimedia and display capabilities at relatively low power. The chips contain two of AMD’s 64-bit “Jaguar” x86 cores, the Radeon Graphics Core Next (GCN), and a security processor along with error correcting memory.
The other two new families go a step further in performance
Tomi Engdahl says:
Is rigorous engineering support dead?
http://www.edn.com/design/systems-design/4441491/Is-rigorous-engineering-support-dead-?_mc=NL_EDN_EDT_EDN_today_20160302&cid=NL_EDN_EDT_EDN_today_20160302&elqTrackId=ed1ed804f1714eb0bd2ee7fc8942e64e&elq=ac839723036b4856b36e1de97c4385ca&elqaid=31129&elqat=1&elqCampaignId=27211
Information is good, and in the Internet era, plentiful too. However, what’s the standing of rigorous information?
I believe looking for rigorous technical support – trustworthy, guaranteed information – in electronics design is getting to be a challenge, too. You can no longer easily reach an individual in Analog Devices or Texas Instruments, or any similar behemoth, who can answer a technical question about their product or application note.
Instead, you are exhorted to join their forum, where you’re supposed to be optimistic that, because of the many like-minded engineers surrounding you, you’ll get a quick and rigorous answer to your question. Quick, perhaps yes. Rigorous? Or even Thoughtful like a Pooh Bear Even If Not Necessarily Rigorous? Hmm. Let me pen some anecdotes.
I believe both stories eventually reached some conclusion because I did not mark the questions as “answered,” but persisted in needling the employee-engineers for acceptable answers.
Back to that big question: Why we’re asked to rely on “official forums” to get answers to technical issues. Is there any sense of responsibility when these engineers respond? Do they realize that by “officially” responding on their company support forums, their shoot-from-the-hip answers are very likely to land their customers in dysfunctional design territory? Why is it so difficult to post a thoughtful response, as opposed to a get-it-off-my-chest response?
Above all, how does one know one has the right answer to a technical question?
Comment:
I strongly believe this is not a fault of engineers and other regular stuff in the companies. The real reason is our race for profit for any price. And it all start in top management pushing to produce more faster and cheaper. You can see this trend all around us in every day life anyway. Not only in industry. Hope it’s not too late.
Tomi Engdahl says:
IO-Link transceiver halves power dissipation
http://www.edn.com/electronics-products/other/4441527/IO-Link-transceiver-halves-power-dissipation?_mc=NL_EDN_EDT_EDN_analog_20160303&cid=NL_EDN_EDT_EDN_analog_20160303&elqTrackId=bed28a5f367f4d8193bc6be334114430&elq=70135d7b8dc2403186e848a6d071c2fc&elqaid=31143&elqat=1&elqCampaignId=27225
With typical driver on-resistance of 2.5 Ω, the MAX14827 IO-Link dual transceiver from Maxim saves more than 50% power dissipation. The tiny device integrates high-voltage functions commonly found in industrial sensors, including two ultralow-power drivers with active reverse-polarity protection and 3.3-V and 5-V linear regulators for low-noise analog/logic supply rails.
The transceiver offers both an SPI interface for sensors that use a microcontroller and a three-wire UART interface for IO-Link operation, which allows interfacing to the microcontroller UART. A multiplexed UART/SPI option allows using one serial microcontroller interface for shared SPI and UART interfaces.
Operation of the MAX14827 is specified for conventional 24-V supply voltages up to 60 V.
Tomi Engdahl says:
The new circuits over a bandwidth of 100 gigahertz
MODERN MEASURING INSTRUMENTS required a lot of performance. Tested signals are fast, bandwidth is growing all the time and analyysäi needs to be done in real time. Keysight Technologies, says that next year oscilloscope bandwidth is growing more than 100 gigahertz.
Progress is based on indiumfosfide based (InP) circuits, which Keysight is the sole manufacturer of the measuring device developed for six years. For example, today’s top model is InP chips reached 63 to 20 gigahertz channel.
Exact data is not yet Keysight upcoming devices or circuits are not told. One hundred gigahertz scopes on the market inputs necessary to wait at least until next year.
Source: http://etn.fi/index.php?option=com_content&view=article&id=4075:uusilla-piireilla-kaistanleveys-yli-100-gigahertsiin&catid=13&Itemid=101
Tomi Engdahl says:
Flash memory’s density surpasses hard drives for first time
http://www.computerworld.com/article/3030642/data-storage/flash-memorys-density-surpasses-hard-drives-for-first-time.html
HDD makers will roll out new tricks to increase areal density in the next two years
NAND flash memory has surpassed hard disk drive (HDD) technology in areal density for the first time, according to a new report from a market research firm.
During a presentation at the 2016 IEEE International Solid State Circuits Conference (ISSCC) in San Francisco last week, Micron shared data showing NAND flash has moved past HDDs in areal density, according to Coughlin Associates.
At last year’s ISSCC, Samsung white papers indicated that its 3D NAND flash products had reached 1.19Tbits per square inch (Tbpsi) and said in 2016 they would reach 1.69Tbpsi.
This year, Micron revealed it had demonstrated areal densities in its laboratories of up to 2.77Tbpsi for its 3D NAND. That compares with the densest HDDs of about 1.3Tbpsi. Tom Coughlin, Coughlin Associates president, noted the flash advancements in a column in Forbes.com last week.
The announced hard drive products from the third quarter of 2014 to the third quarter of 2015 had an increased areal density of about 60%, So HDDs have not stopped evolving,” Coughlin said.
“On the other hand, flash memory is getting denser with technology announcements of 2.77Tbspi, higher than any announced HDD areal density. This is a new development. So flash is developing and certainly getting competitive in terms of areal storage density, but the chips are still more expensive to make than disks and the raw costs of storage will likely remain less for HDDs for some time to come.”
Tomi Engdahl says:
The fourth age of emulation
http://www.edn.com/electronics-products/other/4441506/The-fourth-age-of-emulation?_mc=NL_EDN_EDT_EDN_today_20160303&cid=NL_EDN_EDT_EDN_today_20160303&elqTrackId=3b8d6fcaa6d843e7b2045ae1b12b29c9&elq=dbfa4215f1d04cbcac2e5d7095349c28&elqaid=31145&elqat=1&elqCampaignId=27227
Does Mentor’s claim of ushering in the fourth age of emulation seem reasonable? You tell me.
Mentor’s new Veloce OS3 boosts emulation performance by cutting compile time by 50%, and introduces three new modules, or Apps:
Deterministic ICE captures the complete behaviour of an ICE+target system run. Afterwards, multiple users can perform virtual runs at will, and the results will be deterministic – that is, not subject to the vagaries of varying target board behaviour.
Tomi Engdahl says:
The world’s fastest plastic circuit
Organic electronics is preferred to prepare, light and flexible, but its performance has been a major deficiencies. Now an English SmartKem is the production of plastic-based oscillator circuit, which is the world’s fastest. They can enable, for example, clearly more favorable to the current 4K displays.
Smart Kemi circuit the base of its own process and in materials. The Company appoints the technical name truFLEX. Now the process is made totally organic-5-stage ring oscillator, which switching frequency is above 500 kilohertz.
In addition, the phase delay of the component is less than 200 nanoseconds. Both readings are clearly superior to date readings organic components. Smart Kemi, the circuit optimization is also easy to get to frequencies of megahertz higher.
Organic electronics is – particularly because of lower production costs – for example, the demand for so-called. related to IoT devices and sensor nodes. So that they can take the form of RFID data rate of 53 Kbps, or NFC, the operating frequency of 13.6 MHz, the logic of the delay must be less than 400 nanoseconds. Smart Kemi This new prototype circuit reaches just fine.
Source: http://etn.fi/index.php?option=com_content&view=article&id=4076:maailman-nopein-muovipiiri&catid=13&Itemid=101
Tomi Engdahl says:
Emulation reveal faults more quickly and more comprehensively
Mentor Graphics has announced Veloce-emulaattor new applications and the operating system tuned machines. Marketing Director Jean-Marie Brunet, the emulation move to fourth in the same era. – The next time the applications and at the same time emulation is enhanced greatly, Brunet praised.
Mentor has announced three new Veloce-Apps, or applications. This is due, above all, the emulation development. – With hardware is no longer differ. rotating equipment applications and the operating system form a verification hub or platform in which the design risk is removed, Brunet designers.
Three new applications are called Veloce deterministic ICE, DFT and FastPath. Circuit emulation first makes a two-step process. First are the “traditional” circuit-level ICE emulation, in which the emulator is a physical connection to the right of the test device. In the second stage of tests run virtual host computer. As a result, the traditional ICE emulation can be run, ie divided by different sites.
Source: http://etn.fi/index.php?option=com_content&view=article&id=4065:emulointi-paljastaa-viat-yha-nopeammin-ja-kattavammin&catid=13&Itemid=101
Tomi Engdahl says:
Chip Sales Off to Slow Start to 2016
http://www.eetimes.com/document.asp?doc_id=1329100&
Semiconductor sales started sluggishly across the board in 2016, due largely to softening demand and lingering economic headwinds, according to the Semiconductor Industry Association (SIA) trade group.
Chip sales declined on both a sequential and annual basis across all regions except China, where sales increased compared with January 2015. It marked the third straight month that China was the only region to post year-to-year growth in chip sales.
Global chip sales totaled $26.9 billion in January, down 3% from the previous month and down 6% compared with January 2015, according to the sales numbers, compiled by the World Semiconductor Trade Statistics (WSTS) organization. The sales numbers for the month represent a three-month rolling average
Tomi Engdahl says:
E.U. Tackles III-V on CMOS
$47 million for 5G RF Solution
http://www.eetimes.com/document.asp?doc_id=1329101&
Integrating III-V transistor channels on standard complementary metal oxide semiconductors (CMOS) is the goal of a new three-year, $4.7 million program in the European Union (E.U.) called “Integration of III-V Nanowire Semiconductors for Next Generation High Performance CMOS SoC Technologies” (Insight). The ultimate aim is to meet the specifications of future 5G and radar systems aiming for wider bandwidth and higher-resolution images, respectively. Besides IBM (Switzerland), the program will be conducted by Fraunhofer IAF (Germany), LETI (France), Lund University (Sweden), University of Glasgow (UK) and the Tyndall National Institute (Ireland).
There will be two phases to the program led by IBM and Lund University, with IBM concentrating on prototyping conventional planar transistors with III-V channels, whereas Lund University will investigate the feasibility of vertical III-V transistor channels.
IBM predicts millimeter-wave RF performance at a much lower power consumption level than today, facilitating not just 5G but also cognitive computers, next-generation Internet of Thing (IoT) and the cloud-based platforms supporting them.
Tomi Engdahl says:
Intel outlines a plan to get back in line with Moore’s Law
Intel hopes to get back to advancing the chip manufacturing process every two years with the upcoming 7-nm process.
http://www.pcworld.com/article/3040381/computers/intel-eyes-a-path-to-get-back-in-line-with-moores-law.html
Intel prides itself on making computers faster, cheaper and smaller, but in recent years, the company lost a chip manufacturing edge it had to make that happen.
The company hasn’t kept up with its own deadlines to advance chip technology and has dealt with embarrassing product delays. In recent years, Intel hasn’t been able to advance the chip manufacturing process on a regular two-year cycle, a schedule it had in place for decades.
After encountering challenges involved in making teenier chips, Intel is now advancing the chip manufacturing process every two and a half years. It did so with its current 14-nanometer manufacturing process, and is expected to do so with its upcoming 10-nm process, Stacy Smith, chief financial officer, said during a speech this week at the Morgan Stanley Technology, Media and Telecom Conference.
But Intel hopes to end the half-year lapse at the upcoming 7-nm process, when it hopes to return to advancing chip manufacturing every two years, Smith said.
“We would like to be at two years, but we’re not,” Smith said. “We’re just watching 7-nm as being the potential time where there’s a technology shift that might allow us to get back to the two-year cadence.”
The first chips based on the 10-nanometer process, code-named Cannonlake, will come in the second half of 2017.
Returning to the Moore’s Law schedule hinges on a new technology called EUV (extreme ultraviolet lithography)
EUV could come into action with the 7-nm process. The technology uses ultraviolet light to transfer circuit patterns on silicon wafers using masks. EUV can’t be used now because the tools don’t exist.
Intel has floated the idea of using GaN (gallium nitride) to partly replace silicon on chips.
Tomi Engdahl says:
Intel gets a breakthrough in mobile phones
Intel has invested hundreds of millions, acquisitions, billions of dollars in order to get some kind of an important foothold in the smartphone processor supplier. Now, the American sources say that Intel delivers modem circuits for at least one third of the forthcoming new iPhone.
Information on the forthcoming iPhone device 7 are from Asian manufacturers. According to reports, this is Intel’s XMM 7360 -modeemipiiristä.
XMM circuit 7360 supports LTE terminal class 10
Source: http://etn.fi/index.php?option=com_content&view=article&id=4084:intelille-lapimurto-kannykoissa&catid=13&Itemid=101
Tomi Engdahl says:
Chip Makers Need New Business Models
http://www.eetimes.com/author.asp?section_id=36&doc_id=1329078&
The semiconductor industry needs to consider new business models based on open source hardware, re-programmable silicon and Features-as-a-Service to drive its next phase of growth.
After half a century of sustained expansion and innovation, semiconductor sales and profits are noticeably slowing amid shifts in consumer trends, market forces and the pace of innovation. The resulting slew of consolidations has left many wondering if the industry is losing its mojo.
Worldwide chip sales decreased by 1.9 percent during 2015 to $333.7 billion, according to Gartner, with the World Semiconductor Trade Statistics organization forecasting a slim 1.4 percent sales rebound in 2016 to $341 billion. Meanwhile, Morgan Stanley notes that chip-industry initial public offerings accounted for just 5% of all U.S. technology IPOs in 2015, compared with 25% a decade earlier.
Tomi Engdahl says:
ReRAMs: 3D Filaments and Brain-like Functions
http://www.eetimes.com/author.asp?section_id=36&doc_id=1329084&
University College London researchers are building on earlier work with ReRAMs based only on the sub-oxides of silicon to make the case for the suitability of their devices for use as emulators of brain-like neural functions.
ReRAMs based on the sub-oxides of silicon are attractive because SiO2 is already present in the fabrication process of the solid state circuits with which the ReRAMs will almost inevitably need to be integrated. More so if the two or more memory states can be achieved without needing to introduce and use the movement of foreign materials like silver and copper to build and remove the filaments.
Tomi Engdahl says:
ARM Has R&D Interest In Neural Network Cores
http://www.eetimes.com/author.asp?section_id=36&doc_id=1329087&
ARM has research interests in machine learning and neural networks but is not prepared to say there’s money to be made.
Intellectual property licensor ARM Holdings plc (Cambridge, England) has a research interest in machine learning and neural networks but is not yet prepared to say whether it can be turned into commercial business.
Tomi Engdahl says:
Neural Network Teaches itself to Count Cars
http://www.eetimes.com/document.asp?doc_id=1329096&
BrainChip Holdings Ltd. (Perth, Australia), the listed parent company of BrainChip Inc., has reported the development of an Autonomous Visual Feature Extraction system (AVFE) based on its spiking neural processor technology.
BrainChip’s neural network processor is known as SNAP and uses signal spikes as a means of data transfer and a method known as Spike Time Dependent Plasticity (STDP) for learning
Tomi Engdahl says:
Xilinx Invests in Neural Network Startup
http://www.eetimes.com/document.asp?doc_id=1329086&
FPGA vendor Xilinx has invested in TeraDeep Inc. (Santa Clara, Calif.) a developer of convolutional neural network architectures as part of a Data Center Ecosystem development program.
The program is aimed at emerging workload applications such as machine learning, image and video processing, data analytics, storage data base acceleration, and network acceleration. However, the size of the investment by Xilinx Technology Ventures was not disclosed.
Tomi Engdahl says:
Six Stats Driving Technical Marketing in 2016
http://www.eetimes.com/author.asp?section_id=36&doc_id=1328991&
1. The number one place engineers go to find work-related information is Google.
2. For information they deem valuable, over 80 percent of engineers say they will complete first name and last name lead form fields, and over 70 percent will complete lead form fields for work email address, company name, and job title. So for the naysayers out there who believe engineers won’t complete lead forms, I beg to differ. A critical phrase in this finding that can’t be overlooked is “For information they deem valuable….”
3. Engineers rank the highest trust in content written by engineering experts at vendor companies. Engineers want to hear from other engineers. It’s critical today to get the company SMEs (subject matter experts) sharing their knowledge.
4. Nearly 75 percent of engineers agreed or strongly agreed that they’re more likely to do business with a company that regularly produces new and current content. Engineers expect companies to provide content that informs, analyzes, explains, and persuade them throughout the buyer journey.
5. 94 percent and over 80 percent of engineers, respectively, said detailed diagrams and images as well as technical accuracy are important to content.
6. Over 75 percent of engineers said they are willing to go three pages or deeper in search before they find what they need or start their search over. While only 5 percent of engineers said they stop on page one
To summarize, engineers trust content from expert engineers at vendor companies, they go to Google to find it, and they will search deeply to find what they need. Engineers are also more willing to do business with companies who regularly produce new and current content, primarily white papers, case studies, webcasts, and videos.
Tomi Engdahl says:
Google Contest Builds More Efficient Inverters
http://hackaday.com/2016/03/06/google-contest-builds-more-efficient-inverters/
A few summers ago, Google and IEEE announced a one million dollar prize to build the most efficient and compact DC to AC inverter. It was called the Little Box Challenge, with the goal of a 2kW inverter with a power density greater than 50 Watts per cubic inch.
To put this goal into perspective, the DC inverter that would plug into a cigarette lighter in your car has a power density of about 1 or 2 Watts per cubic inch. Very expensive inverters meant for solar installations have a power density of about 5 Watts per cubic inch. This competition aimed to build an inverter with ten times the power density of what is available today.
Tomi Engdahl says:
The Versatile Performance Switching (VPX) standard, also known as VITA 46, defines Eurocard form factor systems supporting switched fabrics over a new high speed connector. Intended for embedded systems that meet the extremely harsh environments of military applications where size, weight, and power (SWaP) are critical
Tomi Engdahl says:
New generation of physical RTL synthesis improves QoR
http://www.edn.com/electronics-blogs/absolute-eda/4441580/New-generation-of-physical-RTL-synthesis-improves-QoR?_mc=NL_EDN_EDT_EDN_today_20160308&cid=NL_EDN_EDT_EDN_today_20160308&elqTrackId=ea73e22d1ebe41ffb209463221c6357c&elq=aba3f8bcd3764b75912aee5acaf428cf&elqaid=31210&elqat=1&elqCampaignId=27281
The quality of the netlist generated during RTL synthesis has an enormous impact on the rest of the physical design flow. For teams designing large SoCs at advanced nodes, it is more important than ever to come out of RTL synthesis with predictable timing and congestion estimates, DFT, and even a floorplan with good pin placements and feedthroughs. The quality of the netlist coming out of RTL synthesis has a big impact on the speed and predictability of the backend physical implementation and signoff.
What does quality of the netlist mean, and what are the bottlenecks of getting a good quality netlist for physical implementation? One barrier to better quality of results (QoR) from synthesis is when the synthesis tool optimizes the design after generating gates from the RTL. For the best quality, designers need a high-capacity, physically-aware logic synthesis tool that optimizes at a higher level of abstraction, not at the gate level. There are far more opportunities for QoR improvements when synthesis optimization is performed at the RTL level.
Tomi Engdahl says:
UltraScale Architecture
http://www.xilinx.com/products/technology/ultrascale.html
Xilinx’s new 16nm and 20nm UltraScale™ families are based on the first all programmable architecture to span multiple nodes from planar through FinFET technologies and beyond, while also scaling from monolithic through 3D ICs. At 20nm Xilinx pioneered the first ASIC-class All Programmable architecture to enable multi-hundred gigabit-per-second levels of system performance with smart processing at full line rates, scaling to terabits and teraflops. At 16nm, UltraScale+ families combine new memory, 3D-on-3D, and multi-processing SoC (MPSoC) technologies to deliver a generation ahead of value.
The new Xilinx UltraScale+ FPGA portfolio is comprised of the Kintex® UltraScale+ FPGA and Virtex® UltraScale+ FPGA and 3D IC families, while the Zynq® UltraScale+ family includes the industry’s first all programmable MPSoCs. Optimized at the system level, UltraScale+ devices deliver value far beyond a traditional process node migration – providing 2–5X greater system-level performance/watt over 28nm devices, far more systems integration and intelligence, and the highest level of security and safety.
Tomi Engdahl says:
Home> Tools & Learning> Products> Product Brief
The fourth age of emulation
http://www.edn.com/electronics-products/other/4441506/The-fourth-age-of-emulation?_mc=NL_EDN_EDT_EDN_productsandtools_20160307&cid=NL_EDN_EDT_EDN_productsandtools_20160307&elqTrackId=d7159e0c1f8c4458947889d82b41c567&elq=f53326b228c142a89c800956d5b949af&elqaid=31200&elqat=1&elqCampaignId=27272
Tomi Engdahl says:
Home> Tools & Learning> Products> Product Review
uModule regulator scales up to 300A and beyond
http://www.edn.com/electronics-products/electronic-product-reviews/other/4441521/uModule-regulator-scales-up-to-300A-and-beyond?_mc=NL_EDN_EDT_EDN_productsandtools_20160307&cid=NL_EDN_EDT_EDN_productsandtools_20160307&elqTrackId=b5454afd0a2a473f982ae932b0fa8b16&elq=f53326b228c142a89c800956d5b949af&elqaid=31200&elqat=1&elqCampaignId=27272
Designers can now take a 16×16mm 50A Point-of-load (POL) µModule power converter and scale it up to 386A thanks to the new LTM4650 (current sharing using seven of them) plus one LTM4677 (a 36A µModule which is the brain with digital telemetry.)
Linear Technology Corporation recently introduced the LTM4650, a dual 25A or single 50A output step-down µModule regulator with onboard shielded inductors, MOSFETs and a dual DC/DC regulator IC inside a small, thermally-enhanced plastic package.
12V in and 1V out @ 386A
Tomi Engdahl says:
Memory chips cut power in connected devices
http://www.edn.com/electronics-products/other/4441516/Memory-chips-cut-power-in-connected-devices?_mc=NL_EDN_EDT_EDN_productsandtools_20160307&cid=NL_EDN_EDT_EDN_productsandtools_20160307&elqTrackId=713df869fbd143669d4885c2e792c798&elq=f53326b228c142a89c800956d5b949af&elqaid=31200&elqat=1&elqCampaignId=27272
Adesto Technologies reports that its Moneta nonvolatile serial memories consume 50 to 100 times less power during read and write operations than comparable devices. Based on the company’s CBRAM (Conductive Bridging RAM) resistive technology, the parts reduce overall system energy use in connected devices, including Internet of Things, wearables, medical, and industrial products.
Moneta gives designers the flexibility to extend battery life and/or use smaller batteries to power their systems. Devices have an active read current of less than 10 µA at 500 kbps. Write current is 10 µA at 10 kbps. An automatic ultra-deep power-down mode reduces current consumption to just 35 nA.
Tomi Engdahl says:
Detecting Human Stress Using Sensors
http://www.eetimes.com/author.asp?section_id=36&doc_id=1329111&
Chip technology enables us to improve existing measurement and diagnostic methods for conditions such as cardiac and neuro disorders. It makes the equipment more compact, more economical and more comfortable, too.
We at imec and Holst Centre are confident that sensors can help to recognize habits and make adjustments to behavior. But it is certainly no easy task: not technologically, but also not because psychologists and behavioral scientists tend not to be very familiar with modern technology. As a result, there is still some skepticism about whether or not sensors are of any value in changing people’s patterns of behavior. We are currently working with some enthusiastic behaviorists from UZLeuven and KULeuven to investigate the usefulness of sensors for stress management.
Tomi Engdahl says:
Toshiba’s Sale of Medical Unit Could Fetch Billions
http://www.eetimes.com/document.asp?doc_id=1329089&
The medical device industry could be losing one of its giants. Struggling Toshiba, which had planned to sell part or all of its medical equipment business, now plans to simply sell the whole thing, according to Reuters, which cited people familiar with matter.
The Reuters sources thought that aggressive bidding could boost the sales price above the previous estimates equivalent to $3.5 billion. It is a cash infusion the Japanese giant sorely needs.
Tomi Engdahl says:
Broadcom Identifies $300M Cuts
Post Avago, many small divisions created
http://www.eetimes.com/document.asp?doc_id=1329099&
Hock Tan has made a lot of progress re-defining Broadcom Corp. in just a month since he acquired it for $37 billion in the semiconductor industry’s biggest deal to date. But the chief executive of the former Avago is not ready to provide details about what the new company looks like yet.
At a high level, Tan organized what is now Broadcom Ltd. into about 24 profit/loss divisions, considered the new company’s core businesses. Each has its own set of market and technology goals and a general manager reporting to him. He estimated they will report consolidated revenues of $3.55 billion in the April quarter, slightly below Wall Street estimates of $3.57 billion.
Tomi Engdahl says:
MRAM Breakthrough Looms
Fast, dense and cheap finally achieved
http://www.eetimes.com/document.asp?doc_id=1329112&
Everybody in the memory business is trying to build a nonvolatile memory that is as fast as static random access memory (SRAM), as dense as flash and as cheap as read-only-memory (ROM). The problems with this “universal” memory (that could replace all others) has already been solved by magnetic random assess memories—according to those making MRAM.
Unfortunately, the optimization step to actually make nonvolatile MRAM faster, denser and cheaper—that MRAM makers keep promising—always seems to be three years away. Now independent researchers at Eindhoven University of Technology (TU/e, The Netherlands) claim to have solved the fast, dense and cheap problem with a novel new approach called “field-free magnetization reversal by spin-Hall effect and exchange bias”—or “current bending” for short.
Tomi Engdahl says:
Home> Tools & Learning> Products> Product Brief
Power-stingy RF transceiver covers ISM band
http://www.edn.com/electronics-products/other/4441564/Power-stingy-RF-transceiver-covers-ISM-band?_mc=NL_EDN_EDT_EDN_today_20160307&cid=NL_EDN_EDT_EDN_today_20160307&elqTrackId=7558cdad65654deab479be3f8299980e&elq=3e84ffd54ab14e57a0fedaa09d8fc430&elqaid=31195&elqat=1&elqCampaignId=27267
perating over the unlicensed ISM frequency band between 779 MHz and 965 MHz, the ZL70550 RF transceiver from Microsemi boasts best-in-class low-power characteristics. The device consumes only 2.8 mA while transmitting at an output power of -10 dBm and a similar 2.5 mA during reception. Its sleep-state current of just 10 nA makes it well-suited for low-duty-cycle applications.
The ZL70550 can be used for wireless applications operating on coin-cell batteries or energy harvesters, such as electronic shelf labels, retail asset tracking, process control, wearable monitoring, and medical diagnostics. Working from a supply voltage of 1.7 V to 3.6 V, the ZL70550 offers variable output power and data rates of up to 200 kbps
Tomi Engdahl says:
US agency reaches ‘holy grail’ of battery storage sought by Elon Musk and Gates
http://www.theguardian.com/environment/2016/mar/03/us-agency-says-has-beaten-elon-musk-gates-to-holy-grail-battery-storage
Breakthrough in next generation of storage batteries could transform the US electrical grid within five to 10 years, says research agency, Arpa-E
Tomi Engdahl says:
Configurable Analog Chip Computes with 1,000 Times Less Power than Digital
http://www.news.gatech.edu/2016/03/02/configurable-analog-chip-computes-1000-times-less-power-digital
Researchers have built and demonstrated a novel configurable computing device that uses a thousand times less electrical power – and can be built up to a hundred times smaller – than comparable digital floating-gate configurable devices currently in use.
The new device, called the Field-Programmable Analog Array (FPAA) System-On-Chip (SoC), uses analog technology supported by digital components to achieve unprecedented power and size reductions. The researchers said that for many applications these low-power analog-based chips are likely to work as well as or better than configurable digital arrays.
Currently, field programmable gate arrays (FPGAs) – digital devices widely used in consumer devices, defense systems and more – dominate the configurable chip market. These floating-gate integrated circuits can be altered internally at any time, and techniques to reconfigure them for many different forms and functions are well established.
A paper on the new FPAA system-on-chip device has been published on the IEEE Xplore website.
The present FPAA device can operate on less than 30 milliwatts
To program the analog environment of the new device, researchers manipulate electrons in precise ways. Using electron-injection and electron-tunneling techniques
“Our FPAA chip has roughly half a million of these programmable parameters,” Hasler said. “They can be used as a switch in a digital manner – using the lowest possible value for ‘off’ or the highest possible value for ‘on’ – or we can achieve even more rich behavior using intermediate values.”