Here is my list of electronics industry trends and predictions for 2016:
There was a huge set of mega mergers in electronics industry announced in 2015. In 2016 we will see less mergers and how well the existing mergers went. Not all of the major acquisitions will succeed. Probably the the biggest challenge in these mega-mergers is “creating merging cultures or–better yet–creating new ones”.
Makers and open hardware will boost innovation in 2016. Open source has worked well in the software community, and it is coming more to hardware side. Maker culture encourages people be creators of technology rather than just consumers of it. A combination of the maker movement and robotics is preparing children for a future in which innovation and creativity will be more important than ever: robotics is an effective way for children as young as four years old to get experience in the STEM fields of science, technology, engineering, mathematics as well as programming and computer science. The maker movement is inspiring children to tinker-to-learn. Popular DIY electronics platforms include Arduino, Lego Mindstorms, Raspberry Pi, Phiro and LittleBits. Some of those DIY electronics platforms like Arduino and Raspberry Pi are finding their ways into commercial products for example in 3D printing, industrial automation and Internet of Things application fields.
Open source processors core gains more traction in 2016. RISC-V is on the march as an open source alternative to ARM and Mips. Fifteen sponsors, including a handful of high tech giants, are queuing up to be the first members of its new trade group for RISC-V. Currently RISC-V runs Linux and NetBSD, but not Android, Windows or any major embedded RTOSes. Support for other operating systems is expected in 2016. For other open source processor designs, take a look at OpenCores.org, the world’s largest site/community for development of hardware IP cores as open source.
GaN will be more widely used and talked about in 2016. Gallium nitride (GaN) is a binary III/V direct bandgap semiconductor commonly used in bright light-emitting diodes since the 1990s. It has special properties for applications in optoelectronic, high-power and high-frequency devices. You will see more GaN power electronics components because GaN – in comparison to the best silicon alternative – will enable higher power density through the ability to switch at high frequencies. You can get GaN devices for example from GaN Systems, Infineon, Macom, and Texas Instruments. The emergence of GaN as the next leap forward in power transistors gives new life to Moore’s Law in power.
Power electronics is becoming more digital and connected in 2016. Software-defined power brings to bear critical need in modern power systems. Digital Power was the beginning of software-defined power using a microcontroller or a DSP. Software-defined power takes this to another level. Connectivity is the key to success for software-defined power and the PMBus will enable the efficient communication and connection between all power devices in computer systems. It seems that power architectures to become software defined, which will take advantage of digital power adaptability and introduce software control to manage the power continuously as operating conditions change. For example adaptive voltage scaling (AVS) is supported by the AVSBus is contained in the newest PMBus standard V 1.3. The use of power-optimization software algorithms and the concept of the Software Defined Power Architecture (SDPA) are all being seen as part of a brave new future for advanced board-power management.
Nanowires and new forms of memory like RRAM (resistive random access memory) and spintronics are also being researched, and could help scale down chips. Many “exotic” memory technologies are in the lab, and some are even in shipping product: Ferroelectric RAM (FRAM), Resistive RAM (ReRAM), Magnetoresistive RAM (MRAM), Nano-RAM (NRAM).
Nanotube research has been ongoing since 1991, but there has been long road to get practical nanotube transistor. It seems that we almost have the necessary parts of the puzzle in 2016. In 2015 IBM reported a successful auto-alligment method for placing them across the source and drain. Texas Instruments is now capable of growing wafer scale graphene and the Chinese have taken the lead in developing both graphene and nanotubes according to Lux Research.
While nanotubes provide the fastest channel material available today, III-V materials like gallium arsenide (GaAs) and indium gallium arsenide (InGaAs) are all being explored by IBM, Intel, Imec and Samsung as transistor channels on silicon substrates. Dozen of researchers worldwide are experimenting with black phosphorus as an alternative to nanotubes and graphene for the next generation of semiconductors. Black phosphorus has the advantage of having a bandgap and works well alongside silicon photonics device. 3-Molybdenum disulphide MoS2 is also a contender for the next generation of semiconductors, due to its novel stacking properties.
Graphene has many fantastic properties and there has been new finding in it. I think it would be a good idea to follow development around magnetized graphene. Researchers make graphene magnetic, clearing the way for faster everything. I don’t expect practical products in 2016, but maybe something in next few years.
Optical communications is integrating deep into chips finally. There are many new contenders on the horizon for the true “next-generation” of optical communications with promising technologies in development in labs and research departments around the world. Silicon photonics is the study and application of photonic systems which use silicon as an optical medium. Silicon photonic devices can be made using existing semiconductor fabrication. Now we start to have technology to build optoelectronic microprocessors built using existing chip manufacturing. Engineers demo first processor that uses light for ultrafast communications. Optical communication could also potentially reduce chips’ power consumption on inter-chip-links and enable easily longer very fast links between ICs where needed. Two-dimensional (2D) transition metal dichalcogenides (TMDCs), which may enable engineers to exceed the properties of silicon in terms of energy efficiency and speed, moving researchers toward 2D on-chip optoelectronics for high-performance applications in optical communications and computing. To build practical systems with those ICs, we need to figure out how make easily fiber-to-chip coupling or how to manufacture practical optical printed circuit board (O-PCB).
Look development at self-directed assembly.Researchers from the National Institute of Standards and Technology (NIST) and IBM have discovered a trenching capability that could be harnessed for building devices through self-directed assembly. The capability could potentially be used to integrate lasers, sensors, wave guides and other optical components into so called “lab-on-a-chip” devices.
Smaller chip geometries are come to mainstream in 2016. Chip advancements and cost savings slowed down with the current 14-nanometer process, which is used to make its latest PC, server and mobile chips. Other manufacturers are catching to 14 nm and beyond. GlobalFoundries start producing a central processing chip as well as a graphics processing chip using 14nm technology. After a lapse, Intel looks to catch up with Moore’s Law again with with upcoming 10-nanometer and 7-nm processes. Samsung revealed that it will soon begin production of a 10nm FinFET node, and that the chip will be in full production by the end of 2016. This is expected to be at around the same time as rival TSMC. TSMC 10nm process will require triple patterning. For mass marker products it seems that 10nm node, is still at least a year away. Intel delayed plans for 10nm processors while TSMC is stepping on the gas, hoping to attract business from the likes of Apple. The first Intel 10-nm chips, code-named Cannonlake, will ship in 2017.
Looks like Moore’s Law has some life in it yet, though for IBM creating a 7nm chip required exotic techniques and materials. IBM Research showed in 2015 a 7nm chip will hold 20 billion transistors manufactured by perfecting EUV lithography and using silicon-germanium channels for its finned field-effect transistors (FinFETs). Also Intel revealed that the end of the road for Silicon is nearing as alternative materials will be required for the 7nm node and beyond. Scaling Silicon transistors down has become increasingly difficult and expensive and at around 7nm it will prove to be downright impossible. IBM development partner Samsung is in a race to catch up with Intel by 2018 when the first 7nm products are expected. Expect Silicon Alternatives Coming By 2020. One very promising short-term Silicon alternative is III-V semiconductor based on two compounds: Indium gallium arsenide ( InGaAs ) and indium phosphide (InP). Intel’s future mobile chips may have some components based on gallium nitride (GaN), which is also an exotic III-V material.
Silicon and traditional technologies continue to be still pushed forward in 2016 successfully. It seems that the extension of 193nm immersion to 7nm and beyond is possible, yet it would require octuple patterning and other steps that would increase production costs. IBM Research earlier this year beat Intel to the 7nm node by perfecting EUV lithography and using silicon-germanium channels for its finned field-effect transistors (FinFETs). Taiwan Semiconductor Manufacturing Co. (TSMC), the world’s largest foundry, said it has started work on a 5nm process to push ahead its most advanced technology. TSMC’s initial development work at 5nm may be yet another indication that EUV has been set back as an eventual replacement for immersion lithography.
It seems that 2016 could be the year for mass-adoption of 3D ICs and 3D memory. For over a decade, the terms 3D ICs and 3D memory have been used to refer to various technologies. 2016 could see some real advances and traction in the field as some truly 3D products are already shipping and more are promised to come soon. The most popular 3D category is that of 3D NAND flash memory: Samsung, Toshiba, Sandisk, Intel and Micron have all announced or started shipping flash that uses 3D silicon structure (we are currently seeing 128Gb-384Gb parts). Micron’s Hybrid Memory Cube (HMC) uses stacked DRAM die and through-silicon vias (TSVs) to create a high-bandwidth RAM subsystem with an abstracted interface (think DRAM with PCIe). Intel and Micron have announced production of a 3D crosspoint architecture high-endurance (1,000× NAND flash) nonvolatile memory.
The success of Apple’s portable computers, smartphones and tablets will lead to the fact that the company will buy as much as 25 per cent of world production of mobile DRAMs in 2016. In 2015 Apple bought 16.5 per cent of mobile DRAM.
After COP21 climate change summit reaches deal in Paris environmental compliance 2016 will become stronger business driver. Increasingly, electronics OEMs are realizing that environmental compliance goes beyond being a good corporate citizen. On the agenda for these businesses: climate change, water safety, waste management, and environmental compliance. Keep in mindenvironmental compliance requirements that include the Waste Electrical and Electronic Equipment (WEEE) directive, Restriction of Hazardous Substances Directive 2002/95/EC (RoHS 1), and Registration, Evaluation, Authorization and Restriction of Chemicals (REACH). It’s a legal situation: If you do not comply with regulatory aspects of business, you are out of business. Some companies are leading the parade toward environmental compliance or learning as they go.
Connectivity is proliferating everything from cars to homes, realigning diverse markets. It needs to be done easily for user, reliably, efficiently and securely.It is being reported that communications technologies are responsible for about 2-4% of all of carbon footprint generated by human activity. The needs for communications and faster speeds is increasing in this every day more and more connected world – penetration of smart devices there was a tremendous increase in the amount of mobile data traffic from 2010 to 2014.Wi-Fi has become so ubiquitous in homes in so many parts of the world that you can now really start tapping into that by having additional devices. When IoT is forecasted to be 50 billion connections by 2020, with the current technologies this would increase power consumption considerably. The coming explosion of the Internet of Things (IoT) will also need more efficient data centers that will be taxed to their limits.
The Internet of Things (IoT) is enabling increased automation on the factory floor and throughout the supply chain, 3D printing is changing how we think about making components, and the cloud and big data are enabling new applications that provide an end-to-end view from the factory floor to the retail store. With all of these technological options converging, it will be hard for CIOs, IT executives, and manufacturing leaders keep up. IoT will also be hard for R&D.Internet of Things (IoT) designs mesh together several design domains in order to successfully develop a product. Individually, these design domains are challenging. Bringing them all together to create an IoT product can place extreme pressure on design teams. It’s still pretty darn tedious to get all these things connected, and there’s all these standards battles coming on. The rise of the Internet of Things and Web services is driving new design principles as Web services from companies such as Amazon, Facebook and Uber are setting new standards for user experiences. Designers should think about building their products so they can learn more about their users and be flexible in creating new ways to satisfy them – but in such way that the user’s don’t feel that they are spied on what they do.
Subthreshold Transistors and MCUs will be hot in 2016 because Internet of Things will be hot in 2016 and it needs very low power chips. The technology is not new as cheap digital watches use FETs operating in the subthreshold region, but decades digital designers have ignored this operating region, because FETs are hard to characterize there. Now subthreshold has invaded the embedded space thanks to Ambiq’s new Apollo MCU. PsiKick Inc. has designed a proof-of-concept wireless sensor node system-chip using conventional EDA tools and a 130nm mixed-signal CMOS that operates with sub-threshold voltages and opening up the prospect of self-powering Internet of Things (IoT) systems. I expect also other sub-threshold designs to emerge. ARM Holdings plc (Cambridge, England) is also working at sub- and near-threshold operation of ICs. TSMC has developed a series of processes characterized down to near threshold voltages (ULP family for ultra low power are processes). Intel will focus on its IoT strategy and next-generation low voltage mobile processors.
FPGAs in various forms are coming to be more widely use use in 2016 in many applications. They are not no longer limited to high-end aerospace, defense, and high-end industrial applications. There are different ways people use FPGA. Barrier of entry to FPGA development have lowered so that even home makers can use easily FPGAs with cheap FPGA development boards, free tools and open IP cores. There was already lots of interest in 2015 for using FPGA for accelerating computations as the next step after GPU. Intel bought Altera in 2015 and plans in 2016 to begin selling products with a Xeon chip and an Altera FPGA in a single package – possibly available in early 2016. Examples of applications that would be well-suited for use of ARM-based FPGAs, including industrial robots, pumps for medical devices, electric motor controllers, imaging systems, and machine vision systems. Examples of ARM-based FPGAs are such as Xilinx’s Zynq-7000 and Altera’s Cyclone V intertwine. Some Internet of Things (IoT) application could start to test ARM-based field programmable gate array (FPGA) technology, enabling the hardware to be adaptable to market and consumer demands – software updates on such systems become hardware updates. Other potential benefits would be design re-use, code portability, and security.
The trend towards module consolidation is applicable in many industries as the complexity of communication, data rates, data exchanges and networks increases. Consolidating ECU in vehicles is has already been big trend for several years, but the concept in applicable to many markets including medical, industrial and aerospace.
It seems to be that AXIe nears the tipping point in 2016. AXIe is a modular instrument standard similar to PXI in many respects, but utilizing a larger board format that allows higher power instruments and greater rack density. It relies chiefly on the same PCI Express fabric for data communication as PXI. AXIe-1 is the uber high end modular standard and there is also compatible AXIe-0 that aims at being a low cost alternative. Popular measurement standard AXIe, IVI, LXI, PXI, and VXI have two things in common: They each manage standards for the test and measurement industry, and each of those standards is ruled by a private consortium. Why is this? Right or wrong, it comes down to speed of execution.
These days, a hardware emulator is a stylish, sleek box with fewer cables to manage. The “Big Three” EDA vendors offer hardware emulators in their product portfolios, each with a distinct architecture to give development teams more options. For some offerings emulation has become a datacenter resource through a transaction-based emulation mode or acceleration mode.
LED lighting is expected to become more intelligent, more beautiful, more affordable in 2016. Everyone agrees that the market for LED lighting will continue to enjoy dramatic year-on-year growth for at least the next few years. LED Lighting Market to Reach US$30.5 Billion in 2016 and Professional Lighting Markets to See Explosive Growth. Some companies will win on this growth, but there are also losers. Due currency fluctuations and price slide in 2015, end market demands in different countries have been much lower than expected, so smaller LED companies are facing financial loss pressures. The history of the solar industry to get a good sense of some of the challenges the LED industry will face. Next bankruptcy wave in the LED industry is possible. The LED incandescent replacement bulb market represents only a portion of a much larger market but, in many ways, it is the cutting edge of the industry, currently dealing with many of the challenges other market segments will have to face a few years from now. IoT features are coming to LED lighting, but it seem that one can only hope for interoperability
Other electronics trends articles to look:
Hot technologies: Looking ahead to 2016 (EDN)
CES Unveiled NY: What consumer electronics will 2016 bring?
Analysts Predict CES 2016 Trends
LEDinside: Top 10 LED Market Trends in 2016
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Tomi Engdahl says:
A Slow Penetration for RF CMOS
http://www.eetimes.com/author.asp?section_id=36&doc_id=1329132&
After 10 years of debate, where we are with RF CMOS?
I can’t speak for the Mobile World Congress, but at this year’s ISSCC there was very little to suggest any competition remains between RF CMOS and other fabrication technologies like Silicon Germanium (SiGe) or Gallium Arsenide (GaAs) in the construction of cellular radio ICs.
After 10 years of debate, where we are with RF CMOS? A clue is available from the recent (2014) introduction of an analog front end for mobile handsets: We’re just getting started. Qualcomm introduced what it called “the world’s first [emphasis added] multimode, multiband chip featuring an integrated CMOS power amplifier (PA) and antenna switch.” Qualcomm has been the world’s largest supplier of cell phone chip sets — baseband and applications processors — but, apart from power management controllers, has had a smaller impact on the analog front ends. A multi-chip module, Qualcomm’s QFE2320 includes a multi-mode multi-band power amplifier (MMMB PA), a radio transceiver, an envelope tracking power supply, and an integrated antenna switch.
The anatomy of a cellular radio front end
The analog front end is designed to relieve the clutter of components in handsets enabling to multiple 3G/4G and LTE encoding standards (such as GSM, GPRS, EDGE and WCDMA). It accomplishes this two ways: First, carrier signal aggregation reduces the number of radios required to decode a complex signal— integrating up to 5 carriers with up to 100 MHz of spectrum or 3 carriers with peak data rates up to 450 MBits/s ─ effectively increasing data rates by paralleling carrier channels. Secondly, a built-in antenna switch allows the front end match antenna and radio choices.
The integrated switches enable the Analog Front End to decode a variety of frequencies and transmission modes with a small number of power amplifiers. The integrated switches also decrease the footprint of the module e frequencies and transmission modes According to Qualcomm, the QFE2320 covers all major cellular modes (including LTE TDD/FDD, WCDMA/HSPA+, CDMA 1x, TD-SCDMA, and GSM/EDGE) and RF bands 700 to 2700 MHz. The analog front end already supports a number of commercial smartphones, particularly ZTE’s new flagship product, the Grand S II LTE.
What has happened in the past ten years is not a replacement of GaAs power amplifiers by RF CMOS amplifiers. The RF power amplifier function ― the launching of radio signals into the ether ― is performed at the edge of a radio transceiver chain. What happens in that chain is increasingly fabricated in RF CMOS. It is also a definitional issue: When marketers refer to an “all CMOS” radio, they’re typically overlooking the analog component.
A modern 4G phone will have to address multiple encoding schemes and frequency bands if it is to be truly useful worldwide. The architectural choices are basically two: You build multiple radios into the mobile handset, one for each modulation scheme you hope to decode. Or you build an integrated transceiver with multiple antenna drivers (ie, power amplifiers), and include an RF switch to bump between a single transceiver and multiple PAs).
Tomi Engdahl says:
Semiconductor Shipments to Top 1 Trillion Units in 2018
http://www.eetimes.com/document.asp?doc_id=1329127&
More than 1 trillion semiconductors are projected to ship in a calendar year for the first time in 2018, according to a forecast by market research firm IC Insights Inc.
The milestone achievement of about 1.02 trillion devices is expected to increase from 886.7 million units this year and about 950 billion units next year, according to the 2016 edition of IC Insights’ McClean Report. The total includes all semiconductors, including integrated circuits and opto-sensor-discrete (O-S-D) devices.
Topping the 1 trillion mark in 2018 would represent an impressive 9% compound annual growth rate over the past 40 years, from 32.8 billion shipments in 1978, according to IC Insights. The firm says the growth “demonstrates how increasingly dependent on semiconductors the world has become.”
Tomi Engdahl says:
Decoding Electronic Materials Genome
Initiative’s machine learning goes into public domain
http://www.eetimes.com/document.asp?doc_id=1329128&
Electronic materials do not actually have a genome—the complete set of genes for a particular organism—but as a metaphor the Materials Genome Initiative seeks to predict the properties of materials using quantum mechanics to simulate them on a computer. Using this method the University of Connecticut has now discovered the properties of organic electronics (polymers) with a machine learning algorithm that discovered the specific laws governing the dielectric breakdown of polymers thus accurately predicting their bandgap and dielectric constant from their atomic structure.
Tomi Engdahl says:
EUV 2.0 Decision Needed
Time to start the engineering, says mask expert
http://www.eetimes.com/document.asp?doc_id=1329033&
It’s time to come to consensus about the next generation of extreme ultraviolet lithography systems, even though first-generation EUV steppers have not yet entered production fabs. That’s the call to action issued this week from one veteran in the field.
“We need to nail down the next-gen EUV approach,” said Franklin Kalk, chief technology officer of Toppan Photomasks Inc. told EE Times. “There’s been a lot of talk about an anamorphic approach, not using today’s 4x reticle, but one that is 4x one way and 8x another way…if [that’s the best approach] the mask and OPC guys need to know that,” said Kalk who received a lifetime achievement award at this week’s SPIE Photomask Technology conference.
“The design studies I’ve seen for 4x by 8x look pretty good, I think it’s a good solution,” said Kalk. “There are all kinds of things people are talking about doing [for next-gen EUV]…but we need to seize on the next-gen concept so engineering work can start,” he added.
Tomi Engdahl says:
Solder at Room Temperature
http://hackaday.com/2016/03/09/solder-at-room-temperature/
Have you ever seen the science experiment (or magic trick?) where you get water supercooled to where it isn’t frozen, but then it freezes when you touch it, pour it, or otherwise disturb it? Apparently, ice crystals form around impurities or disturbances in the liquid and then “spread.” A similar effect can occur in metals where the molten metal cools in such a way that it stays melted even below the temperature that would usually cause it to melt.
[Martin Thuo] at Iowa University used this property to make solder joints at room temperature using Field’s metal (a combination of bismuth, indium, and tin). The key is a process that coats the molten metal with several nanolayers that protect it from solidifying until something disturbs the protective layer.
Researchers hope to create room-temperature soldering using this technique. The biggest problem so far is that Field’s metal will melt again at 62 degrees Celcius and that makes it impractical for many electronic circuits that can see temperatures higher than that.
Liquid metal ‘balloons’ offer room-temperature soldering
Invention could help the microelectronics industry to connect circuit-board components without risking heat damage.
http://www.nature.com/news/liquid-metal-balloons-offer-room-temperature-soldering-1.19495
Tomi Engdahl says:
Home> Community > Blogs > Out-of-this-World Design
Decoupling for rocket scientists, part 1
http://www.edn.com/electronics-blogs/out-of-this-world-design/4441601/Decoupling-for-rocket-scientists–part-1?_mc=NL_EDN_EDT_EDN_weekly_20160310&cid=NL_EDN_EDT_EDN_weekly_20160310&elqTrackId=04e8998d99d74963ba740de01ae97f8d&elq=d4745b1beaec485bbdb17376a6022bc3&elqaid=31253&elqat=1&elqCampaignId=27334
You are designing your latest sub-system and somebody tells you to place as many 100 nF decoupling capacitors as you can, as close as physically possible to all the integrated circuits, just like we did on our last satellite. As a design engineer, it’s only natural to question this qualitative approach to decoupling. What is its purpose? Why 100 nF? What about other values? How many capacitors? How close to the chip and in what orientation?
Did you know that in some instances you can remove many of the decoupling capacitors on your PCB without impacting the performance or the reliability of your sub-system? How do you optimise de-coupling, avoid over-engineering your design, reduce the BOM, and deliver less expensive and more reliable hardware, right-first-time?
Tomi Engdahl says:
Flexible Batteries, Electronics Expand
http://www.eetimes.com/document.asp?doc_id=1329133&
Today’s tiny market for thin-film batteries will grow to $470 million by 2026, according to a new report. The news comes as proponents of all sorts of flexible printed electronics are wrapping up an annual meeting that attracted a record 650 attendees, showing their latest work.
“The Internet of Things, wearables and environmental sensors…require new form factors and designs that traditional battery technologies simply cannot provide. This is why the likes of Apple, Samsung, LG, STMicroelectronics and TDK are all becoming increasingly involved,” said Xiaoxi He, a technology analyst at market watcher IDTechEx in a new report.
Samsung is using a curved battery in its Gear Fit wristband, and STMicroelectronics has started limited production of thin-film solid-state lithium batteries, the report said. It also noted two other companies starting production of printed batteries.
Tomi Engdahl says:
Temperature Sensors Improving, But Buyer Beware
http://www.eetimes.com/document.asp?doc_id=1329152&
From thermocouples and thermistors to resistance-temperature-detectors (RTDs), temperature sensors are varied and ubiquitous, but it would be wise not to take them for granted. Each type comes with its own set of inherent pros and cons in terms of cost, reliability, linearity, and ease of use. In this feature we will take you through some classics, while also updating you on the state of the art, how to make best of them, and a good example or two of temperature sensor and silicon integration.
Temperature sensors really are everywhere: used in automotive, infrastructure, industrial, military/aerospace, consumer electronics, medical, transportation, power, process control, petro-chemical, and geo-physical, agriculture, and communications applications. When used in combination with other sensors like strain and pressure sensors, they’re making the applications they serve more intelligent, safer, and more reliable. In many systems, temperature monitoring and control is fundamental.
Tomi Engdahl says:
Home> Community > Blogs > PowerSource
Google Little Box Challenge showcases GaN power element
http://www.edn.com/electronics-blogs/powersource/4441575/Google-Little-Box-Challenge-showcases-GaN-power-element?elqTrackId=56768b9a125a4191bd0e9151bf0e6dc9&elq=7c336a274dea493baade1f84853706b9&elqaid=31244&elqat=1&elqCampaignId=27325
GaN is overtaking silicon in the power element market for power management solutions as well as power management where high speed is needed. It is significant that GaN has emerged in the Google Little Box Challenge after rigorous testing of contestants’ creativity and engineering prowess. There has been much discussion regarding who the winner would be, and now the results have been announced, a team of designers from Belgium won and GaN Systems has revealed that their Gallium Nitride power transistors were instrumental in achieving the winning design. The Schneider Electric and the Virginia Tech Future Energy Electronics Center teams won honorable mentions.
This all started with Google teaming up with the IEEE Power Electronics Society. The rationale in creating this contest was particularly about challenging a significant improvement in power inverters which convert DC from renewable energy markets such as solar panels or batteries to AC for use in industry, our homes as well as automobiles.
Today’s inverters in homes are considered too large for homeowners, although they are typically only the size of a picnic cooler. If they were smaller, Google believes that more homes would entertain using them for solar-power, as well as brining electricity to remote areas of the world where energy does not now exist.
he grand prize of $1 Million prize was ultimately awarded to CE+T’s Red Electrical Devils from Belgium, for designing, building and demonstrating an inverter with the highest power density and smallest volume (GaN devices have been doing that more and more often in the power arena). The key goal of the challenge was to reach an inverter power density in excess of 50 W/cubic inch in a volume of under 40 cubic inches
https://www.littleboxchallenge.com/
Tomi Engdahl says:
EUV Lithography Makes Good Progress, Still Not Ready for Prime Time
by Anton Shilov on March 10, 2016 3:00 PM EST
http://www.anandtech.com/show/10097/euv-lithography-makes-good-progress-still-not-ready-for-prime-time
Tomi Engdahl says:
TSMC Details Silicon Road Map
FinFETs will fly from 16nm to 7nm
http://www.eetimes.com/document.asp?doc_id=1329217
Taiwan Semiconductor Manufacturing Co. Ltd. is ramping its 16nm process and making progress on plans to roll out 10 and 7nm nodes over the next two years. The news injected optimism in a crowd of about 1,500 attendees at a Silicon Valley event here where the world’s largest independent chip foundry shared its long-sought success with FinFETs and the great unknown beyond.
Some observers were underwhelmed, claiming TSMC’s road map to 7nm will only bring it in line with the 14nm process in which Intel is currently ramping its Skylake CPUs.
Indeed, even TSMC executives noted its 10 and 7nm nodes will have minimum feature sizes of about 20 and 14nm, respectively. And they all use the same fundamental FinFET transistor structures Intel pioneered at 22nm and 14nm. However, they also reported significant progress on research on post-FinFET devices
Tomi Engdahl says:
MEMS Grand Challenge Debuts
IoT contest fosters innovation
http://www.eetimes.com/document.asp?doc_id=1329203&
Simplfying and popularizing microelectromechanical system (MEMS) design is the goal of the MEMS Design Contest announced yesterday (March 16) at the conference titled Data Automation and Test in Europe (DATE 2016, March 15 to 17, Dresden, Germany). More specifically, the contest encourages chip designers to add MEMS blocks to a chip design, using tools designed for the purpose.
Sponsored by Cadence Design Systems, Coventor, X-FAB and Reutlingen University, the contest will feature a special process design kit (PDK) that the winners will use to fabricate their MEMS chip at X-Fab. If interested attend the DATE session Launch of the Worldwide MEMS Design Contest.
Tomi Engdahl says:
What’s behind Keysight’s 100 GHz announcement?
http://www.edn.com/electronics-blogs/rowe-s-and-columns/4441598/What-s-behind-Keysight-s-100-GHz-announcement-?_mc=NL_EDN_EDT_EDN_weekly_20160317&cid=NL_EDN_EDT_EDN_weekly_20160317&elqTrackId=c22f4d702c4c48d8907e208d416287eb&elq=da3b48b17cc84c3196f83af80ce6fb1c&elqaid=31381&elqat=1&elqCampaignId=27431
On March 1, 2016, Keysight Technologies announced that its engineers had developed InP (Indium Phosphide) technology that will result in oscilloscopes with real-time bandwidth of over 100 GHz. Such bandwidth, needed for today’s 56 Gbps data streams, would put Keysight on top of the bandwidth race. At the present time, Keysight is a close third to second-place Tektronix (70 GHz) while both still trail Teledyne LeCroy at 100 GHz.
EDN: Were there any breakthroughs that came about from the development of the InP process?
Asay: The biggest breakthrough was the speed of the indium phosphide. We’ve been developing InP for the last 5-6 years and now not only have speeds of over 100 GHz, but with 10-bit resolution.
EDN: When do you think you’ll have something to demonstrate?
Asay: Late this year.
EDN: I’d certainly like to see a demonstration at DesignCon 2017.
Asay: We expect to have something well before DesignCon, which is a showcase event for us.
EDN: What bandwidth do you expect to demonstrate at that time?
Asay: We expect to demonstrate 100+ GHz. That’s what’s needed now and we achieved that bandwidth easily. That’s why we issued a press release about the technology.
EDN: How do you test the technology?
Asay: That’s one of the bigger challenges because test equipment is kind of limited right now. We worked with other Keysight entities to get early access to the latest test equipment. That’s one advantage to being an overall test-and-measurement company. We can ask engineers to help us with test methodologies to stretch the limits.
EDN: You’ve always had the microwave people at hand.
Asay: We worked closely with the network analyzer people.
Tomi Engdahl says:
Bandwidth demand drives connector design
http://www.edn.com/design/test-and-measurement/4441553/Bandwidth-demand-drives-connector-design?_mc=NL_EDN_EDT_pcbdesigncenter_20160314&cid=NL_EDN_EDT_pcbdesigncenter_20160314&elqTrackId=abd9c37b433d4f0787045a7b475111c9&elq=cfca82403f4342618d5fb9e72744a018&elqaid=31287&elqat=1&elqCampaignId=27355
Meeting today’s bandwidth needs is often defined in terms of performance requirements and what can or can’t be achieved with current technology options. Many engineers are currently struggling to design 28 Gbps communications channels while others say they are well on their way to 32 Gbps. Some are now reaching for 56 Gbps and a few are looking into the technology to achieve 112 Gbps data rate.
Connectors form an important link in a signal’s transmission chain. Therefore, when designing high-speed systems, don’t overlook them. With the right parts, proper PCB materials, and proper design, you can meet the demand for high data rates.
Prior to today’s high speed design requirements, the issues of concern for interconnects were the physical aspects of their designs and factors that influenced those designs
As system speeds have increased, interconnect design is no longer based solely on mechanical requirements. Designers now have to take into account electrical performance issues such as insertion loss, return loss, crosstalk, skew, and propagation delay, to name a few. As with every aspect of high-speed product development, the successful design of any interconnect involves achieving the right balance between maximizing the physical and mechanical strength of the interconnect while optimizing SI (signal integrity). Interconnect design and manufacture has to be approached as part of the overall system level design process.
The essence of any interconnect design is the footprint, which is sometimes defined by mechanical considerations and other times by SI considerations
Laminate choice is another increasingly important factor in cable and connector design. While FR-4 isn’t the best laminate choice for high speed/high bandwidth designs, it’s still the preference of many product developers because of its low cost and broad availability.
As with all other elements of hardware, the pin geometry needs to be designed such that the focus is upon maintaining signal integrity by reducing crosstalk, coupling and reflections. That’s accomplished by controlling impedance and reducing loss.
Dielectric considerations are primarily a mechanical molding question that arises after the footprint is baked-out and the routing and construction of the connector comes into play.
Tomi Engdahl says:
Google Little Box Challenge showcases GaN power element
http://www.edn.com/electronics-blogs/powersource/4441575/Google-Little-Box-Challenge-showcases-GaN-power-element?_mc=NL_EDN_EDT_EDN_review_20160311&cid=NL_EDN_EDT_EDN_review_20160311&elqTrackId=34d3dbedb4464ad3878511e7fae7db85&elq=edb7f6f382274515a39af3649a9c4383&elqaid=31272&elqat=1&elqCampaignId=27344
GaN is overtaking silicon in the power element market for power management solutions as well as power management where high speed is needed. It is significant that GaN has emerged in the Google Little Box Challenge after rigorous testing of contestants’ creativity and engineering prowess. There has been much discussion regarding who the winner would be, and now the results have been announced, a team of designers from Belgium won and GaN Systems has revealed that their Gallium Nitride power transistors were instrumental in achieving the winning design. The Schneider Electric and the Virginia Tech Future Energy Electronics Center teams won honorable mentions.
https://www.littleboxchallenge.com/
Tomi Engdahl says:
Organic Chemistry Circuits are Flexible and Work Wet
http://hackaday.com/2016/03/21/organic-chemistry-circuits-are-flexible-and-work-wet/
As circuits find their way into more and more real-world environments, the old standard circuitry isn’t always up to the task. It wasn’t that long ago that a computer needed special power, cooling, and a large room. Now those computers wouldn’t cut it for the top-of-the-line smartphone. However, most modern circuits don’t bend well and don’t like getting wet.
An international team of researchers is developing chemical-based circuitry that uses gold nanoparticles and electrically charged organic molecules to build circuit elements that behave like semiconductor diode junctions. It’s simple to make flexible circuits that don’t mind being wet using this chemical soup.
Tomi Engdahl says:
Running Out Of Energy?
http://semiengineering.com/running-out-of-energy/
The anticipated and growing energy requirements for future computing needs will hit a wall in the next 24 years if the current trajectory is correct. At that point, the world will not produce enough energy for all of the devices that are expected to be drawing power.
A report issued by the Semiconductor Industry Association and Semiconductor Research Corp., bases its conclusions on system-level energy per bit operation, which are a combination of many components such as logic circuits, memory arrays, interfaces and I/Os. Each of those contributes to the total energy budget.
For the benchmark energy per bit, as shown in the chart below, computing will not be sustainable by 2040. This is when the energy required for computing is estimated to exceed the estimated world’s energy production. As such, significant improvement in the energy efficiency of computing is needed.
“It’s not realistic to expect that the world’s energy production is going to be devoted 100% to computing so the question is, how do we do more with less and where are the opportunities for squeezing more out of the system?”
“Anytime someone looks at a growth rate in a relatively young segment and extrapolates it decades into the future, you run into a problem that nothing can continue to grow at exponential rates forever,”
Case in point: Once upon a time gasoline cost 5 cents a gallon and cars were built that got 5 or 10 miles to the gallon. If it were extrapolated to say that if the whole world was driving as much as the Americans do in their cars at 5 miles to the gallon, we are going to run out of oil by 2020. But as time goes on, technology comes along that changes the usage patterns and cars are not built to get 5 miles to the gallon.
He noted that the core of the argument here is really a formula about the relationship between computing performance and energy, and it is primarily tracking the evolution of CPUs and capturing the correct observation that in order to go really really fast it takes more than linear increases in power and complexity.
“To push the envelope you have to do extraordinary things and the core assumption of the whole report is that you will continue on that same curve as you ramp up computing capability further still.”
And a key area of focus today is the interface between design and manufacturing where there is a constant need to keep focusing on how to contribute to getting more done with less power, and ultimately with less total energy consumed.
That also requires adapting to the new hardware architectures that bring more parallelism and more compute efficiency, and then working with very large distributed systems. Given the immense challenges of lowering the energy requirements of computing in the future, it is obvious the task will be accomplished with all hands on deck. And given the impressive accomplishments of the semiconductor industry in the past 50 years, there’s no doubt even more technological advancements will emerge to hold back the threat of hitting the energy wall.
Tomi Engdahl says:
Chip Market May Contract Again
http://www.eetimes.com/author.asp?section_id=36&doc_id=1329246&
At least one market watcher thinks the semiconductor industry will decline slightly for the second straight year for the second time in its history.
Tomi Engdahl says:
Home> Tools & Learning> Products> Product Brief
Mixer’s IF bandwidth spans DC to 6 GHz
http://www.edn.com/electronics-products/other/4441656/Mixer-s-IF-bandwidth-spans-DC-to-6-GHz?_mc=NL_EDN_EDT_EDN_productsandtools_20160321&cid=NL_EDN_EDT_EDN_productsandtools_20160321&elqTrackId=a8afa763724040a0a85da8cc1c1b5679&elq=472530118bc14cdc8e44f995520a67fb&elqaid=31410&elqat=1&elqCampaignId=27456
A double-balanced passive mixer, the LTC5548 from Linear Technology operates as an up or down converter over a frequency range of 2 GHz to 14 GHz. The device has integrated balun transformers at the RF and LO ports, providing 50-Ω match from 2 GHz to 13.6 GHz and from 1 GHz to 12 GHz at each port, respectively, while enabling single-ended operation. The IF port is also capable of DC to 6 GHz, which allows it to support wideband transmitters and receivers at the baseband.
http://www.linear.com/product/ltc5548
Tomi Engdahl says:
Dean Takahashi / VentureBeat:
Silicon Valley legend and former Intel CEO Andy Grove passes away at 79 — Intel has announced that the company’s former CEO and chairman, Andrew S. Grove, who was born in Hungary as András István Gróf, died today at age 79. — Grove was one of the key figures of the information age …
Silicon Valley legend and former Intel CEO Andy Grove passes away at 79
http://venturebeat.com/2016/03/21/silicon-valley-legend-and-former-intel-ceo-andy-grove-passes-away-at-79/
Intel has announced that the company’s former CEO and chairman, Andrew S. Grove, who was born in Hungary as András István Gróf, died today at age 79.
Grove was one of the key figures of the information age, and he was famous for his hard-charging management style, summed up as “only the paranoid survive.” He was present as a founding employee at Intel, alongside founders Robert Noyce, who died in 1990, and Gordon Moore, who still survives as Intel’s chairman emeritus. Not only did Grove play a key role in making Intel into the world’s biggest chip maker, he also set the pace for competing in what has become a $347 billion global industry.
Grove became Intel’s president in 1979 and took on the role of CEO in 1987. He served as chairman of the board from 1997 to 2005.
Tomi Engdahl says:
FPGA device density is continuing to grow at approximately 2x per node, which is driving more complex and larger FPGA designs. As the complexity grows, FPGA designers are under increasing pressure to accelerate designs and achieve a faster time to market.
At every phase, FPGA designers need sophisticated synthesis tools to help automate and accelerate the individual tasks
Source: https://webinar.techonline.com/1812?keycode=TOL4
Tomi Engdahl says:
Timing-aware pipelining optimization for area reduction
http://www.edn.com/design/integrated-circuit-design/4441689/Timing-aware-pipelining-optimization-for-area-reduction?_mc=NL_EDN_EDT_EDN_today_20160322&cid=NL_EDN_EDT_EDN_today_20160322&elqTrackId=0b4d6941e1a8494797cd027b2954abbd&elq=47083f7e60e143f682f6b9be2422beaf&elqaid=31429&elqat=1&elqCampaignId=27467
SoCs are optimized at the earliest stage possible in the design flow to avoid over-designing. Synthesis, being the first step for netlist generation, focuses on providing restructuring to accrue maximum design performance for the system, while taking care of factors like area and power. The EDA tool’s algorithms are written such that it will start working on the most timing critical paths in the respective cost groups, if any. During this process, it works on only the paths which are violating timing, and the paths with large positive slack are left unreported. There is a chance of getting design improvements when those paths are also analyzed.
Tomi Engdahl says:
Large-panel QFN leadframes reduce costs but bring assembly challenges
http://www.edn.com/design/integrated-circuit-design/4441647/Large-panel-QFN-leadframes-reduce-costs-but-bring-assembly-challenges?_mc=NL_EDN_EDT_EDN_today_20160321&cid=NL_EDN_EDT_EDN_today_20160321&elqTrackId=1267aa5506cc4afc92f963208e5d770f&elq=0ebc92fddf3c4504ad57968ac02bbb6e&elqaid=31405&elqat=1&elqCampaignId=27451
Today more than ever, cost reductions are being driven away from the traditional materials and bill of materials (BOM) reductions and into reductions in labor and manufacturing costs associated with building parts. Strip carriers, as shown in Figure 1 below, have been the long-standing format to attach semiconductors for volume processing in large quantities. Cost reductions push the industry towards larger strip formats in manufacturing for efficiencies at high-cost processes. This is also true for maximizing material potentials and labor at the processing steps. These larger strip sizes increase strip density and reduce labor and factory costs.
This article will cover handling risks, die attach challenges, wirebond, mold, singulation, and tape and reel challenges that are encountered as the strip size is increased and moved to a single block configuration to reduce costs in the manufacturing flow.
A number of industry leaders are actively engaged in cost reduction activities and wide leadframe conversions are part of this.
Tomi Engdahl says:
Concept of Superconducting Memory To Be Tested
Josephson Junctions over 100X faster, researchers claim
http://www.eetimes.com/document.asp?doc_id=1329256&
Russian scientists claim to have invented a new superconducting memory architecture that will be 100s of times faster and consume dozens of times less power than conventional memory chips. The Moscow Institute of Physics and Technology (MIPT, Russia) working with the Moscow State University (MSU, Russia) claim the architecture can also be used to perform single-flux quantum logic operations for superconducting processors, but admits that commercialization is decades away.
“What we have so far is an idea, a concept,”
“We expect its proof of principle experiment to be commenced in the near future.”
“This research as published shows great promise in the untapped potential of materials science to advance storage and computing designs,”
Tomi Engdahl says:
RF Energy Alliance
http://rfenergy.org/
The RF Energy Alliance is a non-profit technical association comprised of companies dedicated to realizing solid-state RF energy’s true potential as a clean, highly efficient and controllable heat and power source. Members share the vision of building a fast-growing, innovative marketplace around the sustainable technology, thereby contributing to quality of life across many application areas.
Tomi Engdahl says:
Ampleon and Midea collaboration results in world’s first solid state oven
http://www.ampleon.com/news/ampleon-and-midea-collaboration-results-in-world-s-first-solid-state-oven.html
Ampleon and Midea, a leading global consumer appliance manufacturer, today announced the results of a yearlong joint collaboration into the use of solid state technology for compact oven design. This initiative has resulted in Midea launching what is believed to be the world’s first commercially available solid state RF energy oven. By addressing the technical challenges associated with designing a small cavity appliance with a single antenna, Midea has created a 200 Watt table top oven that achieves homogeneous cooking. The oven can be powered either from a main power source or, for portable use, from a 24 VDC battery. Midea and Ampleon jointly developed the electronics and power amplifier stages while Midea focused on the overall product design.
Tomi Engdahl says:
Technology Breakthroughs Prepare to Change the World
http://mwrf.com/materials/technology-breakthroughs-prepare-change-world?code=UM_UM6DE
Expect 2016 to be a busy year, as plans are in motion to create technologies with capabilities that push past the boundaries of today’s state-of-the-art solutions.
When surveying the microwaves and RF landscape, it becomes apparent that 2016 could be a watershed year for high-impact technology developments. We’ve seen numerous advances in recent years, but many other possibilities still exist that could have a significant impact on every aspect of our everyday lives. As engineers, researchers, and scientists work hard to create tomorrow’s innovations, future technology seems poised to breakthrough on multiple fronts.
Most already know about the fuss concerning the Internet of Things (IoT), as it aims to provide connectivity to the very objects that we use daily. Some predict that we could see tens of billions of connected devices within the next several years. Another talking point is 5G, as future wireless networks could achieve performance levels that far exceed today’s capabilities. Expect a flurry of announcements to spin out through the year as development efforts continue regarding the IoT and 5G.
Although the IoT and 5G are receiving a large amount of attention, other new technologies loom on the horizon. One such example is RF cooking.
s gallium-nitride (GaN) technology finds its way into more applications, look for GaN-based products to continue to play a major role in 2016.
Tomi Engdahl says:
ESC Boston 2016: Test equipment preview
http://www.edn.com/design/test-and-measurement/4441619/ESC-Boston-2016-Test-equipment-preview?_mc=NL_EDN_EDT_EDN_today_20160323&cid=NL_EDN_EDT_EDN_today_20160323&elqTrackId=8121be82491048c2a61ae2e034335147&elq=3d0696c3a0f8418a965458b5a32d073d&elqaid=31449&elqat=1&elqCampaignId=27482
Tomi Engdahl says:
Home> Tools & Learning> Products> Product Brief
Press-fit reed sensor installs quickly
http://www.edn.com/electronics-products/other/4441677/Press-fit-reed-sensor-installs-quickly?_mc=NL_EDN_EDT_EDN_analog_20160324&cid=NL_EDN_EDT_EDN_analog_20160324&elqTrackId=85e5b17eada6488892885de49709b58c&elq=dd527950ae904cfc85b115663ddae6a6&elqaid=31470&elqat=1&elqCampaignId=27499
A Firecracker reed sensor with retaining ribs on the capsule, the 59040 from Littelfuse requires no attachment accessories for installation. The ribs on the cylindrical capsule compress when inserted into a 0.375-in. (9.5-mm) diameter hole, enabling a secure installation without the need for screws, brackets, or glue.
Magnetically operated, the 59040 series offers a choice three contact options: normally open, normally closed, and change-over. Switching capability is rated at up to 200 VDC/140 VAC at 10 W/VA.
Typical applications include position sensing in appliances, door and window position sensing in security systems, limit sensing in hydraulic cylinders, and speed and distance measuring/sensing in treadmills and bicycles.
59040 Series – Firecracker Reed Sensor with Retaining Ribs
http://www.littelfuse.com/products/magnetic-sensors-and-reed-switches/reed-sensors/59040.aspx
Tomi Engdahl says:
Multiprotocol transceiver saves board space
http://www.edn.com/electronics-products/other/4441678/Multiprotocol-transceiver-saves-board-space?_mc=NL_EDN_EDT_EDN_analog_20160324&cid=NL_EDN_EDT_EDN_analog_20160324&elqTrackId=4788bdb1b6c042b394cf25a57d6db922&elq=dd527950ae904cfc85b115663ddae6a6&elqaid=31470&elqat=1&elqCampaignId=27499
Housed in a small QFN package, the LTC2873 transceiver from Linear Technology handles RS-232, RS-85, and RS-422 communications, while operating from a single 3-V to 5.5-V supply.
Multiprotocol transceivers like the LTC2873 are used in single point-of-sale terminals, security cameras, traffic control, and industrial automation.
prices starting at $4.45 each
LTC2873 – Single-Bus RS485/RS232 Multiprotocol Transceiver with Switchable Termination
http://www.linear.com/product/ltc2873
One RS485 or One RS232 Transceiver
3V to 5.5V Supply Voltage
Up to 20Mbps RS485
High ESD: ±26kV HBM
1.7V to 5.5V Logic Interface
RS485 Receiver Failsafe Eliminates UART Lockup
Tomi Engdahl says:
Mixed-signal glue chip incorporates I2C & state machine
http://www.edn.com/electronics-products/other/4441694/Mixed-signal-glue-chip-incorporates-I2C—state-machine?_mc=NL_EDN_EDT_EDN_productsandtools_20160328&cid=NL_EDN_EDT_EDN_productsandtools_20160328&elqTrackId=9c2ca250e1ff4f24becb6210c279611d&elq=b5353fa240c7430680a3171fcfc500b4&elqaid=31512&elqat=1&elqCampaignId=27537
Silego Technology’s fifth generation of its GreenPAK (GPAK) programmable mixed-signal ICs, the SLG46531V GPAK 5, joins the company’s configurable mixed-signal ICs (CMICs), adding functions such as an asynchronous state machine, and I²C for on-the-fly reconfiguration.
This latest generation device, including Silego’s new Asynchronous State Machine and I²C blocks, adds flexibility, functionality, and ease of design to the NVM programmable GPAK family of devices. With the addition of the asynchronous (unclocked) state machine, designers can implement up to eight unique states with zero code, zero static power, and fail-safe operation. The addition of I²C enables designers to change device configuration, such as analogue comparator thresholds, on-the-fly. The I²C block can also act as a digital I/O expander.
In quantity, parts are 37¢ or less. A $59 devkit is also available.
GreenPAK 5 Programmable Mixed-signal Matrix
http://www.silego.com/products/greenpak5.html
GreenPAK 5 includes Silego’s new Asynchronous State Machine, I2C, and improved Counter/Delay blocks, introducing even more flexibility, functionality, and ease of design to the NVM programmable GreenPAK Mixed-signal Matrix.
GreenPAK 5 Development Kit
http://www.silego.com/buy/index.php?main_page=product_info&cPath=61&products_id=429
Tomi Engdahl says:
Microsemi Sells Board Level Systems Business
http://www.eetimes.com/document.asp?doc_id=1329284&
Microsemi Corp. said Thursday (March 24) it would sell part of its board level systems business to Mercury System Inc. for $300 million in cash.
Tomi Engdahl says:
VLSI Event Reflects Silicon Shifts
Intel to stretch out 14, 10nm process nodes
http://www.eetimes.com/document.asp?doc_id=1329291&
The semiconductor road map is shifting as advances in semiconductor technology become harder and market drivers become more diverse. That’s the message from this year’s VLSI Symposia, an annual gathering of top chip technologists that released its program this week.
More than 220 papers at the event will describe innovations to drive process technology to 10nm and beyond. Another 350 will describe circuits that squeeze power consumption for use in the Internet of Things, automotive electronics and big data analytics.
A panel of experts from companies such as Intel, IBM and Globalfoundries will discuss the implications of the slowdown in chip scaling in a session entitled “More Moore, More than Moore or Mo(o)re Slowly.” A separate panel will discuss “Semi Business beyond Scaling.”
“As we reach the limits of geometric scaling, we must add a critical functional scaling dimension to our technology innovation through 3D, embedded emerging memories [and] system-in-package,” said Raj Jammy, general chair of the Symposium on VLSI Technology, speaking in a press release.
Tomi Engdahl says:
Biometrics Market To Double Over 6 Years
http://www.eetimes.com/document.asp?doc_id=1329281&
The global market for biometrics technologies and applications will grow from about $13.7 billion in 2015 to more than $30 billion in 2021, according to market forecaster ABI Research.
The demand from within consumer electronics, particularly smartphones, will help drive this growth of 118 percent. Annual embedded fingerprint sensors are forecast to reach two billion by 2021 at compound annual growth rate over the period of 40 percent. That equates to shipments of about 266 million units in 2015 and of 372 million units in 2016.
Tomi Engdahl says:
GaN Gets Somber Reception at APEC 2016
Highlights from APEC 2016
http://www.eetimes.com/document.asp?doc_id=1329303&
Gallium Nitride (GaN) transistor deployments were surprisingly understated at this years’ APEC, held in Long Beach Calif. (March 20-24). For years now, GaN semiconductor developers had used the Applied Power Electronics Conference (APEC) to tout their fledgling product developments — or to denounce the technology as being too fragile, too expensive, too challenging, and just not real. One year, GaN product developments were characterized as “high school science fair projects,” a reaction to the proliferation of technical papers on developers’ web sites, and a then noticeable absence of actual data sheets.
Now, with the introduction of GaN transistors with various voltage and current ratings, package designs, and increasing distributor support, it seems we’ve gone over a hump in user acceptance. Manufacturers should have been popping champagne corks on the show floor (though a few were popped offsite). Instead, the mood on the floor was strangely subdued. There was a certain excitement from EPC’s Alex Lidow, who continues to find new applications for low-voltage GaN transistors, and who views the GaN revolution as a reincarnation of the MOSFET transistor revolution he triggered in the late ‘70s.
Navitas Semiconductor, in an APEC plenary speech, announced they had discovered the key to extracting the promised switching potential of GaN: Use aluminum on GaN (AlGaN) driver ICs for the GAN FETs — preferably on the same chip with GaN power transistors — and clock the resulting DC-DC converters at 40MHz. What a difference GaN would make for miniature power adapters, declared Tony Sagneri of FinSIX Corp. (another plenary speaker). GaN transistors could enable 65 watt tablet adapters with 680W-per-cubic-inch densities, and 96% efficiency, he said.
Infineon, which had acquired International Rectifier’s GaN business more than a year ago, answered written questions on their progress with GaN transistors
Transphorm, an early GaN pioneer, announced on-resistance reductions to its line of 650-volt transistors, but its marketing and development partner, ON Semiconductor, remained quiet
Panasonic was touting its own X-GAN transistors at the conference, and manufacturing
Almost unnoticed on the show floor, Texas Instruments announced they had developed a 600V GaN manufacturing process.
Navitas and EPC (Efficient Power Conversion) were in full proselytization mode. Both companies touted the higher switching speeds enabled by GaN and how this would reduce the size and costs of ancillary components like inductors and capacitors.
In Navitas experiments with Stanford University researchers, a 27MHz DC-to-AC converter in a 5mm x 6mm x 0.85mm QFN package [remember those dimensions] delivered 150 watts with 96% efficiency.
Perhaps the king of low-voltage is EPC, whose transistor line includes 40-, 100- and 200-V devices — eschewing the 650 industrial applications most competitors (including Silicon Carbide vendors) were chasing.
For example, the charging standard devised by the Air Fuel Alliance (formerly the alliance for wireless power, A4WP) uses resonant magnetics, operating at 6.78 MHz. The Air Fuel standard describes a number of power levels up to 50 watts. While the power pulse train can be initiated with legacy silicon (RF transistors, for example), the GaN devices operate with greater efficiency and far less heat disipation.
The ability to go from 48V DC to 5V (or 3.3V or lower) in one conversion step requires a high switching frequency — 1.5 MHZ or more — to effect a 95 or 96% efficiency. TI says its TPS53632G analog controller is optimized for GaN enables 48-to-1V conversion.
Despite the market shifts toward high-voltage industrial products, a large number of power management IC vendors continue to show solutions to server and data center power management problems.
Rohm contribution to the computing power arsenal is a synchronous bus regulator with SMBus and PMBus digital interfaces. The Rohm module, the PV9111, includes control logic, PWM, drivers and MOSFETs all in a 7mm x 7mm MLP package.
CUI promotes a “true power echo system” in which the power consumption of all cards in a rack can be carefully monitored and controlled. This allows data centers to consume more power from the existing architecture, Adams says. The visual interface allows monitoring of loads, utility power draws, battery charging, power allocation among cards in a rack, as well as the battery discharge profile.
The CUI machinery uses a CANbus interface ― rather than the PMBus ― to communicate power consumption of elements in a rack.
Tomi Engdahl says:
APEC 2016: Top 10 Must-Have Innovations for Power Designers
http://www.eetimes.com/document.asp?doc_id=1329294&
Tomi Engdahl says:
Foxxcon, Sharp Make a Deal. What Next?
http://www.eetimes.com/author.asp?section_id=36&doc_id=1329317&
The Sharp-Foxconn soap opera, playing out publicly since 2012, exposed an unusual level of raw emotion between the two companies.
The on-again and off-again attempt by Foxconn of Taiwan to take over Japan’s Sharp Corp. finally came to an end on Wednesday, March 30.
Foxconn agreed to pay about $3.5 billion for a two-thirds stake of Sharp, the two companies announced. Foxconn managed to slash the original offer by nearly $900 million, after a month-long negotiation.
To complicate matters further, Foxconn’s takeover of Sharp is billed as the largest acquisition by a foreign company in Japan’s insular technology sector. Imagine the cultural hurdles posed by this arranged marriage.
Sharp, in particular, is in deep financial trouble.
In the three quarters ending December 2015 Sharp’s consolidated operating earnings were a negative (loss) of 29 billion yen ($240 million), while “recurring profit” was a negative 52.8 billion yen ($440 million) and net income a negative 108 billion yen ($900 million).
Of course, there’s nothing new about Sharp’s troubled LCD operations. The Japanese company has struggled to fend off pricing pressure from its rivals in Asia. Two bank bailouts since 2012 did little to help turn things around. A slowdown in China’s smartphone market has hit Sharp’s sales in recent months.
Foxconn’s display empire
Foxconn has been buying up display business over last several years to build its own empire. An IHS Technology analyst pointed out that 50 percent of Sharp’s Gen 10 TFT LCD fab (manufacturing large LCDTV panels) is already owned by Foxconn. Foxconn also owns Taiwan-based Innolux, one of the largest TFT-LCD manufacturers in the world.
Foxconn has been also making aggressive investments in three new fabs developed to become Gen6 LTPS (Low Temperature Polysilicon ) TFT LCD fabs. All currently under construction
To help those new fabs ramp up quickly and make them truly competitive, Foxconn badly needs Sharp’s engineering resources and IPs.
Foxconn’s ambition in the display business extends to touch panels. A Foxconn subsidiary called General Interface Solution (GIS) Holding Limited is “a leading touch panel supplier and system integrator for mobile products from Apple and other companies,’ according to IHS.
Tomi Engdahl says:
Foxconn gains Sharp’s LCD technology and manufacturing capacity
http://www.edn.com/electronics-blogs/now-hear-this/4441745/Foxconn-gains-Sharp-s-LCD-technology-and-manufacturing-capacity?_mc=NL_EDN_EDT_EDN_today_20160330&cid=NL_EDN_EDT_EDN_today_20160330&elqTrackId=ad8726703e4e4d7e90106ec7cc83dec5&elq=29f33448b3fe490295eb34fb82c79c41&elqaid=31596&elqat=1&elqCampaignId=27569
Taiwan’s Foxconn Technology, the world’s largest electronics contract manufacturer, has reached the finish line in its on-again, off-again pursuit for control of Japan’s Sharp Corporation, one of Japan’s major electronics brands.
Foxconn, whose largest customer is Apple, will gain Sharp’s liquid crystal display (LCD) technology and manufacturing capacity, adding to its existing LCD holdings in Innolux Corporation, Taiwan’s largest flat-screen maker.
The Taiwanese company will take a 66 percent stake in Sharp through investments by its subsidiaries such as Hon Hai Precision Industry, Foxconn (Far East) Limited, and Foxconn Technology. The takeover will bring Foxconn a step closer to Chairman Terry Gou’s dream of creating a company with a brand name and manufacturing scale on a par with South Korea’s Samsung Electronics.
Tomi Engdahl says:
New slope compensation method stabilizes switchers
http://www.edn.com/design/power-management/4441719/New-slope-compensation-method-stabilizes-switchers?_mc=NL_EDN_EDT_EDN_weekly_20160331&cid=NL_EDN_EDT_EDN_weekly_20160331&elqTrackId=89f8a8cbf3ca4e58bfec618eaa6b6865&elq=52a83f9c6d8141269d1a81ef262a6cf2&elqaid=31615&elqat=1&elqCampaignId=27591
In switch-mode power converters, peak current control is very popular because of its inherent current limitation and ease of control. However, if the duty cycle is higher than 50%, there is an instability problem.
To remedy the problem, instead of comparing the peak current with a fixed value, we compare it with a ramp
there is a dramatic improvement: the stability is now as good as when the duty cycle is under 0.5.
However, too much slope compensation makes the converter behave more like a voltage mode converter than a current mode one. If the slope of the reference ramp is 50% of the current slope, we are at the limit of instability. Thus, a practical slope for the reference ramp is between 50% and 100% of the current ramp; 75% is a good choice. This method of adding the reference ramp is called “slope compensation”.
Tomi Engdahl says:
Swiss Open-Source Processor Core Ready For IoT
http://www.eetimes.com/document.asp?doc_id=1329327&
Researchers at ETH Zurich (Swiss Federal Institute of Technology in Zurich) and the University of Bologna have developed PULPino, an open-source processor optimized for low power consumption and application in wearables and the Internet of Things (IoT).
Open-source and collaborative development is now standard practise in the software world – Linux being an example. While there have been hardware efforts, such as OpenRISC and Opencores, open-source hardware has gained the most traction at the board level. Examples include Arduino and Raspberry Pi, for which the PCB designs are publicly available. However, the chips on which those boards are based have remained proprietary.
Now a team led by ETH Professor Luca Benini, has put into the public domain the full design of one of their microprocessor systems, a derivative of the PULP (Parallel ultra low power) project.
The 32-bit PULPino is designed for battery-powered devices with extremely low energy consumption. The arithmetic instructions are also open source: the scientists made the processor compatible with an open-source instruction set – RISC-V – developed at the University of California in Berkeley
PULPino is a simplified version of the more general PULP, in that it has a single processing element rather than a cluster of four processing elements and has simplified instruction and data RAMs and was implemented in FPGA in 2015.
According to presentation materials (downloadable from http://www.pulp-platform.org) the PULPino core is called RI5CY and is a four-stage in-order pipeline implementation of RISC-V.
The core which is compared to a Cortex-M4 from ARM, has an instructions per cycle figure close to 1, support for the base integer instruction set (RV32I), compressed instructions (RV32C) and partial support for the multiplication instruction set extension (RV32M).
The PULP quad-core IC was subject of a tape-out in 28nm from Globalfoundries in November 2015 while the first PULPino implementation (called Imperio) taped out in January 2016 in 65nm CMOS from UMC.
We are happy to share our FREE and OPEN-SOURCE microprocessor system PULPino!
http://www.pulp-platform.org/
You can download the entire source code, test programs, programming environment and even the bitstream for the popular ZEDboard, completely for free under the Solderpad license.
Tomi Engdahl says:
EDA Group Broadens Mission
http://www.eetimes.com/document.asp?doc_id=1329323&
The EDA Consortium, founded in 1989, has renamed itself the Electronic System Design (ESD) Alliance and expended its mission to include semiconductor intellectual property, embedded software and advanced chip packaging. As part of its new charter it is forming initiatives in all three areas.
By reaching beyond in its traditional focus on the $15-20 billion market for design automation software, the group aims to expand beyond its current membership of 40 companies.
“I’d like to at least double membership,”
An initiative on embedded software is still in gestation. “My gut level is it should be working on software that touches the hardware — the true embedded stuff that’s in the chip or closely connected to it,” said Smith. “There are tons of providers here, but it’s a Wild West, he said.
Tomi Engdahl says:
Intel flops out four 3D flash SSDs – and says they’re the densest ever
SSD chip fashionistas adopt the layering system
http://www.theregister.co.uk/2016/03/31/intels_quad_3d_nand_ssd_splurge/
Intel has introduced its first 3D NAND SSDs, updating three planar NVMe SSDs with four new models, and claiming to have the industry’s highest density 3D NAND.
The existing DC P3500, P3600 and P3700 products used 20nm MLC flash technology, with the P3500 and P3600 dating from June 2014 and the P3700 being introduced in September last year along with a P3608 (two P3600s in one SSD package).
Tomi Engdahl says:
Alison Griswold / Quartz:
Zero tech companies went public in the US in Q1 2016, which hasn’t happened since Q1 2009 during the recession — Zero tech companies went public in the US in Q1 2016, which hasn’t happened since Q1 2009 — The US market for tech IPOs has totally frozen over.
The market for tech IPOs hasn’t been this awful since the Great Recession
http://qz.com/652261/the-market-for-tech-ipos-hasnt-been-this-awful-since-the-great-recession/
The US market for tech IPOs has totally frozen over.
Zero Internet or tech companies went public on US exchanges in the first quarter of 2016. The last time that happened was in the first quarter of 2009, during the depths of the Great Recession, according to data from Dealogic.
Just two years ago, the picture looked quite different.
Startups began steering clear of IPOs last year, even as many of them continued to raise money at tremendous valuations. The billion-dollar startup club has grown to include more than 140 members, of which nearly 90 are based in the US. Uber is the biggest, with its $62.5 billion valuation, followed by Chinese electronics company Xiaomi ($46 billion) and Airbnb ($25.5 billion).
But lately a chill has also settled over financing in Silicon Valley. Startup funding fell 30% in the fourth quarter of 2015 from the one prior, to $27.7 billion.
Tomi Engdahl says:
Arik Hesseldahl / Re/code:
Shake-up at Intel as Kirk Skaugen, head of PC business, and Doug Davis, head of IoT effort, depart
Shake-up at Intel as veteran execs Davis and Skaugen leave
http://recode.net/2016/04/04/intel-doug-davis-kirk-skaugen-depart/
Chipmaker Intel just announced the departure plans of two longtime executives, one heading up its business devoted to personal computers, another heading up its Internet of Things efforts.
Kirk Skaugen, Intel’s senior VP in its Client Computing Group (Intel refers to PCs as clients), is leaving the company for a new job elsewhere, according to an internal memo released today.
Doug Davis, the general manager of the Internet of Things unit, is also leaving after 32 years with the chip giant.
Tomi Engdahl says:
Intel Mobile Chip Leader Is Leaving After Less Than a Year in That Role
http://www.bloomberg.com/news/articles/2016-04-01/intel-mobile-chip-leader-aicha-evans-said-to-be-leaving-company
Intel Corp. executive Aicha Evans is leaving the company less than a year into her tenure as head of the semiconductor maker’s struggling mobile phone division.
Evans, who joined the company a decade ago, has handed in her notice at Intel, according to people familiar with the matter who asked not to be identified because the move hasn’t been made public
Intel, the largest chipmaker because of its hold on personal computer and server markets, has spent billions of dollars and more than a decade trying to get into phones. It ended 2015 with a 1 percent share in phone processors
Evans’s departure comes amid speculation her unit is close to a rare mobile breakthrough by becoming a supplier of parts for Apple Inc.’s iPhone.
Tomi Engdahl says:
Programmable DC load returns its wasted energy to the AC source at APEC 2016
http://www.edn.com/electronics-products/electronic-product-reviews/other/4441751/Programmable-DC-load-returns-its-wasted-energy-to-the-AC-source-at-APEC-2016?_mc=NL_EDN_EDT_EDN_today_20160404&cid=NL_EDN_EDT_EDN_today_20160404&elqTrackId=f11481d4ac714c4e80b96107e1447d87&elq=9a860056ca2e4542879b0dd30da5e5e1&elqaid=31651&elqat=1&elqCampaignId=27635
Electric vehicles take advantage of the wasted heat from their braking systems to charge the battery or power ever-increasing amounts of new electronics on board, increasing the efficiency of such a power system. I really appreciate it when a good design also respects power efficiency. This is why I am highlighting Intepro’s line of DC loads.
At Apec 2016 I met with Andrew Engler, Marketing Coordinator for Intepro Systems and Eric Turner, Western Regional Sales Manager who demonstrated their rack-mounted ELR9000 series with output ratings of 3.5 kW, 7 kW and 10.5 kW — scalable to 105 kW.
This system returns up to 95% of the load power to the AC source and is especially important for rental companies and others that need to ship devices from one location to another because these units are much smaller than most systems like this and need no costly crating for transport.
The programmable load uses an integral, grid-synchronized inverter that returns up load test energy back to the grid. Recovering the load energy dramatically reduces energy costs for the user. It also provides a cost-effective alternative to expensive cooling systems used in conventional air- and water-cooled loads to dissipate energy as heat.
These electronic DC loads provide the four most common regulation modes: Constant Voltage (CV), Constant Current (CC), Constant Power (CP) and Constant Resistance (CR).
Tomi Engdahl says:
FinFET’s Father Forecasts Future
Meet the negative-capacitance FET
http://www.eetimes.com/document.asp?doc_id=1329333&
Don’t worry about the end of Moore’s law, there are plenty of good ideas on the semiconductor road map, according to Chenming Hu, a university researcher credited as being the father of the FinFET.
Hu described new transistor concepts that could fuel the chip industry for decades in a talk at the annual Synopsys Users Group
“We all know but don’t like to say out loud that transistor size reduction is a game that has an end and we are racing to that end,” but that doesn’t mean the end of the semiconductor industry and the high tech sector build on top of it, Hu said.
The negative-capacitance transistor (NC-FET) is one of the latest and most significant concepts to emerge from labs at the University of California at Berkeley where Hu is a professor. Hu and colleagues showed work on a 30nm NC-FET made in hafnium zircon dioxide and using a novel 5nm ferroelectric layer.
“Essentially it puts a voltage amplifier into the dielectric…the idea is you get the same performance at lower Vdd,” Hu explained.
The design could help engineers reduce Vdd to levels below 0.3 V, overcoming limits that could pave the way to decades of new devices.
Recently, Berkeley set up a new center to focus on the NC-FET. Intel and TSMC joined, paying $140,000 each
Tomi Engdahl says:
Latest HyperLynx Release Targets Extreme PCB Designs
http://www.eetimes.com/document.asp?doc_id=1329348&
The hot news in PCB space today is the latest release of HyperLynx from the folks at Mentor. Now, just to set the scene and make sure we’re all dancing to the same drum beat, let’s place HyperLynx in the context of the overall PCB design, verification, and manufacturing flow
In these days of extreme design complexity, we’re seeing more and more boards with thousands of components, tens of thousands of connections, and enough voltage rails to make your eyes water.
We’re also seeing shifting high-speed design challenges, including memory interfaces being in transition (DDR3 to DDR4 to Hybrid Memory Cube (HMC) technology); large numbers of lower voltages coupled with higher currents and reduced layers/planes giving a “Swiss cheese” effect that impacts return paths; and fast, multi-lane structures, multi-level signaling (PAM-4), and channel operating margin (COM).
In order to address designs of this caliber, the new release of HyperLynx integrates signal and power integrity; 2D, 2.5D, and 3D solvers; and fast rule checking into a unified environment. Analyzing all of this could potentially be a processing nightmare, not the least that it is no longer possible to work on a subset of the design in isolation; instead, the entire board (including component package internals) has to be analyzed at the same time.
Tomi Engdahl says:
Intel Plans A Future of CMOS
Moore’s Law extended by new materials
http://www.eetimes.com/document.asp?doc_id=1329353&
Intel’s future processors at 10-nanometer and beyond will continue to use CMOS for cores, but the cores will be surrounded by novel circuit architectures using new materials that may extend Moore’s Law indefinitely.
“Moore’s Law was never about scaling, but about the economic benefits of putting more die on wafers,”
“Intel is adding new circuitry, such as adaptive voltage control that increases yields over using fixed voltages, by making its analog circuits digital or at lease digitally assisted, and by exploring new materials for specific functions around the scaled CMOS cores.”
“You need bigger and bigger SRAM caches on processor chips, despite they aging design, because DRAM has not been about to keep up with processor performance,” said Zhang. “You can mitigate the problems with SRAM with 3D, but the best way is merely to improve the size and performance of planar on-chip SRAM memory caches.”
For the last 20 years, the venerable SRAM has essentially remained unchanged, with only minor improvements. However, going forward to the 14-nanometer node and beyond, Intel has been tinkering with the design of SRAM cells to allow them to continue scaling.
“No longer is progress just about scaling, but for last few years it has ben about introducing new transistor architectures and new materials,” said Zhang, including high-k dielectrics, metal gates and 3-D FinFET transistor architectures.
The power to the SRAM arrays, when idle, is also being cured, so that 99 percent of the array can be kept in sleep mode
For instance, analog voltage controlled oscillators (VCOs) have been converted to Digital Voltage Controlled Oscillators (DCO), analog transistors for bipolar junction transistors (BJTs) for thermal runaway sensing, along with all the other analog functions inside the typical analog phase-locked-loop (PLL) that looks in processor frequencies.
Future is adaptive design
The future of continued scaling is dependent on adaptive power management and voltage scaling, according to Zhang, which is needed to manage power with voltage scaling downward especially during sleep periods, but still with enough voltage to keep SRAM alive. Using a variable bias—instead of fixed—next-generation transistors an be dynamically tuned using adaptive control biases that depending on the unique character of each chips’s transistor so on each die produced.
Beyond CMOS
For the future, Zhang believes that the CMOS cores, improved with the adaptive methods above, will remain the heart of future processors beyond 10-nanometer. However, he also predicts that a potpourri of new materials, such as gallium nitride, magnetic materials, III-V materials, Qubits and more will serve as peripheral support technologies to its adaptive CMOS cores.
“Innovations continue to be the driving force into our future processors with CMOS remaining at is core,”
Tomi Engdahl says:
Home> Community > Blogs > Anablog
IC packages and thermal design
http://www.edn.com/electronics-blogs/anablog/4441750/IC-packages-and-thermal-design?_mc=NL_EDN_EDT_EDN_today_20160404&cid=NL_EDN_EDT_EDN_today_20160404&elqTrackId=919c01c01c39452aaa1f97a246cc1616&elq=9a860056ca2e4542879b0dd30da5e5e1&elqaid=31651&elqat=1&elqCampaignId=27635