Agam Shah / PCWorld:
SiFive, creators of open RISC-V architecture, announce $8.5M Series B led by Spark Capital as company unveils two new chip designs
In their quest to democratize access to custom silicon, SiFive has announced the very first RISC-V-based Arduino just hours before the start of Maker Faire Bay Area 2017.
Inventors of RISC-V Unveil U54-MC Coreplex IP, a 64-Bit Multicore CPU Designed for Embedded Applications that Require a Full Operating System.
SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced the availability of U54-MC Coreplex IP, the industry’s first RISC-V based, 64-bit, quadcore real-time capable application processor with support for full featured operating systems such as Linux.
“The ability for RISC-V developers to develop Linux and other Unix-based operating systems on commercial grade silicon will enable the RISC-V software ecosystem to quickly expand beyond embedded systems, and bring new solutions to market. We look forward to seeing the various markets that are now addressable with SiFive’s U54-MC Coreplex IP.”
Athe the Linley Processor Conference today, SiFive, the semiconductor company building chips around the Open RISC-V instruction set has announced the availability of a quadcore processor that runs Linux. We’ve seen RISC-V implementations before, and SiFive has already released silicon-based on the RISC-V ISA. These implementations are rather small, though, and this is the first implementation designed for more than simple embedded devices.
This announcement introduces the SiFive U54-MC Coreplex, a true System on Chip that includes four 64-bit CPUs running at 1.5 GHz. This SoC is built with TSMC’s 28 nm process, and fits on a die about 30 mm². Availability will be on a development board sometime in early 2018, and if our expectations match the reality of SiFive’s previous offerings, you’ll be able to buy this Open SoC as a BGA package some months after that.
So far, there are few tangible details about the SiFive U54-MC, but what we do know looks great. On the software support front, RISC-V support in GCC is stable and mainlined as of the 7.1 release. LLVM is in the process of being submitted, and Linux support is getting there too. Considering no one outside SiFive has this hardware in hand, this is just fine.
U54-MC Coreplex IP is the world’s first RISC-V based 64-bit quad-core application processor, supporting full-featured operating systems such as Linux. The U54-MC Coreplex’s high-performance and flexible memory system makes it ideal for applications such as AI, machine learning, networking, gateways, and smart IoT devices.
SiFive has taped out and started licensing its U54-MC Coreplex, its first RISC-V IP designed to run Linux. The design lags the performance of a comparable ARM Cortex-A53 but shows progress creating a commercial market for the open-source instruction set architecture.
A single 64-bit U54 core delivers 1.7 DMIPS/MHz or 2.75 CoreMark/MHz at 1.5 GHz. It measures 0.234 mm2 including its integrated 32+32KB L1 cache in a TSMC 28HPC process using a 12-track library.
A quad-core complex with a 2-MByte shared coherent L2 cache, Gbit Ethernet and DDR3/4 controllers and other peripherals measures ~30 mm2. SiFive will deliver a quad-core chip that includes an E51 management core that will ship in the first quarter on boards targeting software developers.
The single-issue, in-order U54 is expected to lag the performance of ARM’s dual-issue A53. By comparison, in late 2014 Freescale (now NXP) announced the QorIQ LS1043A, a midrange quad-core A53 running at 1.5 GHz delivering more than 16,000 CoreMarks at 6 W.
SiFive believes its part will be competitive in power and area efficiency. It also aims to innovate in its business model.
The startup will offer designers 100 prototype SoCs for $100,000 with no fees on third-party IP bundled with its cores until customers ship their chips. “Today, you pay all the IP costs upfront — we think that’s the wrong way,” said Jack Kang, vice president of business development for SiFive.
It’s still early days for RISC-V vendors and users.
Microsemi and Arduino are SiFive’s only announced customers. The startup claims that it already has multiple licensees of the U54, including military contractors and large semiconductor companies that serve markets including set-top boxes and data center accelerators.
SiFive launched U54-MC Coreplex IP, a RISC-V based, 64-bit, quadcore real-time capable application processor with support for full featured operating systems such as Linux. The cores utilize a five-stage in-order pipeline, support the RV64GC ISA and cache coherence. It is targeted at AI, machine learning, networking, gateways and smart IoT devices.
SiFive has joined GlobalFoundries’ FDXcelerator Partner Program. SiFive will be making its RISC-V CPU IPs—such as the E31 and E51 RISC-V cores– available on GF’s 22nm FD-SOI process technology. Based on the open source RISC-V ISA, the E31 offers embedded chip designers new capabilities in high performance within strict area and power requirements. The E51 offers 64-bit performance at 32-bit price, power and area.
SiFive announced today that it has joined GLOBALFOUNDRIES’ FDXcelerator™ Partner Program, and will be making RISC-V CPU IP including SiFive’s E31 and E51 RISC-V cores available on GF’s 22FDX® process technology. Based on the open source RISC-V ISA, the SiFive E31 offers embedded chip designers new capabilities in high performance within strict area and power requirements, and the SiFive E51 offers a full 64-bit performance at 32-bit price, power and area.
“As the RISC-V ecosystem continues to grow, SiFive’s leading CPU IP is seeing increased adoption. Our partnership with GF is going to enable an even larger pool of system designers to build on an industry-leading process platform,” said Naveed Sherwani, CEO, SiFive. “SiFive has led the RISC-V ecosystem from early on and we are excited to continue extending RISC-V into new market segments.”
Imperas debuted its RISC-V Processor Developer Suite, a set of models, a software simulator, and tools to validate, verify, and provide early estimation of timing performance and power consumption for RISC-V processors.
SiFive will try to build an easier, cheaper, faster way to design chips with a new $50.6 million funding round that included Huami, the venture arm of China’s Xiaomi. The series C aims to bring the startup to profitability and establish a broad market for its RISC-V cores.
SiFive will release a cloud service for designing RISC-V cores this year. It will expand it into an SoC design platform next year with silicon blocks from partners, said Naveed Sherwani, an industry veteran named chief executive of SiFive last July after 10 years at Open Silicon.
At an event announcing the funding, Sherwani made several ambitious promises he said would amount to a revolution in SoC design.
We use cookies to ensure that we give you the best experience on our website. If you continue to use this site we will assume that you are happy with it.
We are a professional review site that has advertisement and can receive compensation from the companies whose products we review. We use affiliate links in the post so if you use them to buy products through those links we can get compensation at no additional cost to you.OkDecline
10 Comments
Tomi Engdahl says:
HiFive1 Is an Open-Source, Arduino-Compatible RISC-V Dev Kit
http://www.epanorama.net/newepa/2016/11/29/hifive1-is-an-open-source-arduino-compatible-risc-v-dev-kit/
Tomi Engdahl says:
Agam Shah / PCWorld:
SiFive, creators of open RISC-V architecture, announce $8.5M Series B led by Spark Capital as company unveils two new chip designs
Open-source chip mimics Linux’s path to take on closed x86 and ARM CPUs
The RISC-V chip design can be licensed from SiFive
http://www.pcworld.com/article/3194357/internet-of-things/open-source-chip-mimics-linuxs-path-to-take-on-closed-x86-arm-cpus.html
Tomi Engdahl says:
SiFive Unveils the First RISC-V-Based Arduino
https://blog.hackster.io/sifive-unveils-the-first-risc-v-based-arduino-a4d07fe7f21f
In their quest to democratize access to custom silicon, SiFive has announced the very first RISC-V-based Arduino just hours before the start of Maker Faire Bay Area 2017.
Tomi Engdahl says:
SiFive Launches First RISC-V Based CPU Core with Linux Support
https://www.sifive.com/posts/2017/10/04/sifive-launches-first-risc-v-based-cpu-core-with-linux-support/
Inventors of RISC-V Unveil U54-MC Coreplex IP, a 64-Bit Multicore CPU Designed for Embedded Applications that Require a Full Operating System.
SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced the availability of U54-MC Coreplex IP, the industry’s first RISC-V based, 64-bit, quadcore real-time capable application processor with support for full featured operating systems such as Linux.
“The ability for RISC-V developers to develop Linux and other Unix-based operating systems on commercial grade silicon will enable the RISC-V software ecosystem to quickly expand beyond embedded systems, and bring new solutions to market. We look forward to seeing the various markets that are now addressable with SiFive’s U54-MC Coreplex IP.”
Tomi Engdahl says:
SiFive Announces RISC-V SoC
https://hackaday.com/2017/10/04/sifive-announces-risc-v-soc/
Athe the Linley Processor Conference today, SiFive, the semiconductor company building chips around the Open RISC-V instruction set has announced the availability of a quadcore processor that runs Linux. We’ve seen RISC-V implementations before, and SiFive has already released silicon-based on the RISC-V ISA. These implementations are rather small, though, and this is the first implementation designed for more than simple embedded devices.
This announcement introduces the SiFive U54-MC Coreplex, a true System on Chip that includes four 64-bit CPUs running at 1.5 GHz. This SoC is built with TSMC’s 28 nm process, and fits on a die about 30 mm². Availability will be on a development board sometime in early 2018, and if our expectations match the reality of SiFive’s previous offerings, you’ll be able to buy this Open SoC as a BGA package some months after that.
So far, there are few tangible details about the SiFive U54-MC, but what we do know looks great. On the software support front, RISC-V support in GCC is stable and mainlined as of the 7.1 release. LLVM is in the process of being submitted, and Linux support is getting there too. Considering no one outside SiFive has this hardware in hand, this is just fine.
Choose U54‑MC Coreplex
Multi-Core 64-bit RISC-V Applications Processor
https://www.sifive.com/products/coreplex-risc-v-ip/u54-mc/
U54-MC Coreplex IP is the world’s first RISC-V based 64-bit quad-core application processor, supporting full-featured operating systems such as Linux. The U54-MC Coreplex’s high-performance and flexible memory system makes it ideal for applications such as AI, machine learning, networking, gateways, and smart IoT devices.
Tomi Engdahl says:
RISC-V Boots Linux at SiFive
U54 trails but is competitive with ARM A53
https://www.eetimes.com/document.asp?doc_id=1332398&
SiFive has taped out and started licensing its U54-MC Coreplex, its first RISC-V IP designed to run Linux. The design lags the performance of a comparable ARM Cortex-A53 but shows progress creating a commercial market for the open-source instruction set architecture.
A single 64-bit U54 core delivers 1.7 DMIPS/MHz or 2.75 CoreMark/MHz at 1.5 GHz. It measures 0.234 mm2 including its integrated 32+32KB L1 cache in a TSMC 28HPC process using a 12-track library.
A quad-core complex with a 2-MByte shared coherent L2 cache, Gbit Ethernet and DDR3/4 controllers and other peripherals measures ~30 mm2. SiFive will deliver a quad-core chip that includes an E51 management core that will ship in the first quarter on boards targeting software developers.
The single-issue, in-order U54 is expected to lag the performance of ARM’s dual-issue A53. By comparison, in late 2014 Freescale (now NXP) announced the QorIQ LS1043A, a midrange quad-core A53 running at 1.5 GHz delivering more than 16,000 CoreMarks at 6 W.
SiFive believes its part will be competitive in power and area efficiency. It also aims to innovate in its business model.
The startup will offer designers 100 prototype SoCs for $100,000 with no fees on third-party IP bundled with its cores until customers ship their chips. “Today, you pay all the IP costs upfront — we think that’s the wrong way,” said Jack Kang, vice president of business development for SiFive.
It’s still early days for RISC-V vendors and users.
Microsemi and Arduino are SiFive’s only announced customers. The startup claims that it already has multiple licensees of the U54, including military contractors and large semiconductor companies that serve markets including set-top boxes and data center accelerators.
Tomi Engdahl says:
SiFive launched U54-MC Coreplex IP, a RISC-V based, 64-bit, quadcore real-time capable application processor with support for full featured operating systems such as Linux. The cores utilize a five-stage in-order pipeline, support the RV64GC ISA and cache coherence. It is targeted at AI, machine learning, networking, gateways and smart IoT devices.
SiFive Launches First RISC-V Based CPU Core with Linux Support
Inventors of RISC-V Unveil U54-MC Coreplex IP, a 64-Bit Multicore CPU Designed for Embedded Applications that Require a Full Operating System
https://www.sifive.com/posts/2017/10/04/sifive-launches-first-risc-v-based-cpu-core-with-linux-support/
Tomi Engdahl says:
https://semiengineering.com/the-week-in-review-manufacturing-183/
SiFive has joined GlobalFoundries’ FDXcelerator Partner Program. SiFive will be making its RISC-V CPU IPs—such as the E31 and E51 RISC-V cores– available on GF’s 22nm FD-SOI process technology. Based on the open source RISC-V ISA, the E31 offers embedded chip designers new capabilities in high performance within strict area and power requirements. The E51 offers 64-bit performance at 32-bit price, power and area.
SiFive Joins FDXcelerator™ Program to Bring RISC-V Core IP to GLOBALFOUNDRIES’ 22FDX® Process Technology
https://www.sifive.com/posts/2017/11/28/sifive-joins-fdxcelerator-program-to-bring-risc-v-core-ip-to-globalfoundries-22fdx-process-technology/
SiFive announced today that it has joined GLOBALFOUNDRIES’ FDXcelerator™ Partner Program, and will be making RISC-V CPU IP including SiFive’s E31 and E51 RISC-V cores available on GF’s 22FDX® process technology. Based on the open source RISC-V ISA, the SiFive E31 offers embedded chip designers new capabilities in high performance within strict area and power requirements, and the SiFive E51 offers a full 64-bit performance at 32-bit price, power and area.
“As the RISC-V ecosystem continues to grow, SiFive’s leading CPU IP is seeing increased adoption. Our partnership with GF is going to enable an even larger pool of system designers to build on an industry-leading process platform,” said Naveed Sherwani, CEO, SiFive. “SiFive has led the RISC-V ecosystem from early on and we are excited to continue extending RISC-V into new market segments.”
Tomi Engdahl says:
Imperas debuted its RISC-V Processor Developer Suite, a set of models, a software simulator, and tools to validate, verify, and provide early estimation of timing performance and power consumption for RISC-V processors.
RISC-V Processor Developer Suite Announced by Imperas
http://www.imperas.com/articles/risc-v-processor-developer-suite-announced-by-imperas
Tomi Engdahl says:
SiFive Preps RISC-V Cloud Service
Startup snags $50M for SoC platform
https://www.eetimes.com/document.asp?doc_id=1333142
SiFive will try to build an easier, cheaper, faster way to design chips with a new $50.6 million funding round that included Huami, the venture arm of China’s Xiaomi. The series C aims to bring the startup to profitability and establish a broad market for its RISC-V cores.
SiFive will release a cloud service for designing RISC-V cores this year. It will expand it into an SoC design platform next year with silicon blocks from partners, said Naveed Sherwani, an industry veteran named chief executive of SiFive last July after 10 years at Open Silicon.
At an event announcing the funding, Sherwani made several ambitious promises he said would amount to a revolution in SoC design.