The current development of integrated circuits terminated in 2024
IRDS or International Roadmap for Devices and Systems have called IEEE Circuits report drawn up by the development of the road, or roadmap. The organization plans to announce the first official IRDS report next November. It is, however, trickled preliminary data, for example in the form of technical documents. According to them, the current circuits and the development of a smaller scale of the ends around the year 2024.
The forecast would mean in practice that Moore’s Law would cease to exist. The reason for this is the interaction of the physical structures of circuits so small that a smaller scale a silicon-based chips, no longer possible.
There are currently going through the first 11 or 10-nanometer steps in logic circuits. In 2019, the process is changed to 8 or 7 nm, and in 2024 already four or three nanometers. In this case, the logic circuitry transistor gate of the physical width is only 10 nanometers, when it is at the moment the most advanced circles is 24 nanometers.
In practice, the circuit connections will three or four nanometers so small that the parasitic phenomena prevent their reliable operation.
Development does not mean the end of the electronics. Instead of silicon, and the end of the era of CMOS process, it means yes.
Is Moore’s Law dead? Brigadier General Paul Fredenburgh, commandant of the Dwight D. Eisenhower School for National Security and Resource Strategy, asked that question to four industry CEOs last week while visiting Silicon Valley with some of his students. He received four highly nuanced, if not different, answers.
From one perspective or another, all of the CEOs were all correct. It’s taking longer to move from one process node to the next, but there is significantly more compute power being offered at each new node. While that isn’t technically a doubling of transistors every two years or so, performance continues to increase an average of 30% every couple of years, either through architectural changes, new materials or different packaging approaches.
Moreover, there is no end in sight to how long this will continue. 2.5D, fan-out wafer-level packaging and full 3D will radically improve performance and lower power.
What is becoming obvious, though, is that Moore’s Law as it was originally written is getting tougher to follow. There are several reasons for this:
1. Quality is becoming a bigger issue as semiconductors begin making inroads in safety-critical and industrial markets, including autonomous vehicles, robotics and personalized medicine.
2. Market demand for moving to the next process node will continue, but the number of high-volume markets is shrinking. Companies such as Samsung, Intel and Xilinx all need increased transistor density. But for other companies, density isn’t the only way to solve their power/performance/cost issues.
3. Despite the fact that EUV is moving forward after years of delays, the big challenge with advanced nodes is time. EUV will help. But that’s only one piece of the puzzle. It takes longer to design chips at advanced nodes
While Moore’s Law is continuing in one way, it also has ended in another. And while collectively this is referred to as Moore’s Law, it bears only glimmers of resemblance to the observation first penned by Gordon Moore.
In the 48 years since the introduction of the first microprocessor, in 1971, the number of electronic components that can be crammed onto a given area on a chip has increased seven orders of magnitude. That corresponds to a doubling about every two years [see “Moore’s Curse,” IEEE Spectrum, April 2015].
You might think that the performance of previous vacuum-tube electronics could not possibly compare with that record of improvement. Not so. It’s just that the key metric of improvement is different.
An Arm fellow describes, “how I learned to stop worrying and love the end of Moore’s Law.”
At CES in January 2019, Nvidia’s chief executive, Jensen Huang, said what most of us in the tech business had already considered and accepted: Moore’s Law, which predicts regular increases in the computing power of silicon chips, is dead.
Today, the smallest commercially produced chips have feature sizes that are a minuscule 7 nm. As transistors get closer to atomic scale, it’s getting harder to shrink them further. Many believe that today’s most advanced transistor design, the FinFET, can’t get below 5 nm without a major rethink—and that even 5 nm may be prohibitively expensive. That means, in turn, that it’s harder to double the density of transistors on a silicon chip every 24 months, as Moore’s Law predicts.
Two of the world’s largest foundries—Taiwan Semiconductor Manufacturing Co. (TSMC) and Samsung—announced in April that they’d climbed one more rung on the Moore’s Law ladder. TSMC spoke first, saying its 5-nanometer manufacturing process is now in what’s called “risk production”
TSMC says its 5-nm process offers a 15 percent speed gain or a 30 percent improvement in power efficiency. Samsung is promising a 10 percent performance improvement or a 20 percent efficiency improvement. Analysts say these figures are in line with expectations.
Foundries began 7-nm manufacturing without EUV, but later used it to collapse the number of lithographic steps and improve yield. At 5 nm, the foundries are thought to be using 10 to 12 EUV steps
photomasks that contain the patterns are so expensive and each lithography machine itself is a US $100 million
Moore’s Law may not be dead, but at 55 years old, it’s certainly feeling its age, with the pace of semiconductor manufacturing advancement decelerating in recent years. However, a new approach to semiconductor design and integration has arrived: the chiplet, which promises to help restore the microchip industry to its historic rate of advancement.
The global market for processor microchips that utilize chiplets in their manufacturing process is set to expand to $5.8 billion in 2024, rising by a factor of nine from $645 million in 2018, according to the market research firm, Omdia.
In a keynote presentation at this year’s Hot Chips conference, Intel’s chief architect, Raja Koduri, laid out a roadmap to increase transistor density—that is, the number of transistors you can fit on a chip—by a factor of 50.
“We firmly believe there is a lot more transistor density to come,” Koduri said. “The vision will play out over time—maybe a decade or more—but it will play out.”
Why the optimism?
Calling the end of Moore’s Law is a bit of a tradition. As Peter Lee, vice president at Microsoft Research, quipped to The Economist a few years ago, “The number of people predicting the death of Moore’s Law doubles every two years.” To date, prophets of doom have been premature, and though the pace is slowing, the industry continues to dodge death with creative engineering.
Puolijohdevalmistajat ovat kekseliäästi kehittäneet uusia ratkaisuja, joilla Mooren lakina tunnettua pienempään ja energiatehokkaampaan skaalautumista on pidetty hengissä jo vuosikymmeniä. Nyt ollaan jo 5 nanometrissä, mutta kehitys ei pysähdy vieläkään. MIT:n tutkijoiden mukaan uusi materiaali mahdollistaa piirien valmistamisen jopa 1 tai 2 nanometrin viivanleveydellä.
Promising to “innovate with the magic of silicon” Intel is pushing towards the sub-1nm ‘angstrom era of semiconductors’.
Intel is matching foundry rival, TSMC, node-for-node with its new process naming convention, but has also fired the first shot in the race for sub-nanometer terminology. Below 1nm, we’re moving into what it’s now calling the ‘angstrom era of semiconductors’
“We are accelerating our innovation roadmap to ensure we are on a clear path to process performance leadership by 2025,” he says.
Gelsinger goes on to note that Intel “will be relentless in our pursuit of Moore’s Law and our path to innovate with the magic of silicon.”
From the moment transistors went three dimensional, with the move to FinFET (or Tri-Gate in Intel terminology) in 2011, a single dimension measurement has been rendered entirely irrelevant.
This has meant Intel increasingly looks behind the times. Through its manufacturing partner, TSMC, AMD has been able to show off nominally 7nm CPUs while Intel’s desktop chips still languish on an old 14nm node.
But, as we’ve regularly pointed out here on PC Gamer, when it comes to transistor density, Intel’s 10nm node is far more akin to TSMC’s N7, or 7nm node.
the Enhanced SuperFin node forming the basis of the upcoming Alder Lake CPUs, will be using a new convention. First up will be ‘Intel 7′, which is the new name for the nominally 10nm Enhanced SuperFin node, and lines up against TSMC’s N7 process.
Intel 7 is in volume production right now, and Intel claims giving it a new name is fair because of the 10 – 15% performance per watt gains this node is giving over the previous 10nm SuperFin. That’s the sort of perf jump you’d expect from a new process, and Intel is now marketing it as such.
After that we hit ‘Intel 4′, which was previously referred to as 7nm and will line up against TSMC’s N4 process, then we’ll get ‘Intel 3′, and you can guess which rival node that’s going head-to-head with.
Intel 7 delivers an approximately 10% to 15% performance-per-watt increase versus Intel 10nm SuperFin, based on FinFET transistor optimizations. Intel 7 will be featured in products such as Alder Lake for client in 2021 and Sapphire Rapids for the data center, which is expected to be in production in the first quarter of 2022.
Intel 4 fully embraces EUV lithography to print incredibly small features using ultra-short wavelength light.
Intel 3 will be ready to begin manufacturing products in the second half of 2023.
Intel 20A ushers in the angstrom era with two breakthrough technologies, RibbonFET and PowerVia. RibbonFET, Intel’s implementation of a gate-all-around transistor, will be the company’s first new transistor architecture since it pioneered FinFET in 2011.
Intel 20A is expected to ramp in 2024.
2025 and Beyond: Beyond Intel 20A, Intel 18A is already in development for early 2025
After that is where things get super-interesting though, as beyond the Intel 3 products shipping at the tail end of 2023, we then move into another wholly new naming convention. This is the industry moving towards a nominally sub-1nm era, with the name ‘Intel 20A’ being giving to its first new process node of the angstrom era of semiconductors in the first half of 2024.
An angstrom is literally a sub-nanometer unit of measurement, with one angstrom equalling 0.1nm. But Intel is at pains to point out that, despite the ‘A’ in ‘Intel 20A’ standing for angstrom, it is purely a name, not a measurement. So, to be clear, Intel 20A is not a process incorporating transistors measuring 2nm in terms of their gate length.
Intel 20A will also incorporate a new power delivery method, call PowerVia. That in itself will offer the three dimensional chips of tomorrow something called ‘backside power delivery’
ASML plans to introduce new extreme ultraviolet (EUV) lithography equipment that will extend the longevity of Moore’s Law for at least ten years, according to executives at the world’s only supplier of the tools, which are crucial for the world’s most advanced silicon.
Starting in the first half of 2023, the company plans to offer customers equipment that takes EUV numerical aperture (NA) higher to 0.55 NA from the existing 0.33 NA. The company believes that the new equipment will help chip makers reach process nodes well beyond the current threshold (2nm) for at least another 10 years, according to ASML vice president Teun van Gogh, in an interview with EE Times.
Intelin perustajiin kuuluva Gordon Moore julkaisu vuonna 1965 kuuluisan muotoilunsa, jonka mukaan transistorien määrä integroidulla piirillä kaksinkertaistuisi vuosittain. Tätä ”Mooren lakia” on julistettu kuolleeksi useaan kertaan, mutta nyt hollantilainen ASML sanoo lain olevan voimassa vielä ainakin seuraavan kymmenen vuoden ajan.
ASML:n puheilla on merkitystä, sillä yhtiö on maailman suurin askelvalottimien valmistaja. Sen laitteilla valmistetaan merkittävä osa maailman edistyneimmistä mikropiireistä. Nyt yhtiö on antanut pitkän aikavälin teknisen ennusteensa ja sen perusteella Mooren laki voi edelleen hyvin.
Yhtiön perustaja ja teknologiajohtaja Martin van den Brink kertoi, että EUV-litografialla voidaan valmistaa piirejä jopa 0,7 nanometrin viivanleveydellä. Tällä hetkellä edistyneimmät piirit esimerkiksi Applen uusissa iPhone-puhelimissa valmistetaan 5 nanometrin prosessissa. Niihin piirikuviot valotetaan 13 nanometrin EUV-laserilla.
Tällä hetkellä näyttää siltä, että kolmeen nanometriin siirrytään ensi vuonna, kahteen nanometriin vuonna 2024 ja vuoden 2025 puhutaan jo 1,4 nanometristä. ASML:n ennusteessa yhden nanometrin piirejä tullaan näkemään joskus vuosien 2027-2028 aikana. Vuoden 2030 kohdalle Martin van den Brink oli kirjannut lukeman 0,7 nanometriä.
In the world of computer chips, bigger numbers are often better. More cores, higher GHz, greater FLOPs, all desired by engineers and users alike. But there is one measure in semiconductors that’s hot right now, and the smaller, the better. Enter semiconductor manufacturing and the technology node (a.k.a. the process node).
But just exactly what is it, and why is it so important? Why is it measured in nanometers, and why are we going all Sesame Street and bringing this article to you with the numbers 10, 7 and 5?
Benjamin Mayo / 9to5Mac:
Report: Apple and TSMC plan to produce 3nm chips for Macs as soon as 2023, with as many as four dies and up to 40 CPU cores per chip
Apple is taking the PC world by storm with its first debut of Apple Silicon chips inside of Macs, taking what it learned from developing the iPhone and iPad A-series of chips and bringing that architecture to laptops and desktops.
Today, The Information said that Apple has no intent of slowing down and has plans for even faster second- and third-generation chips in the coming years.
The M1, M1 Pro and M1 Max are fabricated on a 5-nanometer process. The report says Apple will follow up with second-generation Apple Silicon chips in 2022, using an upgraded 5-nanometer process. Therefore, the performance and efficiency gains compared to the M1 generation will be relatively small. Apple plans for at least some of these chips to feature two dies, doubling performance in machines that can accommodate larger chips like desktop Macs.
Most notably, The Information says Apple and foundry partner TSMC plan to produce 3-nanometer chips for Macs as soon as 2023. These could feature as many as four dies, with up to 40 CPU cores in total per chip. The three versions of the third-generation chip are reportedly codenamed ‘Ibiza’, ‘Lobos’ and ‘Palma’.
The roadmap suggests that Apple will continue to “easily outperform Intel’s future processors for consumer PCs”, according to the report.
“People claim that Moore’s Law is over, but in my opinion that’s not the case. Moore’s Law can continue by going in the 3rd dimension” —Krishna Saraswat
Intel CEO Pat Gelsinger has announced plans to recover the company’s chip-making crown by 2025. But the company has shared more details about research that could help it compete even further in the future.
The Santa Clara, California-based company revealed a wide range of new technologies in its pipeline that could keep it from falling further behind on Moore’s Law, opening the door to smaller, faster, and cheaper processors with better efficiency. Instead of physically scaling the transistors at the heart of its computer chips, Intel has proposed a way to stack the transistors themselves to pack in more computing resources.
RibbonFETs
Intel is trying to strike back against rivals by rearranging the architecture of its transistors. Intel has previously said it plans to upgrade to “gate-all-around”—also known as “nanosheet”—transistors called RibbonFETs in its 20A technology node.
Intel has announced plans to start manufacturing chips with new RibbonFET transistors inside by 2024. The RibbonFETs are based on sheets of current-carrying silicon stacked in a column. Unlike the FinFETs used in the most advanced chips on the market, where the gate is wrapped around a fin-shaped channel on three sides, the ribbon-shaped channels in Intel’s RibbonFETs are completely surrounded by the gate.
The three-dimensional shape of the RibbonFET means more current flows during the “on” state and less current to leak from the channel when the transistor is switched “off.” The company said that results in better electrostatic control of the transistor and less power leakage, which can sap the final processor’s power efficiency. In the end, the RibbonFETs can consume less power and run faster and more efficiently.
Another key technology in the pipeline is a backside power delivery system for transistors called PowerVia.
3D CMOS Transistors
At IEDM 2021, Intel proposed a new process technology where it stacks nanosheet transistors on top of each other to create more room on the chip to squeeze components. Intel said the 3D CMOS transistors would allow it to pack 30% up to 50% more transistors in every square millimeter of silicon in its products.
The most advanced modern processors contain tens of billions of transistors assembled into logic gates, which are in turn arranged into components such as central processors and memory caches. These logic gates are based on billions of pairs of NMOS and PMOS transistors. The MOSFETs are sprawled out side by side on the plane of the chip, with electric current flowing through the interconnects between them.
But stacking the transistors results in a silicon metropolis with everything closer together.
3D Packaging
Intel is also investing in its advanced packaging arsenal to pack more computing power into the same silicon area. The semiconductor giant plans to start rolling out more products by stacking tiny slabs of silicon called “chiplets or “tiles” on top of each other in three dimensions, mixing and matching a wide range of tiles instead of loading everything on a single system on a chip (SoC).
Intel uses its 3D packaging technology called Foveros to stack tiles with direct copper-to-copper bonding of the interconnects relaying data between the tiles. That results in better power efficiency, interconnect density, and signal routing, while limiting heat dissipation. Intel said it can take advantage of Foveros to place interconnects on the underside of a die as close as 50-µm apart.
Intel said its research department is now working on the next generation called Foveros Direct that reduces the gap between the interconnects to less than 10-µm apart.
Some say that Moore’s Law, which tracks the exponential growth electronics over the last six decades has stalled, and technological stagnation threatens. Mark Rosker, director of DARPA’s Microsystems Technology Office, sees things very differently
Some say that Moore’s Law, which tracks the exponential growth electronics over the last six decades has stalled, and technological stagnation threatens. Mark Rosker, director of DARPA’s Microsystems Technology Office (MTO), sees things very differently. In a new interview with Samuele Lilliu, he explains how the growth described by Moore’s Law has been sustained by waves of innovation from DARPA and how the next stage, what he calls the Fourth Wave, will be carried forward by technologies his office is now developing.
“There have been several problems along the way,” says Rosker. “It hasn’t been a continuous improvement as it’s often represented.”
“Transistors kept getting smaller and smaller and smaller. And that was good. We went from transistors that were many, many microns to things that were starting to be measured in nanometers,” says Rosker.
This worked fine until the transistors were being dwarfed by other parts of the chip, in particular the connectors that control the transistors and the bus lines that transfer data.
“The essential advance that I think most characterized the third wave was the introduction of the FinFET which was first developed by DARPA in the late 1990s,” says Rosker.
“Most transistors that you’re going to find in leading edge electronics, are all developed by this process that DARPA helped develop,” says Rosker.
Now FinFET technology has been pushed as far as it will go and progress is slowing again– leading many to announce the death of Moore’s Law. Rosker says that as we run into limits, we need to move into literally another dimension with complex, three-dimensional chip structures.
“So the fourth wave that’s ahead of us, we will now be imagining dense structures of different types of electronics, different types of transitions, not necessarily all silicon,” says Rosker. “We are seeing lots of indication in the programs that we’re looking at, that the opportunities are an order of magnitude, multi order of magnitude, and may be sustainable for quite a while.”
“What you would like to do is have memory much closer or even within where you do a computation,” says Rosker.
If Rosker is right, then Moore’s Law might keep going for another decade or more – and if it slows down, then DARPA will be there to stir up a fifth wave.
More specifically, we can’t make transistor gates—which control the flow of current from the source to the drain—much smaller than 5 nm because of something called quantum tunneling that prevents them from working as intended. Materials like graphene and carbon nanotubes might be vital to making transistors even smaller thanks to their physical properties, but getting from there to building functional devices will take a while.
In a paper released this week, Chinese researchers explain they’ve created a transistor with the smallest gate length ever reported. This milestone was made possible by creatively utilizing graphene and molybdenum disulfide and stacking them into a staircase structure with two steps.
The trick to this design is that the edge of the graphene sheet is used, which means that when the gate is set to the “on” state, it’s only 0.34 nm wide—essentially the width of the graphene layer itself. Another notable feature of this “side-wall transistor” is its negligible current leakage due to higher off-state resistance. Manufacturers could leverage this quality for low-power applications. Best of all, it would be relatively easy to make, although many of the prototypes required quite a bit of voltage to drive.
Apple once again surprised enthusiasts and analysts with its announcement of the M1 Ultra, a variant of the M1 Max that effectively fuses two chips into one. The result is a dual-chip design viewed by software as a single piece of silicon. Nvidia delivered similar news at the GPU Technology Conference 2022, where CEO Jensen Huang announced that the company will fuse two of the company’s new Grace CPU processors into a single “Superchip.”
These announcements target different markets. Apple has its sights set on the consumer and professional workstation world, while Nvidia intends to compete in high-performance computing. Yet the divergence in purpose only underscores the broad challenges rapidly bringing the era of monolithic chip design to an end.
Mooren laki määrittelee, että transistorien määrä piirisulla kaksinkertaistuu kahden vuoden välein. Lain kuolemaa on ennustettu jo vuosia sirugeometrioiden kutistuessa, mutta ainakin vielä laki pitää kutinsa tiukasti. Tämä näkyy esimerkiksi Applen iPhone-puhelimien järjestelmäpiirien kehityksessä, joka on ollut huimaa.
Vuonna 2013 iPhone 5s:n prosessori oli A7. Piirillä oli vhän yli miljardi transistoria ja se oli valmistettu 28 nanometrin prosessissa. Piillä suoritin vei tilaa 102 neliömillimetriä. Viime vuonna markkinoille tulleen iPhone 13 Pro Maxin A15-prosessorilla oli 15 miljardia transistoria. Tilaa se vei piillä vain 107,7 neliömillimetriä. Valmistusprosessi on 5 nanometriä.
Tämä tarkoittaa, että kahdeksassa vuodessa iPhone-prosessorien CPU-suorituskyky on kasvanut 6,5-kertaiseksi (single core -testin mukaan). Moniydinlaskennan suorituskyky kasvanut samaan aikaan 9,8-kertaiseksi.
Kaikista eniten on noussut grafiikan eli integroidun GPU-prosessoinnin suorituskyky. GFXbecnhmark-testissä A7-prosessori kirjasi tulokseksi 28,7. A15-prosessorin lukema oli 414,1. Suorityskyky on näin kasvanut 14,4-kertaiseksi.
Entäpä se transistorien määrän kasvu? Vuonna 2013 A7-prosessorilla oli miljardia transistoria ja vuonna 2015 A9-piirillä yli kaksi miljardia. Vuonna 2017 A11-piiri nosti transistorien määrän 4,3 miljardiin (prosessina 10 nm). Kaksi vuotta eteenpäin ja A13-piirillä oli 8,5 miljardia transistoria. Ja viime vuonna A15-piirillä transistoreja oli siis yli 15 miljardia. Kyllä Intelin perustanutta Gordon Moorea aikamoiseksi velhoksi täytyy kehua.
Here comes a new ripple in the process node wars among the mega-fab rivals TSMC and Samsung Foundry. The industry reports about TSMC converting its 3-nm process R&D into a 1.4-nm process in June is likely to spark another round of process node duel between Taiwan’s leading pure-play fab and Samsung. However, it’s still not clear how this ambitious conversion to 1.4-nm process geometry will actually work.
Is Moore’s Law slowing down?
What role does More-than-Moore technology play as the industry moves forward?
What are the current challenges faced by manufacturing semiconductors, and is there a solution?
Moore’s Law isn’t really a law of nature or anything else, but it had been a pretty good estimate of how well semiconductor technology was increasing the performance of systems over time. That is until lately, where the Moore’s Law Slowdown ran into power and frequency limitations. When adding the recent chip shortages to the mix, getting the most out of what hardware can be made is important.
The need to industrialize 2D materials to extend Moore’s Law.
The challenge of manufacturing 2D materials at scale.
The solution to the problem of how to industrialize 2D materials.
The International Technology Roadmap for Semiconductors (ITRS) has clearly identified transistors based on 2D materials as one of the key technologies that will offer a long-term solution for extending Moore’s Law. Indeed, the properties and predictable electrical characteristics of 2D materials offer strong potential to continue to extend the remarkable innovation and performance gains we’ve witnessed in the semiconductor industry in the last 50 years.
However, the ITRS isn’t a guarantee that these materials will deliver on this potential. There’s no doubt that the world’s leading semiconductor manufacturers like Intel and TSMC are very keen to understand the manufacturing implications of 2D materials. But, for all of the academic papers in the past 10 years, even the most researched material—graphene—is nowhere near ready for deployment in full, high-volume manufacturing (HVM) production facilities.
The challenge of HVM for 2D materials is significant. But that challenge holds the key to ensuring that 2D materials deliver on the potential, rather than squandering it in a catch-22 of hype.
We’re about to enter a very unique era in the world of silicon fabrication. The currently-used FinFET transistors have been in use since 2011, but as nodes continue to shrink they will need to be replaced by something different. We are now approaching that inflection point, with TSMC recently updating its roadmap to note it’ll be moving to nanosheet transistors once it’s ready for 2nm production. That won’t be for a few more years and Intel and Samsung have announced similar plans.
News of TSMC’s updated roadmap comes in a report from EEtimes, which discusses the company’s future plans. It’s already been widely reported that TSMC will begin its 3nm production at the end of 2022, but this new report confirms its nanosheet plans beyond that. Nanosheets are a type of Gate-All-Around (GAA) transistor that features floating transistor fins with the gate around them, hence the name. Intel has announced similar plans with what it calls RibbonFET. Interestingly TSMC says it expects 2nm nanosheet production to begin in 2025, but Intel’s roadmap has RibbonFET debuting in Q3 of 2024. For its part, Samsung has already shifted to nanowires, which uses thinner fins than nanosheets, for its 3nm process.
The CEO of Nvidia has a message to gamers complaining about the high pricing of the company’s graphics cards. Don’t blame us.
On Wednesday during a videoconference call Q&A with reporters, Nvidia (ticker: NVDA) CEO Jensen Huang was asked about the broad negative reaction from the gaming community over the elevated pricing of its chip maker’s new “Ada Lovelace” graphics cards.
“A 12-inch wafer is a lot more expensive today,” he replied, citing rising chip making costs. “Moore’s Law is dead … It’s completely over.” The executive added the expectations of twice the performance for similar cost was “a thing of the past” for the industry.
When transistors can’t get any smaller, the only direction is up
Perhaps the most far-reaching technological achievement over the last 50 years has been the steady march toward ever smaller transistors, fitting them more tightly together, and reducing their power consumption. And yet, ever since the two of us started our careers at Intel more than 20 years ago, we’ve been hearing the alarms that the descent into the infinitesimal was about to end. Yet year after year, brilliant new innovations continue to propel the semiconductor industry further.
Along this journey, we engineers had to change the transistor’s architecture as we continued to scale down area and power consumption while boosting performance. The “planar” transistor designs that took us through the last half of the 20th century gave way to 3D fin-shaped devices by the first half of the 2010s. Now, these too have an end date in sight, with a new gate-all-around (GAA) structure rolling into production soon. But we have to look even further ahead because our ability to scale down even this new transistor architecture, which we call RibbonFET, has its limits.
So where will we turn for future scaling? We will continue to look to the third dimension. We’ve created experimental devices that stack atop each other, delivering logic that is 30 to 50 percent smaller. Crucially, the top and bottom devices are of the two complementary types, NMOS and PMOS, that are the foundation of all the logic circuits of the last several decades. We believe this 3D-stacked complementary metal-oxide semiconductor (CMOS), or CFET (complementary field-effect transistor), will be the key to extending Moore’s Law into the next decade.
Continuous innovation is an essential underpinning of Moore’s Law, but each improvement comes with trade-offs. To understand these trade-offs and how they’re leading us inevitably toward 3D-stacked CMOS, you need a bit of background on transistor operation.
Stacked CMOS
One commonality of planar, FinFET, and RibbonFET transistors is that they all use CMOS technology, which, as mentioned, consists of n-type (NMOS) and p-type (PMOS) transistors. CMOS logic became mainstream in the 1980s because it draws significantly less current than do the alternative technologies, notably NMOS-only circuits. Less current also led to greater operating frequencies and higher transistor densities.
To date, all CMOS technologies place the standard NMOS and PMOS transistor pair side by side. But in a keynote at the IEEE International Electron Devices Meeting (IEDM) in 2019, we introduced the concept of a 3D-stacked transistor that places the NMOS transistor on top of the PMOS transistor. The following year, at IEDM 2020, we presented the design for the first logic circuit using this 3D technique, an inverter. Combined with appropriate interconnects, the 3D-stacked CMOS approach effectively cuts the inverter footprint in half, doubling the area density and further pushing the limits of Moore’s Law.
Taking advantage of the potential benefits of 3D stacking means solving a number of process integration challenges, some of which will stretch the limits of CMOS fabrication.
We built the 3D-stacked CMOS inverter using what is known as a self-aligned process, in which both transistors are constructed in one manufacturing step. This means constructing both n-type and p-type sources and drains by epitaxy—crystal deposition—and adding different metal gates for the two transistors.
The process might seem complex, but it’s better than the alternative—a technology called sequential 3D-stacked CMOS. With that method, the NMOS devices and the PMOS devices are built on separate wafers, the two are bonded, and the PMOS layer is transferred to the NMOS wafer. In comparison, the self-aligned 3D process takes fewer manufacturing steps and keeps a tighter rein on manufacturing cost, something we demonstrated in research and reported at IEDM 2019.
Importantly, the self-aligned method also circumvents the problem of misalignment that can occur when bonding two wafers. Still, sequential 3D stacking is being explored to facilitate integration of silicon with nonsilicon channel materials, such as germanium and III-V semiconductor materials. These approaches and materials may become relevant as we look to tightly integrate optoelectronics and other functions on a single chip.
The new self-aligned CMOS process, and the 3D-stacked CMOS it creates, work well and appear to have substantial room for further miniaturization. At this early stage, that’s highly encouraging. Devices having a gate length of 75 nm demonstrated both the low leakage that comes with excellent device scalability and a high on-state current. Another promising sign: We’ve made wafers where the smallest distance between two sets of stacked devices is only 55 nm. While the device performance results we achieved are not records in and of themselves, they do compare well with individual nonstacked control devices built on the same wafer with the same processing.
The Future of Moore’s Law
With RibbonFETs and 3D CMOS, we have a clear path to extend Moore’s Law beyond 2024.
With the move to FinFETs, the ensuing optimizations, and now the development of RibbonFETs and eventually 3D-stacked CMOS, supported by the myriad packaging enhancements around them, we’d like to think Mr. Moore will be amazed yet again.
The next wave of Moore’s Law will rely on a developing concept called system technology co-optimization, Ann B. Kelleher, general manager of technology development at Intel told IEEE Spectrum in an interview ahead of her plenary talk at the 2022 IEEE Electron Device Meeting.
“Moore’s Law is about increasing the integration of functions,” says Kelleher. “As we look forward into the next 10 to 20 years, there’s a pipeline full of innovation” that will continue the cadence of improved products every two years. That path includes the usual continued improvements in semiconductor processes and design, but system technology co-optimization (STCO) will make the biggest difference.
The next wave of Moore’s Law will rely on a developing concept called system technology co-optimization, said Ann B. Kelleher, general manager of technology development at Intel in an interview with IEEE Spectrum ahead of her plenary talk at the 2022 IEEE Electron Device Meeting (IEDM).
“Moore’s Law is about increasing the integration of functions,” says Kelleher. “As we look forward into the next 10 to 20 years, there’s a pipeline full of innovation” that will continue the cadence of improved products every two years. That path includes the usual continued improvements in semiconductor processes and design, but system technology co-optimization (STCO) will make the biggest difference.
As computer chips approach the single nanometer scale, at the very limits of the physically possible, the future of semiconductors could lie with the interconnect.
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Tomi Engdahl says:
The current development of integrated circuits terminated in 2024
IRDS or International Roadmap for Devices and Systems have called IEEE Circuits report drawn up by the development of the road, or roadmap. The organization plans to announce the first official IRDS report next November. It is, however, trickled preliminary data, for example in the form of technical documents. According to them, the current circuits and the development of a smaller scale of the ends around the year 2024.
The forecast would mean in practice that Moore’s Law would cease to exist. The reason for this is the interaction of the physical structures of circuits so small that a smaller scale a silicon-based chips, no longer possible.
There are currently going through the first 11 or 10-nanometer steps in logic circuits. In 2019, the process is changed to 8 or 7 nm, and in 2024 already four or three nanometers. In this case, the logic circuitry transistor gate of the physical width is only 10 nanometers, when it is at the moment the most advanced circles is 24 nanometers.
In practice, the circuit connections will three or four nanometers so small that the parasitic phenomena prevent their reliable operation.
Development does not mean the end of the electronics. Instead of silicon, and the end of the era of CMOS process, it means yes.
Source: http://www.etn.fi/index.php/13-news/6061-nykyisten-mikropiirien-kehitys-paattyy-2024
More:
IRDS Reports
http://irds.ieee.org/reports
Tomi Engdahl says:
Time For New Rules
Trying to fit everything into a discussion about Moore’s Law is getting ridiculous.
http://semiengineering.com/time-for-new-rules/
Is Moore’s Law dead? Brigadier General Paul Fredenburgh, commandant of the Dwight D. Eisenhower School for National Security and Resource Strategy, asked that question to four industry CEOs last week while visiting Silicon Valley with some of his students. He received four highly nuanced, if not different, answers.
From one perspective or another, all of the CEOs were all correct. It’s taking longer to move from one process node to the next, but there is significantly more compute power being offered at each new node. While that isn’t technically a doubling of transistors every two years or so, performance continues to increase an average of 30% every couple of years, either through architectural changes, new materials or different packaging approaches.
Moreover, there is no end in sight to how long this will continue. 2.5D, fan-out wafer-level packaging and full 3D will radically improve performance and lower power.
What is becoming obvious, though, is that Moore’s Law as it was originally written is getting tougher to follow. There are several reasons for this:
1. Quality is becoming a bigger issue as semiconductors begin making inroads in safety-critical and industrial markets, including autonomous vehicles, robotics and personalized medicine.
2. Market demand for moving to the next process node will continue, but the number of high-volume markets is shrinking. Companies such as Samsung, Intel and Xilinx all need increased transistor density. But for other companies, density isn’t the only way to solve their power/performance/cost issues.
3. Despite the fact that EUV is moving forward after years of delays, the big challenge with advanced nodes is time. EUV will help. But that’s only one piece of the puzzle. It takes longer to design chips at advanced nodes
While Moore’s Law is continuing in one way, it also has ended in another. And while collectively this is referred to as Moore’s Law, it bears only glimmers of resemblance to the observation first penned by Gordon Moore.
Tomi Engdahl says:
During the 20th Century, Vacuum Tubes Improved in a Moore’s Law-Like Way
https://spectrum.ieee.org/semiconductors/design/during-the-20th-century-vacuum-tubes-improved-in-a-moores-lawlike-way
In the 48 years since the introduction of the first microprocessor, in 1971, the number of electronic components that can be crammed onto a given area on a chip has increased seven orders of magnitude. That corresponds to a doubling about every two years [see “Moore’s Curse,” IEEE Spectrum, April 2015].
You might think that the performance of previous vacuum-tube electronics could not possibly compare with that record of improvement. Not so. It’s just that the key metric of improvement is different.
Tomi Engdahl says:
Moore’s Law Ending? No Problem
https://www.eetimes.com/author.asp?section_id=36&doc_id=1334474
An Arm fellow describes, “how I learned to stop worrying and love the end of Moore’s Law.”
At CES in January 2019, Nvidia’s chief executive, Jensen Huang, said what most of us in the tech business had already considered and accepted: Moore’s Law, which predicts regular increases in the computing power of silicon chips, is dead.
Today, the smallest commercially produced chips have feature sizes that are a minuscule 7 nm. As transistors get closer to atomic scale, it’s getting harder to shrink them further. Many believe that today’s most advanced transistor design, the FinFET, can’t get below 5 nm without a major rethink—and that even 5 nm may be prohibitively expensive. That means, in turn, that it’s harder to double the density of transistors on a silicon chip every 24 months, as Moore’s Law predicts.
Tomi Engdahl says:
Another Step Toward the End of Moore’s Law
https://spectrum.ieee.org/semiconductors/devices/another-step-toward-the-end-of-moores-law
Two of the world’s largest foundries—Taiwan Semiconductor Manufacturing Co. (TSMC) and Samsung—announced in April that they’d climbed one more rung on the Moore’s Law ladder. TSMC spoke first, saying its 5-nanometer manufacturing process is now in what’s called “risk production”
TSMC says its 5-nm process offers a 15 percent speed gain or a 30 percent improvement in power efficiency. Samsung is promising a 10 percent performance improvement or a 20 percent efficiency improvement. Analysts say these figures are in line with expectations.
Foundries began 7-nm manufacturing without EUV, but later used it to collapse the number of lithographic steps and improve yield. At 5 nm, the foundries are thought to be using 10 to 12 EUV steps
photomasks that contain the patterns are so expensive and each lithography machine itself is a US $100 million
Tomi Engdahl says:
TECHNOLOGY
Visualizing Moore’s Law in Action (1971-2019)
https://www.visualcapitalist.com/visualizing-moores-law-in-action-1971-2019/
Tomi Engdahl says:
Chiplets Promise to put Moore’s Law Back on Track
https://www.3dincites.com/2020/05/chiplets-promise-to-put-moores-law-back-on-track/
Moore’s Law may not be dead, but at 55 years old, it’s certainly feeling its age, with the pace of semiconductor manufacturing advancement decelerating in recent years. However, a new approach to semiconductor design and integration has arrived: the chiplet, which promises to help restore the microchip industry to its historic rate of advancement.
The global market for processor microchips that utilize chiplets in their manufacturing process is set to expand to $5.8 billion in 2024, rising by a factor of nine from $645 million in 2018, according to the market research firm, Omdia.
Tomi Engdahl says:
Moore’s Law Lives: Intel Says Chips Will Pack 50 Times More Transistors
https://singularityhub.com/2020/08/23/moores-law-lives-intel-says-chips-will-pack-50-times-more-transistors/
In a keynote presentation at this year’s Hot Chips conference, Intel’s chief architect, Raja Koduri, laid out a roadmap to increase transistor density—that is, the number of transistors you can fit on a chip—by a factor of 50.
“We firmly believe there is a lot more transistor density to come,” Koduri said. “The vision will play out over time—maybe a decade or more—but it will play out.”
Why the optimism?
Calling the end of Moore’s Law is a bit of a tradition. As Peter Lee, vice president at Microsoft Research, quipped to The Economist a few years ago, “The number of people predicting the death of Moore’s Law doubles every two years.” To date, prophets of doom have been premature, and though the pace is slowing, the industry continues to dodge death with creative engineering.
Tomi Engdahl says:
Moore’s law has stalled. Where does processing go from here?
https://www.redsharknews.com/moores-law-has-stalled.-where-does-processing-go-from-here
Tomi Engdahl says:
Will fan-out wafer-level packaging keep Moore’s Law valid?
https://www.edn.com/will-fan-out-wafer-level-packaging-fowlp-keep-moores-law-valid/?utm_content=bufferb1546&utm_medium=social&utm_source=edn_facebook&utm_campaign=buffer
Tomi Engdahl says:
New Transistor Structures At 3nm/2nm
Gate-all-around FETs will replace finFETs, but the transition will be costly and difficult.
https://semiengineering.com/new-transistor-structures-at-3nm-2nm/
Tomi Engdahl says:
Uutta toivoa: Kaksiulotteinen prosessori voisi turvata Mooren lain ja pitää tietokoneet tehon kehityskäyrällä
https://www.tekniikkatalous.fi/uutiset/uutta-toivoa-kaksiulotteinen-prosessori-voisi-turvata-mooren-lain-ja-pitaa-tietokoneet-tehon-kehityskayralla/673fc6a3-5b4e-4492-bc2c-1275241fba93
Tomi Engdahl says:
#TBT: From the 3-nanometer node on, it’s all about nanosheets.
The Nanosheet Transistor Is the Next (and Maybe Last) Step in Moore’s Law
https://spectrum.ieee.org/semiconductors/devices/the-nanosheet-transistor-is-the-next-and-maybe-last-step-in-moores-law
Tomi Engdahl says:
Building “2D” monolayer transistors could help manufacturers break the nanometer barrier and continue improving silicon chips.
Novel “Two-Dimensional” Transistors Could Be the Key to Keeping Moore’s Law Alive
Building “2D” monolayer transistors could help manufacturers break the nanometer barrier and continue improving silicon chips.
https://www.hackster.io/news/novel-two-dimensional-transistors-could-be-the-key-to-keeping-moore-s-law-alive-bf629363768a
Tomi Engdahl says:
https://etn.fi/index.php/13-news/12191-uusi-metalli-vie-piirit-aina-1-nanometriin
Puolijohdevalmistajat ovat kekseliäästi kehittäneet uusia ratkaisuja, joilla Mooren lakina tunnettua pienempään ja energiatehokkaampaan skaalautumista on pidetty hengissä jo vuosikymmeniä. Nyt ollaan jo 5 nanometrissä, mutta kehitys ei pysähdy vieläkään. MIT:n tutkijoiden mukaan uusi materiaali mahdollistaa piirien valmistamisen jopa 1 tai 2 nanometrin viivanleveydellä.
Tomi Engdahl says:
https://singularityhub.com/2021/05/09/ibms-next-generation-chip-tech-shows-off-next-step-in-moores-law/
Tomi Engdahl says:
Intel is changing its process naming to match TSMC node-for-node, promising to “innovate with the magic of silicon.” https://trib.al/DWyreMf
Nanometer no more: Intel changes its process names to match TSMC
By Dave James about 10 hours ago
https://www.pcgamer.com/intel-renames-process-nodes-intros-angstrom-era-of-semiconductors/?utm_medium=social&utm_source=facebook.com&utm_campaign=socialflow
Promising to “innovate with the magic of silicon” Intel is pushing towards the sub-1nm ‘angstrom era of semiconductors’.
Intel is matching foundry rival, TSMC, node-for-node with its new process naming convention, but has also fired the first shot in the race for sub-nanometer terminology. Below 1nm, we’re moving into what it’s now calling the ‘angstrom era of semiconductors’
“We are accelerating our innovation roadmap to ensure we are on a clear path to process performance leadership by 2025,” he says.
Gelsinger goes on to note that Intel “will be relentless in our pursuit of Moore’s Law and our path to innovate with the magic of silicon.”
From the moment transistors went three dimensional, with the move to FinFET (or Tri-Gate in Intel terminology) in 2011, a single dimension measurement has been rendered entirely irrelevant.
This has meant Intel increasingly looks behind the times. Through its manufacturing partner, TSMC, AMD has been able to show off nominally 7nm CPUs while Intel’s desktop chips still languish on an old 14nm node.
But, as we’ve regularly pointed out here on PC Gamer, when it comes to transistor density, Intel’s 10nm node is far more akin to TSMC’s N7, or 7nm node.
the Enhanced SuperFin node forming the basis of the upcoming Alder Lake CPUs, will be using a new convention. First up will be ‘Intel 7′, which is the new name for the nominally 10nm Enhanced SuperFin node, and lines up against TSMC’s N7 process.
Intel 7 is in volume production right now, and Intel claims giving it a new name is fair because of the 10 – 15% performance per watt gains this node is giving over the previous 10nm SuperFin. That’s the sort of perf jump you’d expect from a new process, and Intel is now marketing it as such.
After that we hit ‘Intel 4′, which was previously referred to as 7nm and will line up against TSMC’s N4 process, then we’ll get ‘Intel 3′, and you can guess which rival node that’s going head-to-head with.
Intel 7 delivers an approximately 10% to 15% performance-per-watt increase versus Intel 10nm SuperFin, based on FinFET transistor optimizations. Intel 7 will be featured in products such as Alder Lake for client in 2021 and Sapphire Rapids for the data center, which is expected to be in production in the first quarter of 2022.
Intel 4 fully embraces EUV lithography to print incredibly small features using ultra-short wavelength light.
Intel 3 will be ready to begin manufacturing products in the second half of 2023.
Intel 20A ushers in the angstrom era with two breakthrough technologies, RibbonFET and PowerVia. RibbonFET, Intel’s implementation of a gate-all-around transistor, will be the company’s first new transistor architecture since it pioneered FinFET in 2011.
Intel 20A is expected to ramp in 2024.
2025 and Beyond: Beyond Intel 20A, Intel 18A is already in development for early 2025
After that is where things get super-interesting though, as beyond the Intel 3 products shipping at the tail end of 2023, we then move into another wholly new naming convention. This is the industry moving towards a nominally sub-1nm era, with the name ‘Intel 20A’ being giving to its first new process node of the angstrom era of semiconductors in the first half of 2024.
An angstrom is literally a sub-nanometer unit of measurement, with one angstrom equalling 0.1nm. But Intel is at pains to point out that, despite the ‘A’ in ‘Intel 20A’ standing for angstrom, it is purely a name, not a measurement. So, to be clear, Intel 20A is not a process incorporating transistors measuring 2nm in terms of their gate length.
Intel 20A will also incorporate a new power delivery method, call PowerVia. That in itself will offer the three dimensional chips of tomorrow something called ‘backside power delivery’
Tomi Engdahl says:
Please, no Moore: ‘Law’ that defined how chips have been made for decades has run itself into a cul-de-sac
Are we approaching peak computing? What are the alternatives?
https://www.theregister.com/2021/08/05/moores_law_what_next/
Tomi Engdahl says:
https://interestingengineering.com/new-extreme-ultraviolet-microchip-machine-could-revive-moores-law
Tomi Engdahl says:
ASML Predicts Processors with 300 Billion Transistor by 2030
By Aleksandar Kostovic 2 days ago
The maker of semiconductor-making machines predicts wonderful innovations
https://www.tomshardware.com/news/asml-2030-prediction-300-billion-transistor-processors
Tomi Engdahl says:
Moore’s Law Could Ride EUV for 10 More Years
https://www.eetimes.com/moores-law-could-ride-euv-for-10-more-years/
ASML plans to introduce new extreme ultraviolet (EUV) lithography equipment that will extend the longevity of Moore’s Law for at least ten years, according to executives at the world’s only supplier of the tools, which are crucial for the world’s most advanced silicon.
Starting in the first half of 2023, the company plans to offer customers equipment that takes EUV numerical aperture (NA) higher to 0.55 NA from the existing 0.33 NA. The company believes that the new equipment will help chip makers reach process nodes well beyond the current threshold (2nm) for at least another 10 years, according to ASML vice president Teun van Gogh, in an interview with EE Times.
Tomi Engdahl says:
Mooren laki sai 10 vuotta lisäaikaa
https://etn.fi/index.php/13-news/12668-mooren-laki-sai-10-vuotta-lisaeaikaa
Intelin perustajiin kuuluva Gordon Moore julkaisu vuonna 1965 kuuluisan muotoilunsa, jonka mukaan transistorien määrä integroidulla piirillä kaksinkertaistuisi vuosittain. Tätä ”Mooren lakia” on julistettu kuolleeksi useaan kertaan, mutta nyt hollantilainen ASML sanoo lain olevan voimassa vielä ainakin seuraavan kymmenen vuoden ajan.
ASML:n puheilla on merkitystä, sillä yhtiö on maailman suurin askelvalottimien valmistaja. Sen laitteilla valmistetaan merkittävä osa maailman edistyneimmistä mikropiireistä. Nyt yhtiö on antanut pitkän aikavälin teknisen ennusteensa ja sen perusteella Mooren laki voi edelleen hyvin.
Yhtiön perustaja ja teknologiajohtaja Martin van den Brink kertoi, että EUV-litografialla voidaan valmistaa piirejä jopa 0,7 nanometrin viivanleveydellä. Tällä hetkellä edistyneimmät piirit esimerkiksi Applen uusissa iPhone-puhelimissa valmistetaan 5 nanometrin prosessissa. Niihin piirikuviot valotetaan 13 nanometrin EUV-laserilla.
Tällä hetkellä näyttää siltä, että kolmeen nanometriin siirrytään ensi vuonna, kahteen nanometriin vuonna 2024 ja vuoden 2025 puhutaan jo 1,4 nanometristä. ASML:n ennusteessa yhden nanometrin piirejä tullaan näkemään joskus vuosien 2027-2028 aikana. Vuoden 2030 kohdalle Martin van den Brink oli kirjannut lukeman 0,7 nanometriä.
Tomi Engdahl says:
Aiming for Atoms: The Art of Making Chips Smaller
https://www.techspot.com/article/1856-aiming-for-atoms-chip-manufacturing/
In the world of computer chips, bigger numbers are often better. More cores, higher GHz, greater FLOPs, all desired by engineers and users alike. But there is one measure in semiconductors that’s hot right now, and the smaller, the better. Enter semiconductor manufacturing and the technology node (a.k.a. the process node).
But just exactly what is it, and why is it so important? Why is it measured in nanometers, and why are we going all Sesame Street and bringing this article to you with the numbers 10, 7 and 5?
Tomi Engdahl says:
Benjamin Mayo / 9to5Mac:
Report: Apple and TSMC plan to produce 3nm chips for Macs as soon as 2023, with as many as four dies and up to 40 CPU cores per chip
3nm Mac and iPhone chips coming as soon as 2023, Apple Silicon roadmap leaps ahead of Intel
https://9to5mac.com/2021/11/05/mac-iphone-apple-silicon-future/
Apple is taking the PC world by storm with its first debut of Apple Silicon chips inside of Macs, taking what it learned from developing the iPhone and iPad A-series of chips and bringing that architecture to laptops and desktops.
Today, The Information said that Apple has no intent of slowing down and has plans for even faster second- and third-generation chips in the coming years.
The M1, M1 Pro and M1 Max are fabricated on a 5-nanometer process. The report says Apple will follow up with second-generation Apple Silicon chips in 2022, using an upgraded 5-nanometer process. Therefore, the performance and efficiency gains compared to the M1 generation will be relatively small. Apple plans for at least some of these chips to feature two dies, doubling performance in machines that can accommodate larger chips like desktop Macs.
Most notably, The Information says Apple and foundry partner TSMC plan to produce 3-nanometer chips for Macs as soon as 2023. These could feature as many as four dies, with up to 40 CPU cores in total per chip. The three versions of the third-generation chip are reportedly codenamed ‘Ibiza’, ‘Lobos’ and ‘Palma’.
The roadmap suggests that Apple will continue to “easily outperform Intel’s future processors for consumer PCs”, according to the report.
Tomi Engdahl says:
“People claim that Moore’s Law is over, but in my opinion that’s not the case. Moore’s Law can continue by going in the 3rd dimension” —Krishna Saraswat
2D Semiconductors Stalk Silicon at the Edge of Moore’s Law Researchers are rapidly knocking down the barriers to boosting chip density
https://spectrum.ieee.org/2d-semiconductors-and-moores-law?utm_campaign=RebelMouse&socialux=facebook&share_id=6826486&utm_medium=social&utm_content=IEEE+Spectrum&utm_source=facebook
Tomi Engdahl says:
IBM Unveils Vertical Transistors to Try to Keep Moore’s Law Alive
Dec. 17, 2021
IBM, a powerhouse in the realm of semiconductor research, calls it the Vertical-Transport Field-Effect Transistor (VTFET).
https://www.electronicdesign.com/technologies/embedded-revolution/article/21212101/electronic-design-ibm-unveils-vertical-transistors-to-try-to-keep-moores-law-alive
Tomi Engdahl says:
Intel Proposes New Path for Moore’s Law With 3D Stacked Transistors
Dec. 17, 2021
Intel’s Component Research division keeps its research and development pipeline full by collaborating with its businesses to anticipate future needs and partnering with U.S. labs and other industry players.
https://www.electronicdesign.com/technologies/embedded-revolution/article/21183706/electronic-design-intel-proposes-new-path-for-moores-law-with-3d-stacked-transistors
Intel CEO Pat Gelsinger has announced plans to recover the company’s chip-making crown by 2025. But the company has shared more details about research that could help it compete even further in the future.
The Santa Clara, California-based company revealed a wide range of new technologies in its pipeline that could keep it from falling further behind on Moore’s Law, opening the door to smaller, faster, and cheaper processors with better efficiency. Instead of physically scaling the transistors at the heart of its computer chips, Intel has proposed a way to stack the transistors themselves to pack in more computing resources.
RibbonFETs
Intel is trying to strike back against rivals by rearranging the architecture of its transistors. Intel has previously said it plans to upgrade to “gate-all-around”—also known as “nanosheet”—transistors called RibbonFETs in its 20A technology node.
Intel has announced plans to start manufacturing chips with new RibbonFET transistors inside by 2024. The RibbonFETs are based on sheets of current-carrying silicon stacked in a column. Unlike the FinFETs used in the most advanced chips on the market, where the gate is wrapped around a fin-shaped channel on three sides, the ribbon-shaped channels in Intel’s RibbonFETs are completely surrounded by the gate.
The three-dimensional shape of the RibbonFET means more current flows during the “on” state and less current to leak from the channel when the transistor is switched “off.” The company said that results in better electrostatic control of the transistor and less power leakage, which can sap the final processor’s power efficiency. In the end, the RibbonFETs can consume less power and run faster and more efficiently.
Another key technology in the pipeline is a backside power delivery system for transistors called PowerVia.
3D CMOS Transistors
At IEDM 2021, Intel proposed a new process technology where it stacks nanosheet transistors on top of each other to create more room on the chip to squeeze components. Intel said the 3D CMOS transistors would allow it to pack 30% up to 50% more transistors in every square millimeter of silicon in its products.
The most advanced modern processors contain tens of billions of transistors assembled into logic gates, which are in turn arranged into components such as central processors and memory caches. These logic gates are based on billions of pairs of NMOS and PMOS transistors. The MOSFETs are sprawled out side by side on the plane of the chip, with electric current flowing through the interconnects between them.
But stacking the transistors results in a silicon metropolis with everything closer together.
3D Packaging
Intel is also investing in its advanced packaging arsenal to pack more computing power into the same silicon area. The semiconductor giant plans to start rolling out more products by stacking tiny slabs of silicon called “chiplets or “tiles” on top of each other in three dimensions, mixing and matching a wide range of tiles instead of loading everything on a single system on a chip (SoC).
Intel uses its 3D packaging technology called Foveros to stack tiles with direct copper-to-copper bonding of the interconnects relaying data between the tiles. That results in better power efficiency, interconnect density, and signal routing, while limiting heat dissipation. Intel said it can take advantage of Foveros to place interconnects on the underside of a die as close as 50-µm apart.
Intel said its research department is now working on the next generation called Foveros Direct that reduces the gap between the interconnects to less than 10-µm apart.
Tomi Engdahl says:
Moore’s Not Enough: 4 New Laws of Computing Moore’s and Metcalfe’s conjectures are taught in classrooms every day—these four deserve consideration, too
https://spectrum.ieee.org/on-beyond-moores-law-4-new-laws-of-computing?share_id=6879365
Tomi Engdahl says:
Some say that Moore’s Law, which tracks the exponential growth electronics over the last six decades has stalled, and technological stagnation threatens. Mark Rosker, director of DARPA’s Microsystems Technology Office, sees things very differently
DARPA Aims To Keep Moore’s Law Going — Here’s How
https://lm.facebook.com/l.php?u=https%3A%2F%2Ftrib.al%2Fzr788GE&h=AT10pBMp8Xd6wjWvZLlZ-5JIX_OVp4qaD-SCkVAym1I8g3Qly40OPtLVzu6WVN7UbfjmPrZZ6gv_4Lb-EHaUijjWdcpv3Mu0tF-OBD6v2RJxAh5FT3JqledjBH9-osJ0yQ
Some say that Moore’s Law, which tracks the exponential growth electronics over the last six decades has stalled, and technological stagnation threatens. Mark Rosker, director of DARPA’s Microsystems Technology Office (MTO), sees things very differently. In a new interview with Samuele Lilliu, he explains how the growth described by Moore’s Law has been sustained by waves of innovation from DARPA and how the next stage, what he calls the Fourth Wave, will be carried forward by technologies his office is now developing.
“There have been several problems along the way,” says Rosker. “It hasn’t been a continuous improvement as it’s often represented.”
“Transistors kept getting smaller and smaller and smaller. And that was good. We went from transistors that were many, many microns to things that were starting to be measured in nanometers,” says Rosker.
This worked fine until the transistors were being dwarfed by other parts of the chip, in particular the connectors that control the transistors and the bus lines that transfer data.
“The essential advance that I think most characterized the third wave was the introduction of the FinFET which was first developed by DARPA in the late 1990s,” says Rosker.
“Most transistors that you’re going to find in leading edge electronics, are all developed by this process that DARPA helped develop,” says Rosker.
Now FinFET technology has been pushed as far as it will go and progress is slowing again– leading many to announce the death of Moore’s Law. Rosker says that as we run into limits, we need to move into literally another dimension with complex, three-dimensional chip structures.
“So the fourth wave that’s ahead of us, we will now be imagining dense structures of different types of electronics, different types of transitions, not necessarily all silicon,” says Rosker. “We are seeing lots of indication in the programs that we’re looking at, that the opportunities are an order of magnitude, multi order of magnitude, and may be sustainable for quite a while.”
“What you would like to do is have memory much closer or even within where you do a computation,” says Rosker.
If Rosker is right, then Moore’s Law might keep going for another decade or more – and if it slows down, then DARPA will be there to stir up a fifth wave.
You can see the full 54-minute interview here.
https://vimeo.com/667524271
Tomi Engdahl says:
Moore’s Not Enough: 4 New Laws of Computing
Moore’s and Metcalfe’s conjectures are taught in classrooms every day—these four deserve consideration, too
https://spectrum.ieee.org/on-beyond-moores-law-4-new-laws-of-computing
Tomi Engdahl says:
https://interestingengineering.com/transistors-moores-law
Tomi Engdahl says:
No more transistors: The end of Moore’s law
We can’t make transistors any smaller, is this the end of Moore’s Law?
https://interestingengineering.com/transistors-moores-law
Tomi Engdahl says:
https://etn.fi/index.php/13-news/13200-intel-lupaa-biljoona-transistoria-sirulla-2030
Tomi Engdahl says:
Intel lupaa biljoona transistoria sirulla 2030
https://etn.fi/index.php/13-news/13200-intel-lupaa-biljoona-transistoria-sirulla-2030
Tomi Engdahl says:
Is It the End of the Road for Computing Power?
That phone in your pocket was predicted by Moore’s Law, but it is bumping against its physical and economic limits
https://www.wsj.com/articles/is-it-the-end-of-the-road-for-computing-power-11646389802
Tomi Engdahl says:
Chinese researchers create the world’s smallest transistor gate
Behold the side-wall transistor, possibly the last node for Moore’s Law
https://www.techspot.com/news/93745-chinese-researchers-create-world-smallest-transistor-gate.html
More specifically, we can’t make transistor gates—which control the flow of current from the source to the drain—much smaller than 5 nm because of something called quantum tunneling that prevents them from working as intended. Materials like graphene and carbon nanotubes might be vital to making transistors even smaller thanks to their physical properties, but getting from there to building functional devices will take a while.
In a paper released this week, Chinese researchers explain they’ve created a transistor with the smallest gate length ever reported. This milestone was made possible by creatively utilizing graphene and molybdenum disulfide and stacking them into a staircase structure with two steps.
The trick to this design is that the edge of the graphene sheet is used, which means that when the gate is set to the “on” state, it’s only 0.34 nm wide—essentially the width of the graphene layer itself. Another notable feature of this “side-wall transistor” is its negligible current leakage due to higher off-state resistance. Manufacturers could leverage this quality for low-power applications. Best of all, it would be relatively easy to make, although many of the prototypes required quite a bit of voltage to drive.
Tomi Engdahl says:
Single-Chip Processors Have Reached Their Limits Announcements from Apple and Nvidia prove that chiplets are the future, but interconnects remain a battleground
https://spectrum.ieee.org/single-chip-processors-have-reached-their-limits?share_id=6987301
Apple once again surprised enthusiasts and analysts with its announcement of the M1 Ultra, a variant of the M1 Max that effectively fuses two chips into one. The result is a dual-chip design viewed by software as a single piece of silicon. Nvidia delivered similar news at the GPU Technology Conference 2022, where CEO Jensen Huang announced that the company will fuse two of the company’s new Grace CPU processors into a single “Superchip.”
These announcements target different markets. Apple has its sights set on the consumer and professional workstation world, while Nvidia intends to compete in high-performance computing. Yet the divergence in purpose only underscores the broad challenges rapidly bringing the era of monolithic chip design to an end.
Tomi Engdahl says:
iPhonen suorituskyvyn kasvu ollut hämmästyttävää
https://etn.fi/index.php/13-news/13539-iphonen-suorituskyvyn-kasvu-ollut-haemmaestyttaevaeae
Mooren laki määrittelee, että transistorien määrä piirisulla kaksinkertaistuu kahden vuoden välein. Lain kuolemaa on ennustettu jo vuosia sirugeometrioiden kutistuessa, mutta ainakin vielä laki pitää kutinsa tiukasti. Tämä näkyy esimerkiksi Applen iPhone-puhelimien järjestelmäpiirien kehityksessä, joka on ollut huimaa.
Vuonna 2013 iPhone 5s:n prosessori oli A7. Piirillä oli vhän yli miljardi transistoria ja se oli valmistettu 28 nanometrin prosessissa. Piillä suoritin vei tilaa 102 neliömillimetriä. Viime vuonna markkinoille tulleen iPhone 13 Pro Maxin A15-prosessorilla oli 15 miljardia transistoria. Tilaa se vei piillä vain 107,7 neliömillimetriä. Valmistusprosessi on 5 nanometriä.
Tämä tarkoittaa, että kahdeksassa vuodessa iPhone-prosessorien CPU-suorituskyky on kasvanut 6,5-kertaiseksi (single core -testin mukaan). Moniydinlaskennan suorituskyky kasvanut samaan aikaan 9,8-kertaiseksi.
Kaikista eniten on noussut grafiikan eli integroidun GPU-prosessoinnin suorituskyky. GFXbecnhmark-testissä A7-prosessori kirjasi tulokseksi 28,7. A15-prosessorin lukema oli 414,1. Suorityskyky on näin kasvanut 14,4-kertaiseksi.
Entäpä se transistorien määrän kasvu? Vuonna 2013 A7-prosessorilla oli miljardia transistoria ja vuonna 2015 A9-piirillä yli kaksi miljardia. Vuonna 2017 A11-piiri nosti transistorien määrän 4,3 miljardiin (prosessina 10 nm). Kaksi vuotta eteenpäin ja A13-piirillä oli 8,5 miljardia transistoria. Ja viime vuonna A15-piirillä transistoreja oli siis yli 15 miljardia. Kyllä Intelin perustanutta Gordon Moorea aikamoiseksi velhoksi täytyy kehua.
Tomi Engdahl says:
How real is TSMC’s bid for conversion to 1.4-nm process node?
https://www.edn.com/how-real-is-tsmcs-bid-for-conversion-to-1-4-nm-process-node/#comment-28998
Here comes a new ripple in the process node wars among the mega-fab rivals TSMC and Samsung Foundry. The industry reports about TSMC converting its 3-nm process R&D into a 1.4-nm process in June is likely to spark another round of process node duel between Taiwan’s leading pure-play fab and Samsung. However, it’s still not clear how this ambitious conversion to 1.4-nm process geometry will actually work.
Tomi Engdahl says:
Can Advanced Materials Address Moore’s Law Slowdown and the Chip Shortage?
June 20, 2022
New materials may be able to address the challenges faced by the semiconductor industry.
https://www.electronicdesign.com/industrial-automation/article/21244720/electronic-design-can-advanced-materials-address-moores-law-slowdown-and-the-chip-shortage?utm_source=EG+ED+Analog+%26+Power+Source&utm_medium=email&utm_campaign=CPS220620077&o_eid=7211D2691390C9R&rdx.ident%5Bpull%5D=omeda%7C7211D2691390C9R&oly_enc_id=7211D2691390C9R
What you’ll learn:
Is Moore’s Law slowing down?
What role does More-than-Moore technology play as the industry moves forward?
What are the current challenges faced by manufacturing semiconductors, and is there a solution?
Moore’s Law isn’t really a law of nature or anything else, but it had been a pretty good estimate of how well semiconductor technology was increasing the performance of systems over time. That is until lately, where the Moore’s Law Slowdown ran into power and frequency limitations. When adding the recent chip shortages to the mix, getting the most out of what hardware can be made is important.
Tomi Engdahl says:
Delivering 2D Materials Ready for a “More than Moore” World
June 23, 2022
Over the next few years, we will see 2D materials move out of the lab and gain momentum as a true “more than Moore” commercial high-volume manufacturing proposition.
https://www.electronicdesign.com/industrial-automation/article/21245100/applied-nanolayers-anl-delivering-2d-materials-ready-for-a-more-than-moore-world?utm_source=EG+ED+Analog+%26+Power+Source&utm_medium=email&utm_campaign=CPS220620079&o_eid=7211D2691390C9R&rdx.ident%5Bpull%5D=omeda%7C7211D2691390C9R&oly_enc_id=7211D2691390C9R
What you’ll learn:
The need to industrialize 2D materials to extend Moore’s Law.
The challenge of manufacturing 2D materials at scale.
The solution to the problem of how to industrialize 2D materials.
The International Technology Roadmap for Semiconductors (ITRS) has clearly identified transistors based on 2D materials as one of the key technologies that will offer a long-term solution for extending Moore’s Law. Indeed, the properties and predictable electrical characteristics of 2D materials offer strong potential to continue to extend the remarkable innovation and performance gains we’ve witnessed in the semiconductor industry in the last 50 years.
However, the ITRS isn’t a guarantee that these materials will deliver on this potential. There’s no doubt that the world’s leading semiconductor manufacturers like Intel and TSMC are very keen to understand the manufacturing implications of 2D materials. But, for all of the academic papers in the past 10 years, even the most researched material—graphene—is nowhere near ready for deployment in full, high-volume manufacturing (HVM) production facilities.
The challenge of HVM for 2D materials is significant. But that challenge holds the key to ensuring that 2D materials deliver on the potential, rather than squandering it in a catch-22 of hype.
Tomi Engdahl says:
TSMC’s 3nm process will be its last to use FinFET transistors. After that it will be moving to a gate-all-around nanosheet at 2nm.
TSMC Says it Will Move to Nanosheet Transistors at 2nm
https://www.extremetech.com/computing/336824-tsmc-says-it-will-move-to-nanosheet-transistors-at-2nm?utm_campaign=trueAnthem%3A+Trending+Content&utm_medium=trueAnthem&utm_source=facebook
We’re about to enter a very unique era in the world of silicon fabrication. The currently-used FinFET transistors have been in use since 2011, but as nodes continue to shrink they will need to be replaced by something different. We are now approaching that inflection point, with TSMC recently updating its roadmap to note it’ll be moving to nanosheet transistors once it’s ready for 2nm production. That won’t be for a few more years and Intel and Samsung have announced similar plans.
News of TSMC’s updated roadmap comes in a report from EEtimes, which discusses the company’s future plans. It’s already been widely reported that TSMC will begin its 3nm production at the end of 2022, but this new report confirms its nanosheet plans beyond that. Nanosheets are a type of Gate-All-Around (GAA) transistor that features floating transistor fins with the gate around them, hence the name. Intel has announced similar plans with what it calls RibbonFET. Interestingly TSMC says it expects 2nm nanosheet production to begin in 2025, but Intel’s roadmap has RibbonFET debuting in Q3 of 2024. For its part, Samsung has already shifted to nanowires, which uses thinner fins than nanosheets, for its 3nm process.
Tomi Engdahl says:
https://etn.fi/index.php/13-news/13843-iphonen-teho-kasvanut-kohisten-vuosien-varrella
Tomi Engdahl says:
Nvidia CEO Says ‘Moore’s Law Is Dead’
https://www.barrons.com/articles/nvidia-graphic-card-prices-moores-law-51663778838
The CEO of Nvidia has a message to gamers complaining about the high pricing of the company’s graphics cards. Don’t blame us.
On Wednesday during a videoconference call Q&A with reporters, Nvidia (ticker: NVDA) CEO Jensen Huang was asked about the broad negative reaction from the gaming community over the elevated pricing of its chip maker’s new “Ada Lovelace” graphics cards.
“A 12-inch wafer is a lot more expensive today,” he replied, citing rising chip making costs. “Moore’s Law is dead … It’s completely over.” The executive added the expectations of twice the performance for similar cost was “a thing of the past” for the industry.
Tomi Engdahl says:
Gordon Moore’s law keeps chip leaders ahead of the pack
In the space of just three pages, the director of semiconductor R&D at Fairchild Camera and Instrument Corp. outlined one of the most powerful observations in modern business and science.
https://www.moneycontrol.com/news/opinion/gordon-moores-law-keeps-chip-leaders-ahead-of-the-pack-9268491.html
Tomi Engdahl says:
3D-Stacked CMOS Takes Moore’s Law to New Heights
https://spectrum.ieee.org/3d-cmos
When transistors can’t get any smaller, the only direction is up
Perhaps the most far-reaching technological achievement over the last 50 years has been the steady march toward ever smaller transistors, fitting them more tightly together, and reducing their power consumption. And yet, ever since the two of us started our careers at Intel more than 20 years ago, we’ve been hearing the alarms that the descent into the infinitesimal was about to end. Yet year after year, brilliant new innovations continue to propel the semiconductor industry further.
Along this journey, we engineers had to change the transistor’s architecture as we continued to scale down area and power consumption while boosting performance. The “planar” transistor designs that took us through the last half of the 20th century gave way to 3D fin-shaped devices by the first half of the 2010s. Now, these too have an end date in sight, with a new gate-all-around (GAA) structure rolling into production soon. But we have to look even further ahead because our ability to scale down even this new transistor architecture, which we call RibbonFET, has its limits.
So where will we turn for future scaling? We will continue to look to the third dimension. We’ve created experimental devices that stack atop each other, delivering logic that is 30 to 50 percent smaller. Crucially, the top and bottom devices are of the two complementary types, NMOS and PMOS, that are the foundation of all the logic circuits of the last several decades. We believe this 3D-stacked complementary metal-oxide semiconductor (CMOS), or CFET (complementary field-effect transistor), will be the key to extending Moore’s Law into the next decade.
Continuous innovation is an essential underpinning of Moore’s Law, but each improvement comes with trade-offs. To understand these trade-offs and how they’re leading us inevitably toward 3D-stacked CMOS, you need a bit of background on transistor operation.
Stacked CMOS
One commonality of planar, FinFET, and RibbonFET transistors is that they all use CMOS technology, which, as mentioned, consists of n-type (NMOS) and p-type (PMOS) transistors. CMOS logic became mainstream in the 1980s because it draws significantly less current than do the alternative technologies, notably NMOS-only circuits. Less current also led to greater operating frequencies and higher transistor densities.
To date, all CMOS technologies place the standard NMOS and PMOS transistor pair side by side. But in a keynote at the IEEE International Electron Devices Meeting (IEDM) in 2019, we introduced the concept of a 3D-stacked transistor that places the NMOS transistor on top of the PMOS transistor. The following year, at IEDM 2020, we presented the design for the first logic circuit using this 3D technique, an inverter. Combined with appropriate interconnects, the 3D-stacked CMOS approach effectively cuts the inverter footprint in half, doubling the area density and further pushing the limits of Moore’s Law.
Taking advantage of the potential benefits of 3D stacking means solving a number of process integration challenges, some of which will stretch the limits of CMOS fabrication.
We built the 3D-stacked CMOS inverter using what is known as a self-aligned process, in which both transistors are constructed in one manufacturing step. This means constructing both n-type and p-type sources and drains by epitaxy—crystal deposition—and adding different metal gates for the two transistors.
The process might seem complex, but it’s better than the alternative—a technology called sequential 3D-stacked CMOS. With that method, the NMOS devices and the PMOS devices are built on separate wafers, the two are bonded, and the PMOS layer is transferred to the NMOS wafer. In comparison, the self-aligned 3D process takes fewer manufacturing steps and keeps a tighter rein on manufacturing cost, something we demonstrated in research and reported at IEDM 2019.
Importantly, the self-aligned method also circumvents the problem of misalignment that can occur when bonding two wafers. Still, sequential 3D stacking is being explored to facilitate integration of silicon with nonsilicon channel materials, such as germanium and III-V semiconductor materials. These approaches and materials may become relevant as we look to tightly integrate optoelectronics and other functions on a single chip.
The new self-aligned CMOS process, and the 3D-stacked CMOS it creates, work well and appear to have substantial room for further miniaturization. At this early stage, that’s highly encouraging. Devices having a gate length of 75 nm demonstrated both the low leakage that comes with excellent device scalability and a high on-state current. Another promising sign: We’ve made wafers where the smallest distance between two sets of stacked devices is only 55 nm. While the device performance results we achieved are not records in and of themselves, they do compare well with individual nonstacked control devices built on the same wafer with the same processing.
The Future of Moore’s Law
With RibbonFETs and 3D CMOS, we have a clear path to extend Moore’s Law beyond 2024.
With the move to FinFETs, the ensuing optimizations, and now the development of RibbonFETs and eventually 3D-stacked CMOS, supported by the myriad packaging enhancements around them, we’d like to think Mr. Moore will be amazed yet again.
Tomi Engdahl says:
New Intel research charts a course to trillion-transistor chip designs by 2030
The research describes Intel’s plan to advance 2D transistor and 3D packaging technologies
https://www.techspot.com/news/96852-new-intel-research-charts-course-trillion-transistor-chip.html
Tomi Engdahl says:
Intel’s Take on the Next Wave of Moore’s Law Ann B. Kelleher explains what’s new 75 years after the transistor’s invention
https://spectrum.ieee.org/whats-next-for-moores-law
The next wave of Moore’s Law will rely on a developing concept called system technology co-optimization, Ann B. Kelleher, general manager of technology development at Intel told IEEE Spectrum in an interview ahead of her plenary talk at the 2022 IEEE Electron Device Meeting.
“Moore’s Law is about increasing the integration of functions,” says Kelleher. “As we look forward into the next 10 to 20 years, there’s a pipeline full of innovation” that will continue the cadence of improved products every two years. That path includes the usual continued improvements in semiconductor processes and design, but system technology co-optimization (STCO) will make the biggest difference.
The Device That Changed Everything Transistors are civilization’s invisible infrastructure
https://spectrum.ieee.org/point-contact-transistor
Tomi Engdahl says:
Intel’s Take on the Next Wave of Moore’s Law Ann B. Kelleher explains what’s new 75 years after the transistor’s invention
https://spectrum.ieee.org/whats-next-for-moores-law
The next wave of Moore’s Law will rely on a developing concept called system technology co-optimization, said Ann B. Kelleher, general manager of technology development at Intel in an interview with IEEE Spectrum ahead of her plenary talk at the 2022 IEEE Electron Device Meeting (IEDM).
“Moore’s Law is about increasing the integration of functions,” says Kelleher. “As we look forward into the next 10 to 20 years, there’s a pipeline full of innovation” that will continue the cadence of improved products every two years. That path includes the usual continued improvements in semiconductor processes and design, but system technology co-optimization (STCO) will make the biggest difference.
Tomi Engdahl says:
As computer chips approach the single nanometer scale, at the very limits of the physically possible, the future of semiconductors could lie with the interconnect.
Big Trouble in Little Interconnects At the outer edges of Moore’s Law, connecting components is increasingly the game
https://spectrum.ieee.org/interconnect-back-side-power?share_id=7390553&socialux=facebook&utm_campaign=RebelMouse&utm_content=IEEE+Spectrum&utm_medium=social&utm_source=facebook