Chip Market Brightens in 2017. The semiconductor industry may yet have been flat in 2016, but expects it is expected that the electronics industry rebounds in 2017, probably in the first half. Wall Streeter predicts return to 5% growth. Total IC business growth is expected to be around five percents for few years to come.There seems to several promises to this direction, especially in memory business. Chips Execs See Maturing Industry article says that pessimism about immediate revenue and R&D growth is a sign of a maturing industry.
Thanks to both rising prices and volume sales, the memory sector is expected to lead overall semiconductor sales growth. Sales of memory chips will increase 10% next year to a new record high of $85.3 billion, according to the latest report from IC Insights. NAND flash will grow almost as fast at 10% next year. The average annual growth rate for the memory market is forecast to be 7.3% from 2016-2021. Every year we need 5.6% more bits than previous year, and the unit prices are increasing on both DRAM and Flash.
There will be also other growth sectors. The data center will be the fastest growth segment next year, rising 10%, followed by automotive at 9% and communications at 7%. Consumer and industrial markets growing at about 4% in line with the overall industry. PCs will be the big drag on 2017, declining 2%.
China Dominates Planned Chip Fabs as more than 40% of front end semiconductor fabs scheduled to begin operation between 2017 and 2020 are in China, a clear indication that China’s long-stated ambition to build a significant domestic semiconductor industry is taking shape.
Trump Win Could Mean Big Questions for Manufacturing as while Trump vowed to keep American manufacturing jobs, he offered little in the way of stated policy other than the promise to punish companies that sent manufacturing job outside the US. Questions about trade also could directly affect US manufacturing. How that plays out is a big unknown.
Europe will try to advance chip manufacturing, but not much results in 2017 as currently there is almost no leading-edge digital chip manufacturing left in Europe as the local companies have embraced outsourcing of digital semiconductor manufacturing to foundries. The European Commission intends to reconvene a high-level group of European CEOs and executives to exchange views on Europe’s 10/100/20 nanoelectronics and chip manufacturing project and make adjustments as necessary for a wave of European Union investment supposedly starting in 2020. The two most advanced wafer fab locations left in Europe in terms of deep sub-micron miniaturization belong to Intel in Leixlip, Ireland and Globalfoundries in Dresden, Germany.
Smaller geometries are to be taken into use and researched in 2017. Several chipmakers ramp up their 10nm finFET processes, with 7nm just around the corner. As TSMC, GF/Samsung Battle at 7nm the net result is in the course of 18 months chip designers will see at least three variants of 7nm — separate immersion variants from TSMC and Globalfoundries and the EUV version from GF/Samsung. Intel has yet to detail its 7nm node.
At the same time R&D has begun for 5nm and beyond, but Uncertainty Grows For 5nm, 3nm as costs are skyrocketing. Both 5nm and 3nm present a multitude of unknowns and challenges. To put this in perspective, there are roughly two silicon atoms in 1nm of line width in a chip. Etching Technology Advances as atomic layer etch (ALE) moves to the forefront of chip-making technology—finally. TSMC recently announced plans to build a new fab in Taiwan at a cost of $15.7 billion targeted for TSMC’s 5nm and 3nm processes, which are due out in 2020 and 2022.
Moore’s Law continues to slow as process complexities and costs escalate at each node. Moore’s Law is dead, just not in the way everyone thinks. SiFive believes open source hardware is the way forward for the semiconductor industry. Technological advances keep allowing chips to scale, but the economics are another story – particularly for smaller companies that can’t afford chips in the volumes. The solution, according to San Francisco-based startup, SiFive, is open-source hardware, specifically an architecture developed by the company’s founders called RISC-V (pronounced “risk-five”). Done right SiFive, which was awarded Startup of the Year at the 2016 Creativity in Electronics (ACE) Awards, believes that RISC-V will do for the hardware industry what Linux has done for software. For example 5th RISC-V Workshop Points to Growing Interest in the RISC-V Platform.
Sensors are hot in 2017. These tiny, powerful solutions are creating the interface between the analog and the digital world. Data is everywhere, and sensors are at the very heart of that. While no one really knows what technology’s next “killer application” will be, we are confident that any killer app will rely on sensors.Appliance autonomy promises to make life simpler, but this field has still lots of to improve even after year 2017.
Interface ICs will continue to help simplify high-bandwidth designs while making them more robust and reliable. Application areas that will benefit include automotive, communications, and industrial. Both wired and wireless interface solutions have plenty of applications.
Analog’s status is rising as more sensors and actuators are added into electronic devices, pressure is growing to more seamlessly move data seamlessly back and forth between analog and digital circuitry. IoT pushes up demand for analog content and need for communication between these two worlds will continue to grow. Analog and digital always have fit rather uncomfortably together, and that discomfort has grown as SoCs are built using smaller feature sizes. The demand for analog silicon has always existed in the embedded space, but the advent of the Internet of Things (IoT) is increasing the demand for connected mixed-signal content. At 28nm and 16/14nm, standard “analog” IP includes a fair amount of digital content.
It seems that hardware designer is a disappearing resource and software is the king in 2017. It is becoming less and less relevant in what format the device is used in many applications. Card computers are standard products and are found in many different card formats that can be used in very many applications. Embedded development is changing to more and more coding. More software designers that understand some hardware are needed, but it is not easy to leap to move to the hardware to software.
The power electronics market is moving at very fast pace. Besides traditional industrial, renewable, and traction sectors, new applications such as energy-storage systems, micro-grids, and dc chargers are emerging. As the automotive world moves to electric vehicles, this creates challenges for IGBT and SiC-MOSFET ICs, and their associated gate drivers. New packages for high-voltage IGBTs and high-voltage SiC-MOSFETs are introduced.
More custom power distribution and higher voltages on data center computer systems in 2017. OpenRack and OpenCompute projects are increasing the distribution voltage inside the server itself. This approach, plus transitioning to new materials such as gallium nitride in the power-conversion systems, can reduce overall power consumption by 20% and increase server densities by 30-40%.”
Power Modules and Reference Designs will be looked at in 2017 even more than earlier in power electronics. The semiconductor and packaging technologies used in power modules have advanced considerably, and the industry is developing modules today that are denser, less expensive, and easier to use. Designers want to rely on power modules to speed up designs and optimize space using smaller, easy-to-use power modules. Module manufacturers hope that engineers will increasingly choose a module over a discrete design in many applications.
The bi-directional DC/DC converter has been around for a while, but new applications are quickly emerging which necessitate the use of this architecture in so many more systems. Battery back-up systems need bi-directional DC/DC converters. Applications today require better energy efficiency and such systems as green power with solar or wind generation, need storage so that when there is no wind or sun available the electricity flow is not interrupted.
Power supplies need to become more efficient. Both European Union’s (EU) Code of Conduct (CoC) Tier 1 and CoC Tier 2 efficiency standards are to be taken into use. The European Union’s CoC Tier 1 effectively harmonizes the EU with US DoE Level VI and became effective as a voluntary requirement from January 2014, two years ahead of Level VI. Its adoption as an EU Ecodesign rule is currently under review to become law with an implementation date of January 2017. The key difference between the CoC requirements and Level VI is the new 10% load measure, which imposes efficiency requirements under a low-load condition where historically most types of power supplies have been notoriously inefficient. CoC Tier 2 further tightens the no-load and active mode power consumption limits.
During 2016, wireless-power applications started to pick up across many fields in the semiconductor industry, and it will continue to do so. Wireless power will continue to gain traction with increased consumer demand. Hewlett Packard, Dell, jjPlus, and Witricity have already announced products based on Airfuel standards. And, products based upon the Qi standard will continue to grow at a rapid pace.
Other prediction articles:
In Power & Analog 2017 Forecast: What Experts Are Saying article representatives from major players in the semiconductor industry share their predictions for 2017 regarding power modules, wireless power, data converters, wireless sensing, and more.
Looking Ahead to 2017 article tells on to what SIA is focused on working with. “U.S. semiconductor technology should be viewed as a strategic national asset, and the Administration should take a holistic approach in adopting policies to strengthen this vital sector,” the letter says
Hot technologies: Looking ahead to 2017 article collection has EDN and EE Times editors explore some of the hot technologies in 2017 that will shape next year’s technology trends and beyond.
1,115 Comments
Tomi Engdahl says:
Chip Design Takes on Functional Safety
http://www.eetimes.com/author.asp?section_id=36&doc_id=1331776&
To design chips meeting Functional Safety requirements is no cakewalk. What designers need is an automated end-to-end flow to take the guesswork out of Functional Safety design.
Since the dawn of the compute era, the trifecta of power/performance/area (or PPA as we have come to know it) dominates the discussion of any new chip. Together, they bounded the performance of a compute platform and served as a time-tested benchmark for all new silicon projects.
They have company.
Designers of mission-critical chips for automotive, industrial, medical and enterprise applications now must contend with ensuring failures are avoided and any unavoidable failure is as safe as possible. The challenge of Functional Safety is every bit as daunting as the other three dimensions and poses a few quirks of its own.
Broadly defined, Functional Safety ensures that a system will remain dependable and function as intended even if something unplanned or unexpected happens. While relevant to all mission-critical computing applications, the automotive sector, driven in large part by the growing adoption of advanced driver-assistance systems (ADAS), is taking the lead in defining a safety process. Barring a few exceptions, the framework for the semiconductor industry is the ISO26262 international standard for automotive electric/electronic systems. The standard mandates traceable and documented design and verification methodologies backed by quantitative and quantitative measures of failure rates of the underlying hardware.
Tomi Engdahl says:
GaAs Nanowires Boost Solar
Add-ons to Silicon Panels
http://www.eetimes.com/document.asp?doc_id=1331784&
Fields of vertically oriented gallium arsenide (GaAs) nanowires boost the output of silicon solar panels by 50 percent, converting the part of the spectrum that is inaccessible to silicon solar cells, according to Sol Voltaics (Lund, Sweden).
Sol Voltaics claims its Aeotaxy process — which guarantees that the GaAs nanowires align vertically with opposite doping at each end — permits the light converted by silicon solar cells to pass through while harvesting the unused part of the spectrum to boost a panel’s output.
Tomi Engdahl says:
Robo-car Redraws Auto Landscape
http://www.eetimes.com/author.asp?section_id=36&doc_id=1331791
We can count at least 10 ADAS/autonomous vehicle platforms. How will these hardware and software platforms overlap, interact and compete?
Tomi Engdahl says:
Samsung Targets 4nm in 2020
http://www.eetimes.com/document.asp?doc_id=1331785
Samsung Electronics Co. Ltd. Wednesday (May 24) updated its foundry technology roadmap, including detailing its second-generation FD-SOI platform, several bulk silicon FinFET processes down to 5nm and a 4nm “post FinFET” structure process set to be in risk production in 2020.
Samsung, which formally broke its foundry operation into a separate business unit called Samsung Foundry last week, also reiterated previously announced plans to put extreme ultraviolet (EUV) lithography into production in 2018 at the 7nm node.
Tomi Engdahl says:
12 Views on the Future of Electronics
Neural processors overtake CPUs, GPUs
http://www.eetimes.com/document.asp?doc_id=1331771
Tomi Engdahl says:
Kinam Kim (below), president of Samsung’s semiconductor business, helped kick off the event with a talk that reiterated the optimism of Imec’s chip researchers. He pointed to research suggested that silicon can scale to a 1.5-nm node and, with new materials, perhaps even beyond.
Kim predicted that the DRAM and NAND technologies that Samsung dominates will continue to evolve. But he suggested that neural-network processors will disrupt the CPU and GPU architectures of rivals Intel and Nvidia, pointing to the startup the Korean giant has invested in, Graphcore.
Source: http://www.eetimes.com/document.asp?doc_id=1331771
Tomi Engdahl says:
Samsung has formed a new foundry division and rolled out a range of new processes. Specifically, Samsung plans to develop 8nm, 7nm, 6nm, 5nm and 4nm. It also introduced an 18nm FD-SOI technology.
GlobalFoundries has provided more details about its 300mm fab plans in China. The company and the Chengdu municipality have announced an investment to develop an ecosystem for its 22nm FD-SOI technology in China.
Source: https://semiengineering.com/week-review-manufacturing/
Tomi Engdahl says:
Verification And Validation Don’t Mean The Same Thing
https://semiengineering.com/verification-validation-dont-mean-thing/
The two tasks have different goals and require a different approach.
Tomi Engdahl says:
Foundry Wars, Take Two
https://semiengineering.com/foundry-wars-take-two/
What multiple process nodes and market uncertainties mean to the design world.
Samsung, GlobalFoundries, TSMC and Intel all have declared their intention to fill in nearly every node possible with multiple processes, different packaging options, and new materials. In fact, the only number that hasn’t been taken so far is 9nm.
It’s not that one foundry’s 10nm is the same as another’s. Each company defines its nodes differently, and these days comparing nodes is almost meaningless. Moreover, markets generally don’t care. Transistor density doesn’t have equal weight for many of the new application areas the foundries are trying to address. In up-and-coming markets, no one is sure what will be critical factors, which is why there are so many possible configurations floating around.
Tomi Engdahl says:
But this mad race to fill in every whole number node—and after 2nm every half-number node, starting with 1.5nm—is becoming a big problem for EDA and IP companies.
Source: https://semiengineering.com/foundry-wars-take-two/
Tomi Engdahl says:
Automotive, medical, industrial, IoT, augmented reality, cloud/server and other markets are the big new market opportunities that have been identified by many companies. But which chips, at which nodes, and in which configurations or packages isn’t obvious at this point. And that’s a problem for EDA vendors, which already are stretching their resources.
Source: https://semiengineering.com/foundry-wars-take-two/
Tomi Engdahl says:
Toward Continuous HW-SW Integration
https://semiengineering.com/shifting-left-toward-continuous-integration/
Increased complexity and heterogeneity are prompting new methods that can avert surprises at the end of the design cycle.
Hardware is only as good as the software that runs on it, and as system complexity grows that software is lagging behind.
The way to close that gap is to improve the methodology for developing that software in the first place. That includes making sure updates are verified and tested before being pushed out to devices, adding the same kinds of detailed checks that chipmakers have used to develop hardware in the past.
Trying to shift software development further left isn’t a new idea, of course. A number of approaches have been developed over the years to solve this problem. Agile software methods, for example, attempt to reduce errors by pooling the efforts of two or more software developers working simultaneously on code. Continuous integration, meanwhile, addresses the problem from a different angle. In essence, code is checked into a shared repository or development branch continuously, and then verified by frequent automated builds to find problems early.
“More and more development teams are using continuous integration as a means to streamline the overall development process, and to avoid unpleasant surprises during the integration phases of development,”
With continuous integration, a digital twin is developed simultaneously with the real machine, ideally from the initial concept. The approach also allows development teams to work in more isolated teams, where the concept of continuous integration might apply more for the system, becoming a question of “when” the code is ready to integrate into the system.
“For example, take the Xilinx UltraScale+ MPSoC, which integrates quad ARM Cortex-A53 cores, Cortex-R5 cores, and an FPGA fabric, with multiple power planes enabling functional separation,” Kurisu said. “One would expect multiple development teams to be writing code for this SoC—one team developing Linux on the application cores, another team developing safety applications on the real-time cores, and another implementing algorithms on the FPGA fabric. Architecturally, each of these application areas might communicate over a defined interface. Although each of these individual teams might use a continuous integration methodology to build the code that runs on their cores, the main part of the integration begins once all the parts of the system are available. Here again, the question of continuous integration is tied to the question of when code is ready for full-system integration.”
Complexity has been growing steadily, in part because no one is quite sure what kinds of chips or functionality will be required across a wide swath of nascent markets, such as virtual/augmented reality, automotive, medical, industrial IoT and deep learning. A common approach has been to throw multiple processor types and functionality onto a chip, because that is a cheaper alternative than trying to put everything into a single ASIC, and and then glue it all together with software.
But as the number of heterogeneous elements in a design continues to expand, this is just one more option for simplifying the development process.
“One could argue that today’s state of the art in both software and hardware would preclude the need for continuous integration,” said Mentor’s Kurisu. “A model-based design actually motivates the approach, and in fact creates leverage for a continuous integration methodology.”
Tomi Engdahl says:
Measurements Help Minimize EMI and RFI
http://www.mwrf.com/test-measurement/measurements-help-minimize-emi-and-rfi?NL=MWRF-001&Issue=MWRF-001_20170525_MWRF-001_0&sfvc4enews=42&cl=article_1_b&utm_rid=CPG05000002750211&utm_campaign=11276&utm_medium=email&elq2=2641e1044bbf448b8228a129f6f69615
Electronic energy is widespread in most operating environments, and circuits must be designed so that they don’t add to the totals—or succumb to the interference.
Tomi Engdahl says:
New graphical programming platform accelerates understanding
http://www.controleng.com/single-article/new-graphical-programming-platform-accelerates-understanding/55c116e5026af7ab71c721d591c89b31.html
National Instruments LabVIEW NXG 1.0 software, the next generation of LabVIEW, aims to deliver LabVIEW productivity to nonprogrammers with an easier workflow. NI continues LabView 2017 development and support.
National Instruments (Nasdaq: NATI) announced LabVIEW NXG 1.0, the first release of the next generation of LabVIEW engineering system design software on May 23 at NIWeek. NI, calling itself “provider of platform-based systems that enable engineers and scientists to solve the world’s greatest engineering challenges,” said in its announcement that “LabVIEW NXG bridges the gap between configuration-based software and custom programming languages with an innovative new approach to measurement automation that empowers domain experts to focus on what matters most – the problem, not the tool.”
Differences with LabView 2017
NI said LabVIEW NXG introduces a re-engineered editor with functionality that experienced LabVIEW users often request and still offers a user experience similar to complementary software in the market. The refreshed editor extends the openness of LabVIEW to integrate with a broader set of languages. The modernized editor improves programming productivity by streamlining the editor micro-interactions, user interface objects based on vector graphics and zooming capabilities.
Tomi Engdahl says:
Big Data Reshapes Silicon
The view of Compute 2.0 from Bristol
http://www.eetimes.com/document.asp?doc_id=1331781
The huge data sets collected by web giants such as Amazon, Google, and Facebook are fueling a renaissance of new chips to process them. Two of the latest efforts will be described at an annual conference on computer architecture in late June.
Stanford researchers will describe Plasticine, a reconfigurable processor that sports nearly 100x better performance/watt than an FPGA while being easier to program. Separately, two veteran designers at Nvidia were part of a team that defined an inference processor that delivers more than twice the performance and energy efficiency of exiting devices.
The chips represent tips of an iceberg of work. Intel acquired three machine-learning startups in the past year. Rival Samsung, along with Dell EMC, invested in Graphcore (Bristol, U.K.), one of a half-dozen independent startups in the area.
Meanwhile, Nvidia is racking up rising sales for its GPUs as neural network training engines. Simultaneously, it is morphing its architecture to better handle such jobs.
Google claims that neither its massive clusters of x86 CPUs nor Nvidia’s GPUs are adequate. So it has rolled out two versions of its own accelerator, the TPU.
“This is Compute 2.0; it is absolutely a new world of computing,” said Nigel Toon, chief executive of Graphcore. “Google eventually will use racks and racks of TPUs and almost no CPUs because 98 percent of its revenues come from search,” a good application for machine learning.
Tomi Engdahl says:
What Will Happen to Intel’s Internet of Things Business?
The chipmaker talks a lot about its growing IoT business, but it still isn’t generating enough cash to become a major pillar of growth.
https://www.fool.com/investing/2017/05/21/what-will-happen-to-intels-internet-of-things-busi.aspx
Intel (NASDAQ:INTC) CEO Brian Krzanich frequently highlights the Internet of Things (IoT) as a key growth market for the aging chipmaker. But critics are quick to point out that the segment generated just 5% of its revenues and 3% of the company’s operating income last quarter — so it’s hardly a pillar of growth for the company.
Revenue at the business rose 11% annually to $721 million during the quarter, fueled by rising demand for its industrial, video, and automotive chips. But operating income fell 15% to $105 million due to higher investments in driverless cars and other technologies.
Looking ahead, will Intel’s IoT business ever become big enough to be considered a core business? Or will it remain a tiny side business compared to its core PC and data center businesses?
1. Industrial chips
Intel’s IoT chips are used across a wide variety of industries, including manufacturing, healthcare, retail, energy companies, and smart homes. These low-powered chips gather information from various devices and transfer them to cloud-based platforms for analysis.
2. Driverless cars
Intel recently agreed to buy Mobileye (NYSE:MBLY), the world’s largest vendor of ADAS (advanced driver assistance systems), for over $15 billion. Mobileye also produces EyeQ computer vision chips that help vehicles “see” and respond to their surroundings.
3. IoT video solutions
A crucial core technology in the driverless vehicle push is computer vision. That’s why Intel acquired computer vision start-up Movidius last September. Movidius is the developer of Project Tango, a project from Alphabet’s Google that creates virtual overlays of real-world surfaces with depth-sensing cameras — a concept which is related to Intel’s own augmented reality headset, Project Alloy. Buying both Movidius and Mobileye should significantly strengthen Intel’s own RealSense depth-sensing cameras.
4. Wearable devices
Wearable devices — powered by the button-sized Curie module or SD-card sized Edison chip — were featured prominently in Intel’s earlier promotions of IoT technologies. The company also acquired fitness watchmaker Basis and smart eyewear maker Recon in 2015. Intel secured high-profile partnerships with Google, Fossil, Oakley, and Tag Heuer to develop new fitness trackers and smartwatches. It even put its chips into a wide variety of bracelets and experimental smart clothing.
Tomi Engdahl says:
Verification Cowboys
https://semiengineering.com/verification-cowboys/
What does it take to be a successful EDA startup? Seven verification company executives provide some insight.
Tomi Engdahl says:
Microchip’s PIC32MZ DA — The Microcontroller With A GPU
http://hackaday.com/2017/05/30/microchips-pic32mz-da-the-microcontroller-with-a-gpu/
When it comes to displays, there is a gap between a traditional microcontroller and a Linux system-on-a-chip (SoC). The SoC that lives in a smartphone will always have enough RAM for a framebuffer and usually has a few pins dedicated to an LCD interface. Today, Microchip has announced a microcontroller that blurs the lines between what can be done with an SoC and what can be done with a microcontroller. The PIC32MZ ‘DA’ family of microcontrollers is designed for graphics applications and comes with a boatload of RAM and a dedicated GPU.
The key feature for this chip is a boatload of RAM for a framebuffer and a 2D GPU. The PIC32MZ DA family includes packages with 32 MB of integrated DRAM designed to be used as framebuffers. Support for 24-bit color on SXGA (1280 x 1024) panels is included. There’s also a 2D GPU in there with support for sprites, blitting, alpha blending, line drawing, and filling rectangles. No, it can’t play Crysis — just to get that meme out of the way — but it is an excellent platform for GUIs.
http://ww1.microchip.com/downloads/en/DeviceDoc/60001361D.pdf
Tomi Engdahl says:
Flexible nanogenerator acts as loudspeaker, microphone
https://semiengineering.com/powerperformance-bits-may-30/
Engineers at Michigan State University developed a paper-thin, flexible ferroelectret nanogenerator, or FENG, that can both generate energy from human motion and act as a loudspeaker and microphone.
“This is the first transducer that is ultrathin, flexible, scalable and bidirectional, meaning it can convert mechanical energy to electrical energy and electrical energy to mechanical energy,” said Nelson Sepulveda, MSU associate professor of electrical and computer engineering.
The FENG starts with a silicone wafer, which is then fabricated with several layers of environmentally friendly substances including silver, polyimide and polypropylene ferroelectret. Ions are added so that each layer in the device contains charged particles.
How scientists turned a flag into a loudspeaker
http://msutoday.msu.edu/news/2017/how-scientists-turned-a-flag-into-a-loudspeaker/
A paper-thin, flexible device created at Michigan State University not only can generate energy from human motion, it can act as a loudspeaker and microphone as well, nanotechnology researchers report today in Nature Communications.
The audio breakthrough could eventually lead to such consumer products as a foldable loudspeaker, a voice-activated security patch for computers and even a talking newspaper.
Tomi Engdahl says:
Apple, Intel Attack Rivals
SoC hire, new CPUs hit Q’comm, AMD
http://www.eetimes.com/document.asp?doc_id=1331806&
Apple and Intel got an edge on rivals in separate moves that came to light Tuesday (May 30), showing heated competition in semiconductors. Apple hired a top Qualcomm engineering manager expected to lead its SoC efforts while Intel announced a new high-end PC processor family, leapfrogging renewed competition from Advanced Micro Devices.
Apple hired Esin Terzioglu, a vice president of engineering who led the central engineering group at Qualcomm’s semiconductor division for the last eight years. For its part, Intel announced its Core i9 Extreme Edition family, including an 18 core, 36 thread chip that leapfrogs AMD’s Ryzen Threadripper, a 16 core, 32 thread chip announced in mid-May.
Tomi Engdahl says:
Arrow is now a design and software company
Before everything was easier. Arrow Electronics was known as a component wholesaler, which provided circuitry for all potential suppliers and little technical support, but not much else. New Arrow is a very different company.
Arrow is nowadays nothing but a iron supplier.
Arrow has deliberately sought to get rid of his old image as a “just” broadline distributor. For a couple of years, the company has made it through its Five Years Out slogan. According to Smith and Bickley, it is not a matter of solving the eternal problem of basic distribution: small margins in a sector where volumes threaten to shrink. Instead, Arrow helps businesses move to the Internet of Things.
- Traditionally, companies are either hardware or software experts. IoT is, however, a complex and multidisciplinary challenge that, however, includes both sides. We want to solve this customer problem, the men say.
According to Bickley, 70 per cent of Arrow’s IoT customers are new acquaintances. Businesses that are bringing IoT into their own business but have no idea how to do it. – For these companies, Arrow is the supplier of the solution. Our role is to be implementing this “überisation”.
The industrial internet also forces Arrow’s old customers to come up again.
- Ten years ago this would have been an absolutely impossible idea. We could not have told the journalist what these should develop. Now, big suppliers like Cypress, Analog Devices, Intel and Microsoft are listening to us when the IoT world needs to develop products, Smith praises.
Source: http://www.etn.fi/index.php/13-news/6392-arrow-on-nyt-suunnittelu-ja-softayritys
Tomi Engdahl says:
VTT Senior Research Scientist Jaakko Leppäniemi has demonstrated in his dissertation that metal oxide print thin film transistors can challenge the amorphous silicon transistors used in current displays.
VTT has printed thin film transistors on flexible plastic substrates with better electrical properties and performance than existing liquid crystal display transistors.
Flexible electronic circuits printed on plastic are shown along with suitable flexible displays, for example, on smart clothes or even on contact lenses, which could measure blood sugar at the same time.
Metal oxide-based printed and low-cost thin film transistors can be used in the future for example in flexible displays and bio-sensors.
Source: http://www.uusiteknologia.fi/2017/06/01/muoville-painetut-transistorit-jopa-muita-parempia/
Tomi Engdahl says:
Mentor Embedded 20th Anniversary
Mentor Embedded Celebrates 20 Years in Embedded Systems
https://www.mentor.com/embedded-software/20th-anniversary?contactid=1&PC=L&c=2017_05_31_esd_newsletter_update_v5
Tomi Engdahl says:
Home> Community > Blogs > Rowe’s and Columns
LabVIEW NXG: Version 2.0 is coming
http://www.edn.com/electronics-blogs/rowe-s-and-columns/4458451/LabVIEW-NXG–Version-2-0-is-coming
Every year at NI Week, National Instruments makes a huge splash with a new version of LabVIEW. Because NI Week is a user conference, the LabVIEW faithful stand and cheer when they can save even just a few clicks. Although NI introduced new features in LabVIEW 2017, this year was different because of LabVIEW NXG.
On May 23 2017, NI officially introduced LabVIEW NXG 1.0, the first totally rewritten LabVIEW since LabVIEW 2 in 1992 when the first Windows version came out. The faithful greeted LabVIEW NXG’s introduction with blank faces or raised eyebrows.
LabVIEW 2017, also introduced at NI Week, is not NXG. That is, it follows the strain released in 1992. LabVIEW 2017 received some cheers for features such as better integration with other languages, particularly Python, but not to the usual thunderous applause and certainly nothing compared to the most thunderous applause of all: the introduction of undo with LabVIEW 5 in 1998.
NI admitted that LabVIEW NXG 1.0 is not ready for prime time. Indeed, LabVIEW NXG 2.0 was on display in the exhibit hall. Version 1.0 lacks many features of LabVIEW 2017. Its purpose is to give users a view of what’s coming in version 2.0 and beyond. Just like USB 2.0 was really USB 1.0, the same holds for LabVIEW NXG.
Tomi Engdahl says:
Radio Shack to Close Most Retail Stores
http://www.electronicdesign.com/communications/radio-shack-close-most-retail-stores
Though Radio Shack will shutter over 1000 stores this holiday weekend, the firm isn’t going away as it emphasizes its online retail business.
Those of us who grew up with electronics will miss going to a Radio Shack store. After 95 years of business, Radio Shack is closing most of its retail establishments. At one time, they had over 7,000 stores—you could easily find one anywhere in the country if the need arose for a battery, cable, small parts, CB, or family radios.
Now where do we go? Online, of course. Most of us who buy electronic parts and accessories will readily make the switch, considering the fact that so much of the electronics business is online anyway.
Over this Memorial Day weekend, Radio Shack will close over 1000 stores, leaving less than 70 corporate and 500 Radio Shack dealer stores around the country.
Tomi Engdahl says:
Sourcing Used Equipment
https://semiengineering.com/sourcing-used-equipment/
SurplusGlobal’s EVP talks about equipment shortages in 200mm equipment and why this market is in crisis mode.
E: What is the status of the 200mm new or used equipment market today?
Greig: Right now, there is a large shortage of 200mm equipment. We’ve just noticed recently a little slowdown in the buying of equipment. That’s because there is nothing to buy. So we are scrounging around for 200mm available equipment, and it’s very difficult. And in some cases, folks who are selling equipment right now can ask for high prices. They are getting it because companies are desperate for equipment.
SE: Before we explore that, let’s start with the fab capacity equation. 200mm fabs are running at or near 100% utilization now. Is that the case and what’s driving the demand?
Greig: It’s still very high. We believe it’s still way above 90%. There is huge growth in the automotive sector and the sensor business. Everything that people were talking about two years ago regarding increased demand is coming to fruition.
Tomi Engdahl says:
Low Cost 1.5 A Gate Drivers
https://www.eeweb.com/company-news/ixys/low-cost-1.5-a-gate-drivers
The IX4426, IX4427, and IX4428 are low-cost dual low side gate driver ICs. The gate drivers outputs are capable of sourcing and sinking 1.5 A, and they have a wide operating voltage range of 4.5 V to 35 V
The IX4426 is configured as a dual inverting driver; the IX4427 is configured as a dual noninverting driver; and the IX4428 is configured with one inverting and one non-inverting driver. All versions have an industry standard pinout, and are available in an 8-lead SOIC package. The IX4426N, IX4427N and IX4428N devices are lower cost drop in replacements for various competitive 1.5 A gate drivers, while providing a much higher 35 V operating capability.
The low cost IX4426/7/8 drivers are well suited for driving power MOSFETS and IGBTs in switching power supplies, motor controls, and DC to DC converters.
Tomi Engdahl says:
Pointing to Progress in Probe Stations
http://www.mwrf.com/test-measurement/pointing-progress-probe-stations?NL=MWRF-001&Issue=MWRF-001_20170601_MWRF-001_724&sfvc4enews=42&cl=article_2_b&utm_rid=CPG05000002750211&utm_campaign=11360&utm_medium=email&elq2=1d7cda08214343419a439db9229fe70f
Mechanical precision and repeatability enable RF/microwave probe stations to support on-wafer measurements through millimeter-wave frequencies.
Tomi Engdahl says:
Chip Makers Build Fortunes From RF MEMS
There is “plenty of room at the bottom” for microelectromechanical systems, but the market for the technology is growing increasingly crowded.
http://www.mwrf.com/semiconductors/chip-makers-build-fortunes-rf-mems?NL=MWRF-001&Issue=MWRF-001_20170601_MWRF-001_724&sfvc4enews=42&cl=article_1_b&utm_rid=CPG05000002750211&utm_campaign=11360&utm_medium=email&elq2=1d7cda08214343419a439db9229fe70f
Tomi Engdahl says:
DRAM Price Surge Continues
Dylan McGrath
http://www.eetimes.com/document.asp?doc_id=1331796&
Global DRAM sales reached a record high of $14.1 billion in the first quarter, driven by a roughly 30 percent increase in the average contract price of PC DRAM modules, according to memory chip price tracking firm DRAMeXchange.
First quarter DRAM revenue was up by more than 13 percent compared with the fourth quarter of 2016, the firm said.
According to DRAMeXchange, most PC OEMs negotiated first quarter DRAM contracts at the end of 2016, when DRAM was in tight supply. Not only did these price increases affect PC DRAM, but they also spilled over into the server and mobile DRAM markets, increasing the price of mobile DRAM products by nearly 10 percent on average, according to the firm.
Tomi Engdahl says:
Apple, Intel Attack Rivals
SoC hire, new CPUs hit Q’comm, AMD
http://www.eetimes.com/document.asp?doc_id=1331806
Apple and Intel got an edge on rivals in separate moves that came to light Tuesday (May 30), showing heated competition in semiconductors. Apple hired a top Qualcomm engineering manager expected to lead its SoC efforts while Intel announced a new high-end PC processor family, leapfrogging renewed competition from Advanced Micro Devices.
Apple hired Esin Terzioglu, a vice president of engineering who led the central engineering group at Qualcomm’s semiconductor division for the last eight years. For its part, Intel announced its Core i9 Extreme Edition family, including an 18 core, 36 thread chip that leapfrogs AMD’s Ryzen Threadripper, a 16 core, 32 thread chip announced in mid-May.
Tomi Engdahl says:
NAND Shortage Drives Price Surge
http://www.eetimes.com/document.asp?doc_id=1331838&
Contract pricing for NAND flash memory surged by 20 to 25 percent in the first quarter, a strong testament to the undersupply condition that persists in the market, according to DRAMeXchange, a firm that tracks memory chip pricing.
NAND revenue typically falls off considerably between the seasonally strong fourth quarter and the the first quarter of the year, traditionally a slow season for end device shipments. However, in the first quarter of this year, global NAND revenue declined by just 0.4 percent, as the reduction of two-dimensional NAND capacity was severe enough to create tight demand, DRAMeXchange said.
Prices of mobile storage products such as embedded multi-chip package (eMCP), embedded multi-media card (eMMC) and universal flash storage (UFS) also continue climbing, DRAMeXchange said.
http://www.dramexchange.com/
Tomi Engdahl says:
NOR ports in living cells
A group of scientists at the University of Washington’s synthetic biology have developed a new method for processing digital information in live cells. Scientists built a set of synthetic genes that work in cells like NOR gates. NOR ports can be assembled into different arrangements for all types of information processing circuits.
Live cells need to continually process information to monitor their changing environment and to reach an appropriate response. Through millions of years of experimentation and error, evolution has come to a certain level of data processing at the cellular level.
Source: http://www.etn.fi/index.php/13-news/6408-nor-portteja-elavissa-soluissa
Tomi Engdahl says:
Tech Talk: Cryogenic DRAM
What happens when you use DRAM at extremely low temperatures?
https://semiengineering.com/tech-talk-cryogenic-dram/
Rambus Chief Scientist Craig Hampel talks with Semiconductor Engineering about quantum computing and the power/performance benefits of running DRAM at extremely low temperatures.
Tomi Engdahl says:
The memories are now pulling the distributors as well
In January-March, semiconductor distribution in Europe grew by as much as 10.5 per cent year-on-year. According to the Distributors ‘and Manufacturers’ Association of Semiconductor Specialists, the distributors sold semiconductors in the first quarter of EUR 2.13 billion.
Growth brought especially memory circuits, analogue and logic circuits. Memory growth is big, as the average prices for both DRAM and flash circuits have risen for a long time. This is reflected in the growth of total trade.
In the Nordic countries, the trend was clearly a plus sign. Sales of $ 178 million meant an 8.6 percent increase in the year-on-year figures.
Source: http://etn.fi/index.php/13-news/6416-muistit-vetavat-nyt-jakelijoitakin
Tomi Engdahl says:
Increase yields with Jet Printing
http://electronicsmaker.com/increase-yields-with-jet-printing
Available at Gemini Tec.
Our stencil free operation eliminates cost and reduces manufacturing times.
Suited to the most complex of PCBA’s, Solder Jet Printing makes it possible reflow the most challenging of components, where traditional screen printers struggle.
Jet Printing places millions of perfectly shaped solder dots onto each pad on the PCB, to create the perfect solder deposit, time and time again, a dot of paste – for every pad on the PCB.
Gemini was the first UK CEM to adopt this process for all its customers.
Solder jet printing allows control far beyond traditional stencils, with each component having the right volume solder paste.
Stencil-free means a reduction in lead time, as we no longer need to engineer and purchase stencils. During the prototype phase, we can make edits to the paste programs within seconds, without the need to re-order any stencils.
Tomi Engdahl says:
Prices of Flash circuits rose by 25 percent
in January-March, manufacturers of NAND flashes were able to smile, as DramExchange rose by 20-25 percent from October to December.
For manufacturers, the situation is good in many ways. The average prices are rising, the demand for SSDs is growing steadily, and smart phones have a solid flash memory at a fast pace.
For example, the smartphone now has an average storage capacity of 42 gigabytes, while at the end of 2013, the average smartphone had an average NAND of 13.4 gigabytes.
Source: http://www.etn.fi/index.php/13-news/6418-flash-piirien-hinnat-nousivat-25-prosenttia
Tomi Engdahl says:
Graphene and Quantum Dots put in motion a CMOS-integrated camera that can see the invisible
https://www.icfo.eu/newsroom/news/3581-graphene-and-quantum-dots-put-in-motion-a-cmos-integrated-camera-that-can-see-the-invisible
ICFO develops the first graphene-quantum dot based CMOS integrated camera, capable of imaging visible and infrared light at the same time. Over the past 40 years, microelectronics has advanced by leaps and bounds thanks to silicon and CMOS (Complementary metal-oxide semiconductors) technology, making possible computing, smartphones, compact and low-cost digital cameras, as well as most of the electronic gadgets we rely on today. However, the diversification of this platform into applications other than microcircuits and visible light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS.
This obstacle has now been overcome. ICFO researchers have shown for the first time the monolithic integration of a CMOS integrated circuit with graphene, resulting in a high-resolution image sensor consisting of hundreds of thousands of photodetectors based on graphene and quantum dots (QD). They operated it as a digital camera that is highly sensitive to UV, visible and infrared light at the same time. This has never been achieved before with existing imaging sensors. In general, this demonstration of monolithic integration of graphene with CMOS enables a wide range of optoelectronic applications, such as low-power optical data communications and compact and ultra sensitive sensing systems.
“The development of this monolithic CMOS-based image sensor represents a milestone for low-cost, high-resolution broadband and hyperspectral imaging systems”
This research has been partially supported by the European Graphene Flagship, the European Research Council, the Government of Catalonia, Fundació Cellex and the Severo Ochoa Excellence program of the Government of Spain
Broadband image sensor array based on graphene–CMOS integration
http://www.nature.com/nphoton/journal/v11/n6/full/nphoton.2017.75.html
Tomi Engdahl says:
Sebastian Anthony / Ars Technica UK:
IBM unveils world’s first 5nm chip, claims 40% performance boost at the same power compared to today’s 10nm chips
IBM unveils world’s first 5nm chip
Built with a new type of gate-all-around transistor, plus extreme ultraviolet lithography.
https://arstechnica.co.uk/gadgets/2017/06/ibm-5nm-chip/
IBM, working with Samsung and GlobalFoundries, has unveiled the world’s first 5nm silicon chip. Beyond the usual power, performance, and density improvement from moving to smaller transistors, the 5nm IBM chip is notable for being one of the first to use horizontal gate-all-around (GAA) transistors, and the first real use of extreme ultraviolet (EUV) lithography.
GAAFETs are the next evolution of tri-gate finFETs: finFETs, which are currently used for most 22nm-and-below chip designs, will probably run out of steam at around 7nm; GAAFETs may go all the way down to 3nm, especially when combined with EUV. No one really knows what comes after 3nm.
2D, 3D, and back to 2D
For the longest time, transistors were mostly fabricated by depositing layers of different materials on top of each other. As these planar 2D transistors got shorter and shorter (i.e. more transistors in the same space), it became increasingly hard to make transistors that actually perform well (i.e. fast switching, low leakage, reliable). Eventually, the channel got so small that the handful of remaining silicon atoms just couldn’t ferry the electricity across the device quickly enough.
FinFETs solve this problem by moving into the third dimension: instead of the channel being a tiny little 2D patch of silicon, a 3D fin juts out from the substrate, allowing for a much larger volume of silicon. Transistors are still getting smaller, though, and the fins are getting thinner. Now chipmakers need to use another type of transistor that provides yet another stay of execution.
Enter GAAFETs, which are kind of 2D, but they build upon the expertise, machines, and techniques that were required for finFETs. There are a few ways of building GAAFETs, but in this case IBM/Samsung/GloFo are talking about horizontal devices. The easiest way to think of these lateral GAAFETs is to take a finFET and turn it through 90 degrees.
In the case of IBM’s GAAFET, there are actually three nanosheets stacked on top of each other running between the source and drain, with the gate (the bit that turns the channel on and off) filling in all the gaps.
Fabrication-wise, GAAFETs are particularly fascinating.
One major advantage of IBM’s 5nm GAAFETs is a significant reduction in patterning complexity. Ever since we crossed the 28nm node, chips have become increasingly expensive to manufacture, due to the added complexity of fabricating ever-smaller features at ever-increasing densities. Patterning is the multi-stage process where the layout of the chip—defining where the nanosheets and other components will eventually be built—is etched using a lithographic process. As features get smaller and more complex, more patterning stages are required, which drives up the cost and time of producing each wafer.
IBM Research’s silicon devices chief, Huiming Bu, says this 5nm chip is the first time that extreme ultraviolet (EUV) lithography has been used for front-end-of-line patterning. EUV has a much narrower wavelength (13.5nm) than current immersion lithography machines (193nm), which in turn can reduce the number of patterning stages.
Tomi Engdahl says:
Wall Street Journal:
A look at market cap changes among biggest chipmakers: Nvidia and Broadcom surge, Intel and Qualcomm decline, and TSMC surpasses Intel with highest valuation
How the Big Chip Rally Knocked Leaders Off Their Perches
Intel falls from No. 1, Qualcomm from No. 2, and upstarts can rally even more
https://www.wsj.com/articles/how-the-big-chip-rally-knocked-leaders-off-their-perches-1496584800?mod=rss_Technology&utm_source=dlvr.it&utm_medium=twitter
Tomi Engdahl says:
What’s Next In Scaling, Stacking
The 40nm gate-pitch cliff, 3D SoCs with microfluidic cooling, new fan-outs and 2.5D—it’s all on the table.
https://semiengineering.com/whats-next-in-scaling-and-stacking/
SE: Chipmakers are shipping 16nm/14nm processes with 10nm and 7nm technologies either ramping or just around the corner. These processes are based on finFET transistors, where the control of the current is accomplished by implementing a gate on each of the three sides of a fin. How long will the finFET last?
Steegen: From Imec’s perspective and the analysis that we’ve done, the finFET is a strong device. We see this one lasting. Let’s use gate pitch, because that is actually where you see a little bit of a cliff between a fin verses a nanowire. This is around 40nm. So, you could say if 5nm still parks itself in a 40nm gate pitch range, it’s there we believe that a finFET is still a very strong device.
SE: Is this the “foundry 5nm” node? (In the process technology world, the “foundry 5nm” or “industry 5nm” node is roughly equivalent to a full-scaled 7nm technology from IDMs like Intel and R&D organizations such as Imec. So, a “foundry 3nm” may resemble a full-scaled 5nm node from Intel and Imec.)
Steegen: Let’s set the record straight. When you are talking about 5nm, you are probably talking about the industry’s 5nm and not Imec’s. Internally, Imec has a node nomenclature. We have to set this straight, because Imec does full-node scaling.
Tomi Engdahl says:
What Are FeFETs?
How this new memory stacks up against existing non-volatile memory.
https://semiengineering.com/what-are-fefets/
The memory market is going in several different directions at once. On one front, the traditional memory types, such DRAM and flash, remain the workhorse technologies in systems despite undergoing some changes in the business. Then, several vendors are readying the next-generation memory types in the market.
As part of an ongoing series, Semiconductor Engineering will explore where the new and traditional memory technologies are heading. In this segment, Stefan Müller, chief executive of Ferroelectric Memory Co. (FMC), sat down with Semiconductor Engineering to discuss memory technology and other topics. Startup FMC is developing ferroelectric FETs (FeFETs), a new memory type. The technology can also be applied to logic.
Tomi Engdahl says:
IBM Claims 5nm Nanosheet Breakthrough
Get 2-to-3 Days Battery Live
http://www.eetimes.com/document.asp?doc_id=1331850&
IBM researchers and their partners have developed a new transistor architecture based on stacked silicon nanosheets that they believe will make FinFETs obsolete at the 5nm node.
The architecture, which was described Monday (June 5) at the 2017 Symposia on VLSI Technology and Circuits conference in Kyoto, Japan, is the culmination of 10 years of research on nanosheets by IBM, its Research Alliance partners GlobalFoundries and Samsung, and equipment suppliers. Compared to FinFETs, the new architecture consumes far less power, according to the researchers.
The Alliance breakthrough should enable battery powered devices like smartphones and other mobile devices to run for 2-to-3 days on a single charge, as well as boost performance of artificial intelligence (AI), virtual reality and even supercomputers, they say.
Less than two years after developing 7nm test chips with 20 billion transistors, the researchers say they have paved the way for 30 billion transistors on a fingernail-sized chip with quadruple all-around nanowire gates. Test results indicate a 40 percent boost in performance (at the same power as 7nm FinFETs) or up to a 75 percent savings in power compared with today’s advanced 10nm transistors.
According to IBM, the new 5nm breakthrough to more performance will boost its cognitive computing efforts as well as everybody’s efforts toward higher-throughput cloud computing and deep learning, along with lower power and longer battery life for all mobile Internet-of-Things (IoT) devices.
Tomi Engdahl says:
Apple, Amazon to Join Foxconn’s Toshiba Bid
http://www.eetimes.com/document.asp?doc_id=1331857&
Apple and Amazon will pony up to pay a portion of contract manufacturer Foxconn’s bid to acquire Toshiba’s semiconductor business as the consumer electronics powerhouses move to secure a steady supply of NAND flash memory, Foxconn’s cheif executive told the Nikkei news service.
Apple and Amazon are dependent on NAND flash memory for their consumer electronics offerings, including iPhone, iPad and the Alexa-powered Amazon Echo. Many of these products are built by Foxconn. Last week, market research firm DRAMeXchange reported that contract prices for NAND rose 20 to 25 percent in the first quarter, stabilizing the price of NAND in what is traditionally a slower time of year for memory chip sales.
Tomi Engdahl says:
NAND Shortage Drives Price Surge
http://www.eetimes.com/document.asp?doc_id=1331838&
Contract pricing for NAND flash memory surged by 20 to 25 percent in the first quarter, a strong testament to the undersupply condition that persists in the market, according to DRAMeXchange, a firm that tracks memory chip pricing.
Tomi Engdahl says:
Nvidia CEO Says Moore’s Law Is Dead
http://www.eetimes.com/document.asp?doc_id=1331836&
Nvidia CEO Jensen Huang has become the first head of a major semiconductor company to say what academics have been suggesting for some time: Moore’s Law is dead.
The enablers of an architectural advance every generation — increasing the size of pipelines, using superscalar tweaks and speculative execution — are among the techniques that are now lagging in the effort to keep pace with the expected 50 percent increase in transistor density each year, Huang told a gathering of reporters and analysts at the Computex show in Taipei.
“Microprocessors no longer scale at the level of performance they used to — the end of what you would call Moore’s Law,” Huang said. “Semiconductor physics prevents us from taking Dennard scaling any further.”
Dennard scaling, also known as MOSFET scaling, is based on a 1974 paper co-authored by Robert H. Dennard, after whom it is named. Originally formulated for MOSFETs, it states, roughly, that as transistors get smaller their power density stays constant, so that power use stays in proportion with area.
The diminishing returns from Moore’s Law and Dennard scaling have seen the semiconductor industry enter a mature stage in which just a handful of chipmakers can afford the multibillion dollar investments required to push the process technology forward. By now, only a few chip designers have the deep pockets to double down on fabricating silicon at the 16nm and 14nm nodes, design rules where the distinction has become increasingly blurred.
That stagnation in the progress of technology has also led to rapid industry consolidation in recent years that’s resulted in a flurry of multi-billion dollar mergers and acquisitions.
Even so, Huang suggested a modus vivendi for the semiconductor industry that plays into graphics processors, the products that Nvidia expects will enable continuing advances for years to come. Deep learning will use the processing power of GPUs that Nvidia makes as part of a new architecture that will take the company into artificial intelligence, outside the computer gaming business Nvidia has dominated, according to Huang.
Nvidia has highlighted its Volta GPU on 12nm at an 815mm die size, taking up the same surface area as 7 iPhone processors, and connected to 16GB of high bandwidth memory using Taiwan Semiconductor Manufacturing Co.’s (TSMC) silicon interposer technology. A configuration of eight of these chips in Nvidia’s DGX-1 deep learning / high performance computing machine sells for $149,000.
Tomi Engdahl says:
12 Views on the Future of Electronics
Neural processors overtake CPUs, GPUs
http://www.eetimes.com/document.asp?doc_id=1331771&
Speakers at the annual Imec Technology Forum set out a smorgasbord of ideas on the future of electronics in machine learning, medicine, and how tomorrow’s systems will communicate with each other and interact with users.
Kinam Kim (below), president of Samsung’s semiconductor business, helped kick off the event with a talk that reiterated the optimism of Imec’s chip researchers. He pointed to research suggested that silicon can scale to a 1.5-nm node and, with new materials, perhaps even beyond.
Kim predicted that the DRAM and NAND technologies that Samsung dominates will continue to evolve. But he suggested that neural-network processors will disrupt the CPU and GPU architectures of rivals Intel and Nvidia, pointing to the startup the Korean giant has invested in, Graphcore.
Tomi Engdahl says:
NI Week: Things That Educate, Sound, and Move
http://www.eetimes.com/document.asp?doc_id=1331824&
The annual NI Week user conference took place May 22 through 25 here.
Some of the items on display in the exhibit hall and at the keynote addresses educated students, advanced 5G, and produced control systems with precise timing.
Tools for engineering education
At the Academic Forum Partner Expo held on May 22, National Instruments and partner companies displayed their wares that help educators teach engineering principles.
Diligent, a National Instruments Company, uses a modular system called PMOD in which students can design measurement and control systems.
This component test bench connects to a National Instruments VirtualBench, letting students learn about active components such as transistors and ADCs.
Robotics tools use an NI MyRio for teaching about measurements and control.
NI Week 2017 showcased equipment, applications, and technical sessions relating to 5G. The keynote session on May 23 featured a channel-sounding system developed by AT&T.
Many NI Week attendees develop control systems for industrial and robotics applications. For 2017, NI Week featured a slot-car track in which bridges, gates, and windmills were controlled through a time-sensitive network (TSN). Using an industrial controller from Cisco, National Instruments CompactRIO, and sensors and actuators, the system knows the location of each car and reacts by closing draw bridges, opening gates, and rotating propellers just in time to avoid accidents.
Tomi Engdahl says:
The Benefits of HW/SW Co-Simulation for Zynq-Based Designs
https://www.eeweb.com/blog/adam_taylor_2/the-benefits-of-hw-sw-co-simulation-for-zynq-based-designs
Heterogeneous System-on-Chip (SoC) devices like the Xilinx Zynq 7000 and Zynq UltraScale+ MPSoC combine high-performance processing systems with state-of-the-art programmable logic. This combination allows the system to be architected to provide an optimal solution. User interfaces, communication, control, and system configuration can be addressed by the Processor System (PS). Meanwhile, the Programmable Logic (PL) can be used to implement low latency, deterministic functions and processing pipelines that exploit its parallel, nature such as those used by image processing and industrial applications.
Verifying interactions between the PS and PL presents challenges to the design team. The 2015 Embedded Markets Survey identified debugging as one of the major design challenges faced by engineering teams and also identified a need for improved debugging tools. While bus functional models can be used initially, these models are often simplified and do not enable verification of the developed SW drivers and application at the same time. Full functional models are available, but these can be prohibitively expensive. When implementing a heterogeneous SoC design, there needs to be a verification strategy that enables both PL and PS elements to be verified together at the earliest possible point.
Traditionally, verification has initially been performed for each element (functional block) in the design in isolation; verifying all the blocks together occurs when the first hardware arrives. The software engineering team developing the applications to run on the PS needs to ensure the Linux Kernel contains all the necessary modules to support its use and has the correct device tree blob; this is normally verified using QEMU (short for Quick Emulator), which is a free and open-source hosted hypervisor that performs hardware virtualization.
Meanwhile, in order to correctly verify the PL design, the logic verification team is required to generate and sequence commands like those issued by the application software to verify that the logic functions as required.
It is possible to use a development board as in interim step to verify the HW and SW interaction before the arrival of the final hardware. However, debug on real hardware can be complicated, requiring additional instrumentation logic to be inserted in the hardware. This insertion takes additional time as the bit file needs to be regenerated to include the instrumentation logic. Of course, this change in the implementation can also impact the underlying behavior of the design, thereby masking issues or introducing new issues that make themselves apparent only in the debugging builds.
Being able to verify both the SW and the HW designs using co-simulation, therefore, provides several significant benefits. It can be performed earlier in the development cycle and does not require waiting for development hardware to arrive, thereby reducing the cost and impacts of debugging.
HW & SW Co-simulation
Co-Simulation between SW and HW requires the logic simulation tool used to verify the HW design to be able to interact with an SW simulation emulation environment.
The release of Aldec’s Riviera-PRO (2017.10) enables just this HW and SW co-simulation by the provision of a bridge between Riviera-PRO and QEMU, thereby enabling the execution of the developed software for Linux-based Zynq developments.
This bridge has been created using SystemC Transaction Level Modelling (TLM) to define the communication channels between QEMU and Riviera-PRO. The concurrent verification of the SW and HW is facilitated by the bridge’s ability to transfer information in both directions.
Within this integrated simulation environment, the engineering team is able to use standard and advanced debug methodologies to address any issues that may arise as the verification proceeds. In the case of Riviera-PRO, this includes such capabilities as setting break points within the HDL, examining data flow, and even analyzing the code coverage and paths that are exercised by the SW application running in QEMU. In the case of QEMU, the SW team can use Gnu DeBugger (GDB) to instrument both the kernel and the driver to step through the code using breakpoints.
This co-simulation approach has the benefit of not only providing greater visibility and debugging capability within the hardware simulation environment, but it also enables the same Linux kernel developed for the target hardware to be used within QEMU.
Tomi Engdahl says:
GaN Technology: A Lean, Green (Power) Machine
http://www.electronicdesign.com/power/gan-technology-lean-green-power-machine?NL=ED-003&Issue=ED-003_20170607_ED-003_586&sfvc4enews=42&cl=article_1_b&utm_rid=CPG05000002750211&utm_campaign=11473&utm_medium=email&elq2=64ef08ebf1ad4a88a3bdd95cd10d92b0
Sponsored by: Texas Instruments. The devil is in the details when designing a Titanium-grade power supply with gallium-nitride technology, from driver circuits and new power design topologies to digital control schemes and new product qualification tests.
Electricity is the world’s fastest-growing form of end-use energy consumption. The U.S. Energy Information Administration (EIA) estimates that worldwide generating capacity will grow to 36.5 million megawatt-hours by 2040, a 69% increase from 2012, driven by rising incomes in China, India, and other emerging Asian economies. Electricity generation in the U.S. will grow 24% by 2040—about 1% annually.
Houston, we got a problem…. the EIA also estimates that some 6% of electricity generated in the U.S. goes to waste in supply and disposition—more than 14 million megawatt-hours annually at current rates of consumption. Reducing just a portion of this waste through efficiency improvements could make it possible to slow the growth of demand, and accelerate the closing of inefficient and polluting coal-fired power plants.
As a result, governments and regulatory agencies worldwide are moving to implement standards for energy efficiency.
The 80 Plus standards, now part of Energy Star in the U.S., cover computer power supplies.
the latest Titanium standard requires a maximum efficiency of up to 96% from ac input to dc output.
Meeting these new standards requires rethinking every building block in a power supply, and GaN technology is playing an increasing role.
Why GaN?
Gallium nitride (GaN) is a wide-bandgap (WBG) semiconductor with a bandgap of 3.4 electron-volts (eV) compared to silicon’s 1.1 eV. For power designs, the wider bandgap translates into several performance improvements for GaN compared to silicon
GaN Challenges
Hold on a second, though.
Benefitting from GaN’s superior performance requires more than simply swapping out existing silicon FETs for their GaN equivalents. The first GaN devices to appear operated in depletion mode—i.e., they were normally in the “on” state—whereas Si MOSFETs are normally off enhancement-mode devices.
To provide drop-in replacements for Si MOSFETs, GaN FET suppliers redesigned their products to operate in enhancement mode, typically by placing a low-voltage Si switch in series with the depletion-mode GaN to form a cascode configuration. A native enhancement-mode GaN device is possible, too, but driving it is more complicated because the GaN gate is resistive, voltage-sensitive, and requires a minimum current to remain on.
An SMPS power supply using GaN technology must change many building blocks to see the maximum performance improvement.
Replacing a Si MOSFET with a GaN FET forces other design changes, too. The driver circuit must be more precise to accommodate GaN’s higher switching speed. Also, the switches are highly sensitive to parasitic inductances from internal and external sources like traces, packages, and interconnects.
An examination of the two block diagrams reveals significant differences between the two designs.The Si-based design needs four stages to convert the 115- or 230-V ac input to the 1- or 1.8-V final dc voltage, while the GaN design lets the designer eliminate the intermediate dc-dc conversion stage. The three-stage design can reduce the component count by up to 50%.