Chip Market Brightens in 2017. The semiconductor industry may yet have been flat in 2016, but expects it is expected that the electronics industry rebounds in 2017, probably in the first half. Wall Streeter predicts return to 5% growth. Total IC business growth is expected to be around five percents for few years to come.There seems to several promises to this direction, especially in memory business. Chips Execs See Maturing Industry article says that pessimism about immediate revenue and R&D growth is a sign of a maturing industry.
Thanks to both rising prices and volume sales, the memory sector is expected to lead overall semiconductor sales growth. Sales of memory chips will increase 10% next year to a new record high of $85.3 billion, according to the latest report from IC Insights. NAND flash will grow almost as fast at 10% next year. The average annual growth rate for the memory market is forecast to be 7.3% from 2016-2021. Every year we need 5.6% more bits than previous year, and the unit prices are increasing on both DRAM and Flash.
There will be also other growth sectors. The data center will be the fastest growth segment next year, rising 10%, followed by automotive at 9% and communications at 7%. Consumer and industrial markets growing at about 4% in line with the overall industry. PCs will be the big drag on 2017, declining 2%.
China Dominates Planned Chip Fabs as more than 40% of front end semiconductor fabs scheduled to begin operation between 2017 and 2020 are in China, a clear indication that China’s long-stated ambition to build a significant domestic semiconductor industry is taking shape.
Trump Win Could Mean Big Questions for Manufacturing as while Trump vowed to keep American manufacturing jobs, he offered little in the way of stated policy other than the promise to punish companies that sent manufacturing job outside the US. Questions about trade also could directly affect US manufacturing. How that plays out is a big unknown.
Europe will try to advance chip manufacturing, but not much results in 2017 as currently there is almost no leading-edge digital chip manufacturing left in Europe as the local companies have embraced outsourcing of digital semiconductor manufacturing to foundries. The European Commission intends to reconvene a high-level group of European CEOs and executives to exchange views on Europe’s 10/100/20 nanoelectronics and chip manufacturing project and make adjustments as necessary for a wave of European Union investment supposedly starting in 2020. The two most advanced wafer fab locations left in Europe in terms of deep sub-micron miniaturization belong to Intel in Leixlip, Ireland and Globalfoundries in Dresden, Germany.
Smaller geometries are to be taken into use and researched in 2017. Several chipmakers ramp up their 10nm finFET processes, with 7nm just around the corner. As TSMC, GF/Samsung Battle at 7nm the net result is in the course of 18 months chip designers will see at least three variants of 7nm — separate immersion variants from TSMC and Globalfoundries and the EUV version from GF/Samsung. Intel has yet to detail its 7nm node.
At the same time R&D has begun for 5nm and beyond, but Uncertainty Grows For 5nm, 3nm as costs are skyrocketing. Both 5nm and 3nm present a multitude of unknowns and challenges. To put this in perspective, there are roughly two silicon atoms in 1nm of line width in a chip. Etching Technology Advances as atomic layer etch (ALE) moves to the forefront of chip-making technology—finally. TSMC recently announced plans to build a new fab in Taiwan at a cost of $15.7 billion targeted for TSMC’s 5nm and 3nm processes, which are due out in 2020 and 2022.
Moore’s Law continues to slow as process complexities and costs escalate at each node. Moore’s Law is dead, just not in the way everyone thinks. SiFive believes open source hardware is the way forward for the semiconductor industry. Technological advances keep allowing chips to scale, but the economics are another story – particularly for smaller companies that can’t afford chips in the volumes. The solution, according to San Francisco-based startup, SiFive, is open-source hardware, specifically an architecture developed by the company’s founders called RISC-V (pronounced “risk-five”). Done right SiFive, which was awarded Startup of the Year at the 2016 Creativity in Electronics (ACE) Awards, believes that RISC-V will do for the hardware industry what Linux has done for software. For example 5th RISC-V Workshop Points to Growing Interest in the RISC-V Platform.
Sensors are hot in 2017. These tiny, powerful solutions are creating the interface between the analog and the digital world. Data is everywhere, and sensors are at the very heart of that. While no one really knows what technology’s next “killer application” will be, we are confident that any killer app will rely on sensors.Appliance autonomy promises to make life simpler, but this field has still lots of to improve even after year 2017.
Interface ICs will continue to help simplify high-bandwidth designs while making them more robust and reliable. Application areas that will benefit include automotive, communications, and industrial. Both wired and wireless interface solutions have plenty of applications.
Analog’s status is rising as more sensors and actuators are added into electronic devices, pressure is growing to more seamlessly move data seamlessly back and forth between analog and digital circuitry. IoT pushes up demand for analog content and need for communication between these two worlds will continue to grow. Analog and digital always have fit rather uncomfortably together, and that discomfort has grown as SoCs are built using smaller feature sizes. The demand for analog silicon has always existed in the embedded space, but the advent of the Internet of Things (IoT) is increasing the demand for connected mixed-signal content. At 28nm and 16/14nm, standard “analog” IP includes a fair amount of digital content.
It seems that hardware designer is a disappearing resource and software is the king in 2017. It is becoming less and less relevant in what format the device is used in many applications. Card computers are standard products and are found in many different card formats that can be used in very many applications. Embedded development is changing to more and more coding. More software designers that understand some hardware are needed, but it is not easy to leap to move to the hardware to software.
The power electronics market is moving at very fast pace. Besides traditional industrial, renewable, and traction sectors, new applications such as energy-storage systems, micro-grids, and dc chargers are emerging. As the automotive world moves to electric vehicles, this creates challenges for IGBT and SiC-MOSFET ICs, and their associated gate drivers. New packages for high-voltage IGBTs and high-voltage SiC-MOSFETs are introduced.
More custom power distribution and higher voltages on data center computer systems in 2017. OpenRack and OpenCompute projects are increasing the distribution voltage inside the server itself. This approach, plus transitioning to new materials such as gallium nitride in the power-conversion systems, can reduce overall power consumption by 20% and increase server densities by 30-40%.”
Power Modules and Reference Designs will be looked at in 2017 even more than earlier in power electronics. The semiconductor and packaging technologies used in power modules have advanced considerably, and the industry is developing modules today that are denser, less expensive, and easier to use. Designers want to rely on power modules to speed up designs and optimize space using smaller, easy-to-use power modules. Module manufacturers hope that engineers will increasingly choose a module over a discrete design in many applications.
The bi-directional DC/DC converter has been around for a while, but new applications are quickly emerging which necessitate the use of this architecture in so many more systems. Battery back-up systems need bi-directional DC/DC converters. Applications today require better energy efficiency and such systems as green power with solar or wind generation, need storage so that when there is no wind or sun available the electricity flow is not interrupted.
Power supplies need to become more efficient. Both European Union’s (EU) Code of Conduct (CoC) Tier 1 and CoC Tier 2 efficiency standards are to be taken into use. The European Union’s CoC Tier 1 effectively harmonizes the EU with US DoE Level VI and became effective as a voluntary requirement from January 2014, two years ahead of Level VI. Its adoption as an EU Ecodesign rule is currently under review to become law with an implementation date of January 2017. The key difference between the CoC requirements and Level VI is the new 10% load measure, which imposes efficiency requirements under a low-load condition where historically most types of power supplies have been notoriously inefficient. CoC Tier 2 further tightens the no-load and active mode power consumption limits.
During 2016, wireless-power applications started to pick up across many fields in the semiconductor industry, and it will continue to do so. Wireless power will continue to gain traction with increased consumer demand. Hewlett Packard, Dell, jjPlus, and Witricity have already announced products based on Airfuel standards. And, products based upon the Qi standard will continue to grow at a rapid pace.
Other prediction articles:
In Power & Analog 2017 Forecast: What Experts Are Saying article representatives from major players in the semiconductor industry share their predictions for 2017 regarding power modules, wireless power, data converters, wireless sensing, and more.
Looking Ahead to 2017 article tells on to what SIA is focused on working with. “U.S. semiconductor technology should be viewed as a strategic national asset, and the Administration should take a holistic approach in adopting policies to strengthen this vital sector,” the letter says
Hot technologies: Looking ahead to 2017 article collection has EDN and EE Times editors explore some of the hot technologies in 2017 that will shape next year’s technology trends and beyond.
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Tomi Engdahl says:
Tektronix Unveils Powerful New Oscilloscope Family
High channel counts and reconfigurability could appeal to a growing swath of embedded designers.
https://www.designnews.com/electronics-test/tektronix-unveils-powerful-new-oscilloscope-family/129378197056936?cid=nl.x.dn14.edt.aud.dn.20170607.tst004t
The 5 Series MSO mixed signal oscilloscope is said to offer a series of firsts, including a 4-, 6- and 8-channel product family, reconfigurable scope inputs, a 15.6-inch HD display with capacitive touch and an optional Windows operating system.
“This is not just any new platform, it’s the largest development effort in our company’s history,” Gary Waldo, product planner for Tektronix, told Design News. “Literally every single aspect of this product is new.”
The product family includes the MSO54, MSO56, and MSO58 models, which incorporate four, six, and eight analog channels, respectively. The reconfigurability feature enables the product to offer between eight and 64 digital channels, as well. Bandwidth on the various versions ranges from 350 MHz to 2 GHz.
One of the keys to the new product is Tektronix’s development of a specialized ASIC that integrates much of the conventional scope circuitry into a single chip.
Prices for the new scopes range from $12,600 to $40,600, depending on the number of channels and the bandwidth.
Tomi Engdahl says:
Q&A with Kris Myny, Principal Member of Technical Staff at imec
In this interview, Kris Myny discusses how imec technology, such as metal-oxide thin-film transistors, has the potential to impact everyday products and services.
http://www.mwrf.com/components/qa-kris-myny-principal-member-technical-staff-imec?NL=MWRF-001&Issue=MWRF-001_20170606_MWRF-001_90&sfvc4enews=42&cl=article_1_b&utm_rid=CPG05000002750211&utm_campaign=11446&utm_medium=email&elq2=18bfb588024f444bb09ff704bff1a441
Tomi Engdahl says:
IBM Optics Go CMOS
Low-Cost Photonics Goal
http://www.eetimes.com/document.asp?doc_id=1331851&
Researchers from IBM this week are describing a breakthrough in 60-gigabit-per-second (Gb/s) optical interconnect that the company claims will lead to broad replacement of costlier 56 Gb/s copper interconnects.
At the 2017 Symposia on VLSI Technology and Circuits, in Kyoto, Japan, scientists from IBM Research in Zurich will describe an inexpensive 60 Gb/s optical receiver that is expected to be followed next year by a matching optical transmitter. Together, the two devices will form a complete optical-transceiver built in CMOS at costs that the company expects to be lower than the costs of a copper interconnect.
“We are developing a single lane 60-Gigabit per second optical receiver with non-return to zero (NRZ) signaling targeting low cost multi-mode vertical-cavity surface-emitting laser (VCSEL) based links,” Alessandro Cevrero, an engineer at IBM, told EE Times in advance of the symposium.
“The power is way lower than our competitors, ~120mW for the receiver and eventually below 300mW for the full transceiver,” Cevrero said. “Also, its compact CMOS footprint and low power consumption means it can be moved closer to the processor or switch chip and eventually even be put in the same package or even on processor chip die, providing high bandwidth connectivity directly from the processor or switch chip spanning up to 100-meters. This covers links from processor-to-processor, processor-to-memory, from drawer-to-drawer inside a rack and from a rack to a tier-1 Internet switch.”
“Some people believed that a SiGe solution was required to achieve good optical sensitivity at data rates above 32Gb/s,” Cevero said. “Our work demonstrates that CMOS can achieve the same sensitivity, but at much lower power consumption.”
The 60 Gb/s optical link IBM demonstrated still depends on discrete III-V photodetectors (for the receiver) and discrete III-V lasers (for the transmitter) together forming a transceiver that is otherwise all-CMOS. Others, such as Intel (which offers a 25-Gigabit per second optical transceiver), use silicon photonics to modulate the light from a III-V lasers. Intel combines four such channels to achieve 100-Gbits per second today, but at much higher cost and power consumption, according to IBM. Intel, however, is shooting for the same goal as IBM by 2020.
IBM’s current prototype runs at a wavelength of 850 nanometers, which is the standard wavelength for VCSEL-based multi-mode optical links, making it suitable for processor-to-memory, processor-to-processor and server-to-server communications. Once the complete transceiver is demonstrated later this year or early 2018, the price crossover point will have been reached,
“So far, optical links were always pushed out due to their higher costs, but now we have reached the point where optics are at the same price as electrical links,”
Electrical links, however, need complex equalization when we go to higher data rates, and hence require more power. Also, their distance is limited to about two meters of cable compared to 100 meters for our optical solution.”
Toifl also claimed IBM’s “breakthrough” CMOS photonics technology provides superior sensitivity ( -9dBm) and is ideal for the high throughput requirements of cloud computing.
Tomi Engdahl says:
IBM Breakthrough: Optical Connections to Data Centers
IBM says it has achieved in its research laboratory 14-nanometer CMOS process optical switches that reach 60 gigabit switching speed per second. In the company’s vision, the optical interface replaces the electronic data center between the server rack and the switch.
When the data center replaces interfaces with electronic optics, it significantly adds more bandwidth, but the linkage power consumption is also clearly reduced.
IBM is already working on more than 70 gigabit optical connectors in the CMOS process.
Source: http://www.etn.fi/index.php/13-news/6437-ibm-n-lapimurto-optiset-liitannat-datakeskuksiin
More:
IBM scientists achieve 60 Gb/s with optical receiver in in 14nm CMOS FinFET
https://www.youtube.com/watch?v=ZAQVge2T5tw&feature=youtu.be
This work reports a low power implementation of a 60Gb/s NRZ optical receiver (RX) in 14nm bulk CMOS finFET featuring a first-order digital CDR with high jitter tolerance (JTOL).
Tomi Engdahl says:
China May Become No. 2 Fab Spender by 2018
http://www.eetimes.com/document.asp?doc_id=1331863&
China is expected to become the world’s second-largest spender on chip equipment by 2018 as a number of startups in the nation start ramping up new fabs.
China will increase overall fab spending, including construction and equipment, by 54 percent annually as the nation’s spending rises from $3.5 billion in 2016 to $5.4 billion in 2017, according to global chip equipment industry association SEMI. By 2018, the figure will jump to $8.6 billion in 2018, according to SEMI.
The bullish forecast comes as market research firm Gartner Inc. said it expects semiconductor industry sales to grow 12.3 percent this year, reaching $386 billion. Gartner said favorable market conditions that gained momentum in the second half of 2016 have raised the outlook for the chip market in both 2017 and 2018.
Tomi Engdahl says:
Expectations Rise as Chip Sales Keep Climbing
http://www.eetimes.com/document.asp?doc_id=1331866&
Forecasts for semiconductor industry growth keep climbing as the memory chip market booms and expectations for the remainder of the year rise.
The World Semiconductor Trade Statistics (WSTS) organization Tuesday (June 6) increased its forecast for the year, saying it now expects chip sales to grow 11.5 percent to reach $378 billion. This would represent the highest annual growth for the semiconductor industry since 2010.
WSTS, an organization of chip vendors that tracks sales data from more than 45 members, had previously said it expected chip sales to increase by 6.5 percent this year.
Tomi Engdahl says:
Chip Test Shifts Left
https://semiengineering.com/chip-test-shifts-left/
Semiconductor testing moves earlier in the process as quality and reliability become increasingly important.
Tomi Engdahl says:
Designing fast, isolated microamp current sources: Part 1
http://www.edn.com/design/analog/4458406/Designing-fast–isolated-microamp-current-sources–Part-1
In order to test and characterize optical front end circuits, a controllable, high bandwidth, microamp-level current source is needed. However, most optocouplers on the market have large CTR variation, making them unsuitable. Using transistors to build current sources is one of the options. However, they can’t provide a floating output like photodiodes.
One solution to this problem is the HCNR200/201 high-linearity optocoupler from Broadcom (previously Avago Technologies). Unlike most optocouplers, the HCNR200/201 exhibits high linearity and stable gain characteristics, which makes it an excellent solution for floating current source design. Similar optocouplers are available from other manufacturers.
https://www.broadcom.com/products/optocouplers/industrial-plastic/specific-function/high-linearity-analog/hcnr200
Tomi Engdahl says:
New Heat-Spreading Diamond for Radio Frequency Applications
http://www.mwrf.com/materials/new-heat-spreading-diamond-radio-frequency-applications?NL=MWRF-001&Issue=MWRF-001_20170608_MWRF-001_273&sfvc4enews=42&cl=article_1_b&utm_rid=CPG05000002750211&utm_campaign=11499&utm_medium=email&elq2=04d42462fd4c42f2bed500e317529dc4
A lesser known characteristic of diamond is that it absorbs heat more readily than any other material at room temperature. A subsidiary of the diamond giant De Beers aims to exploit that ability for whisking away heat from electronics.
The company, Element Six, released last week its latest grade of synthetic diamond for thermal management applications. The new product exhibits a thermal conductivity up to 700 W/mK, three times more effective at spreading heat equally from hot spots in RF power amplifiers and other electronics than alternative ceramic products.
Thomas Obeloer, business development manager at Element Six, said in a statement that Diafilm ETC700 delivered high thermal conductivity “far surpassing the performance of competing materials such as copper or ceramics.” It is the lowest of six grades in the company’s Diafilm product line, which range up to 2000 W/mK.
The new Diafilm product exhibits a large “conduction cross-section” that enables better RF performance by improving the ground-plane isolation. Its high bulk thermal conductivity “reduces capacitive coupling between ground planes at low frequencies, and reduces conductive losses at higher frequencies,” Element Six said in a statement.
Tomi Engdahl says:
DARPA Funds Development of New Type of Processor
Worlds 1st Non-Von-Neumann
http://www.eetimes.com/document.asp?doc_id=1331871&
A completely new kind of non-von-Neumann processor called a HIVE — Hierarchical Identify Verify Exploit — is being funded by the Defense Advanced Research Project Agency (DARPA) to the tune of $80 million over four-and-a-half years. Chipmakers Intel and Qualcomm are participating in the project, along with a national laboratory, a university and a defense contractor North Grumman.
“When we look at computer architectures today, they use the same [John] von Neumann architecture invented in the 1940s. CPUs and GPUs have gone parallel, but each core is still a von Neumann processor,” Trung Tran, a program manager in DARPA’s Microsystems Technology Office (MTO), told EE Times in an exclusive interview.
“HIVE is not von Neumann because of the sparseness of its data and its ability to simultaneously perform different processes on different areas of memory simultaneously,” Trung said. “This non-von-Neumann approach allows one big map that can be accessed by many processors at the same time, each using its own local scratch-pad memory while simultaneously performing scatter-and-gather operations across global memory.”
Graph analytic processors do not exist today, but they theoretically differ from CPUs and GPUs in key ways. First of all, they are optimized for processing sparse graph primitives. Because the items they process are sparsely located in global memory, they also involve a new memory architecture that can access randomly placed memory locations at ultra-high speeds (up to terabytes per second).
Today’s memory chips are optimized to access long sequential locations (to fill their caches) at their highest speeds, which are in the much slower gigabytes per second range. HIVEs, on the other hand, will access random eight-byte data points from global memory at its highest speed, then process them independently using their private scratch-pad memory. The architecture is also specified to be scalable to up to however many HIVE processors are needed to perform a specific graph algorithm.
The graph analytics processor is needed, according to DARPA, for Big Data problems, which typically involve many-to-many rather than many-to-one or one-to-one relationships for which today’s processors are optimized. A military example, according to DARPA, might be the the first digital missives of a cyberattack.
Besides the HIVE chip, the DARPA mandate calls for the development of software tools to help programming the new architecture, which goes beyond today’s parallel processing paradigm by also allowing simultaneous parallel access to random memory locations. If successful, DARPA claims that the graph analytics processor will be able to recognize and identify all types of situations that are intractable for conventional CPUs and GPUs.
Tomi Engdahl says:
Renesas Getting Healthy with Healthcare
Home-grown FD-SOI, wireless charging coming
http://www.eetimes.com/document.asp?doc_id=1331763&
Nobody would question Renesas Electronics’ MCU prowess in the automotive market. The Japanese chip company held the number three spot in the global automotive IC market in 2016, largely by leveraging the strength of its MCUs in cars.
But what does Renesas have up its sleeve in non-automotive segments?
He also discussed Renesas technologies devised for ultra-low energy IoT end-node devices.
These include Silicon-on-Thin-Box (SOTB), Renesas’ version of FD-SOI, and an internally developed wireless technology to charge a small lithium secondary battery used in healthcare, wearables and hearing aids.
Of course, this isn’t the first time Renesas has touted SOTB. But now, the Japanese company is confident that it can slash power consumption in its MCUs, reducing, for example, a 20 mW Synergy microcontroller to 2 mW. The goal is a quantum leap in battery life in IoT devices that could lead to a “battery-less” product when combined with energy harvesting, according to the company.
Tomi Engdahl says:
Transient Power Problems Rising
At 10/7nm, power management becomes much more difficult; old tricks don’t work.
https://semiengineering.com/transient-power-problems-rising/
Transient power is becoming much more problematic at 10/7nm, adding yet another level of complexity for design teams already wrestling with power issues caused by leakage, a variety of power management techniques to control dynamic power, and leakage current.
Tomi Engdahl says:
Hardware/Software Tipping Point
https://semiengineering.com/hardwaresoftware-tipping-point/
Has the tide turned from increasing amounts of general purpose, software defined products, to one where custom hardware will make a comeback?
It doesn’t matter if you believe Moore’s Law has ended or is just slowing down. It is becoming very clear that design in the future will be significant different than it is today.
Moore’s law allowed the semiconductor industry to reuse design blocks from previous designs, and these were helped along by a new technology node—even if it was a sub-optimal solution. It lowered risk and the technology node provided performance and power gains that enabled increasing amounts of integration.
Slow turn or landslide?
“More and more we are seeing people build things that have a more focused system model in mind,” says Drew Wingard, CTO at Sonics. “We see targeted chips that are doing just neural network inferencing, or at the edge we see IoT devices that may power a smart watch. These have a more constrained set of system requirements at least with respect to the non-CPU resources.”
But this is not likely to be a landslide. “We will not get as big gains for the new nodes compared to previous ones because we are not reducing the voltage as much,”
Legacy means that this transition will be like steering the Titanic. “A lot of SoCs are built to give the software an easier task,”
Most of the time, dark silicon is talked about as being a bad thing because it is an inefficient use of chip area and resources. But is it fair to assume that all parts of a chip should be used all of the time?
“The role of the operating system’s (OS) power management shifts a bit and then the OS responsibility becomes setting up the policy choices. Then you can move the actual management of the power states into hardware.”
Fundamentally there are two ways to control of power. “Software creates runtime variation in the thermal profile of chips,” says Oliver King, CTO for Moortec. “This makes it difficult to predict, at design time, the thermal issues unless the software is already well defined. There are a couple of approaches to this problem. The first is to have hardware which can sense and manage it’s own issues. The second is for software to take into account data from thermal and voltage sensors on die.”
Many in the industry are frustrated with how few of the power-saving features that have been designed into chips actually get used by software. “A lot of chips that have aggressive power management capability require so much firmware to be able to turn them on and off that they never get to use the features – they never have time to write this firmware,” adds Wingard.
Adding accelerators
The migration of software into hardware is usually accomplished with the addition of accelerators. These could be dedicated hardware, or more optimized programmable solutions that are tailored to specific tasks. These include DSP, neural networks and FPGA fabrics.
There are a number of different kinds of accelerators, each with its own set of attributes. But overall, the intent and utility of accelerators is the same. “It makes sense to deploy accelerators when the algorithms are well enough understood that you can make use of that hardware effectively,” points out Wingard. “Then we can do things with less energy.”
Sometimes, a standard becomes so important within the industry that custom hardware also becomes the right choice. An example of this is the H.264 video compression standard. “It would be foolish to do this with a programmable solution,” adds Desai.
It is also possible to generalize multiple standards into a class of operations and to create a partially optimized solution for them. “Audio and voice may be using 24-bit processing versus baseband, which may be doing complex math necessary for complex FFT and FIR,”
Then there is the emerging area of neural networks. “While neural networks are not standardized, you know from a high level that there are standard ways of doing things,” says Desai.
Wingard goes on to explain that “the inner loop of a neural network looks like a matrix multiply and a non-linear function that determines what I do with the result of that matrix multiply. At the lowest level it is very generic. If you go up one level, there is a network topology that is implemented.”
The world would be a lot simpler and more power efficient if there were not so many competing standards.
FPGAs have been used for a long time as co-processors but they require a coarse-grained approach to partitioning due to the high latency between the processor and the FPGA which resides in a separate chip. But that is changing.
“We have seen specific FPGA architectures that had arrays of ALUs – both academically and commercially—to do software offload,”
“FPGAs traditionally have been general-purpose, but embedded FPGAs can be used as accelerators for verticals like data center neural networks, automotive and edge networks,” said Steve Mensor, vice president of marketing at Achronix. “There is an ultra-short reach for connectivity and you can have a dedicated I/O.”
One of the advantages of including eFPGAs is that many of these markets are still nascent, so changes are likely over the life of a product because standards are still being defined.
What should be accelerated?
Deciding which software functions should be migrated into hardware or specialized processor is not an easy task. For one thing, the industry lacks the tools to make this easy. “You have to be able to measure it,” exclaims Amos. “Without this you cannot even measure how efficient the hardware/software combination is. What gets measured gets fixed.”
Amos explains that we need a new way to measure how this combination is performing in the real world. One option is to build the chip and measure it, but it would be much better to do this before the silicon has been fixed. “
“There are tools that look at hardware and can optimize it just by looking at it statically,”
Others are using FPGA prototypes to measure how efficient the software is so that decisions can get made. “We need a model with just enough accuracy to fool you into thinking you are running on silicon,”
Improving software
Even without hardware changes, there is a lot of gain that could be made just by updating the software. “Legacy can never be ignored,” Amos says. “There is a lot of software out there, and to go back to code that has been running for 10 years is unlikely.”
Amos also has a warning about getting too aggressive moving functionality into hardware. “We have had a migration from a community of hardware engineers when software was just emerging. Since then the universities are churning out software engineers, and there are not enough hardware engineers to make big changes. If we start moving software into hardware, who is going to do that?”
As with many things, economics will be the final decisionmaker. If something can be done more efficiently for the same or less dollars, then it will happen.
Tomi Engdahl says:
Safety Plus Security: A New Challenge
https://semiengineering.com/safety-plus-security-a-new-challenge/
First in a series: There is a price to pay for adding safety and security into a product, but how do you assess that and control it? The implications are far reaching, and not all techniques provide the same returns.
Nobody has ever integrated safety or security features into their design just because they felt like it. Usually, successive high-profile attacks are needed to even get an industry’s attention. And after that, it’s not always clear how to best implement solutions or what the tradeoffs are between cost, performance, and risk versus benefit.
Putting safety and security in the same basket is a new trend outside of mil/aero, and it adds both complexity and confusion into chip design. For one thing, these two areas are at different levels of maturity. Second, many companies believe they only have to deal with one or the other. But as the automotive industry has learned, security impacts safety and the two are tightly bound together. Interestingly, the German language uses the same word for both – sicherheit.
Incorporating safety and security into a product is not about a tool or an added piece of IP. It requires a change in workflows, which makes it a more difficult transition than just a new spec item or workflow step caused by the latest technology node. It also requires a mindset change in how to approach the design in the first place, because safety and security both need to be built into designs from the very outset.
“It is important for people to reorient their priorities and understand the tradeoffs,” states Rob Knoth, product management director for the DSG group at Cadence. “Even design schedule has to be considered. There may be a time-to-market window, and factoring in safety and security on top of an already challenging design schedule is difficult.”
Ignoring safety and security is no longer an issue for an increasing number of products. “As chips become more capable and are being used in more fully autonomous systems, it is increasingly important, and in many cases critical, that they correctly and rapidly analyze and react to the environment,
There are three classes of faults that have to be considered when looking at safety and security—random, systematic and malicious. Each of these requires a different approach, different kinds of analysis and each will result is different impacts on the product schedule and cost.
Random failures
Perhaps the easiest category to analyze is random failures, and there are an array of tools and techniques that can be used to guard against these in hardware.
The question is how to accomplish this. “To create an extremely safe system, one could simply duplicate or triplicate all the chips in the system, and even all the IP systems on each chip (we’ve seen this done in practice!),”
There are places where redundancy is necessary.
The challenge is knowing which parts of the hardware to concentrate on. “This could include redundant register files, added ECC protection in memory, redundant CPU core so that you can go lock-step,”
And there are hidden dangers. “It doesn’t take a genius to figure out that you need to be astute about what and how you use duplication,”
Shuler summarizes the techniques most commonly used. “Add redundant hardware blocks only where this has the greatest effect on functional safety diagnostic coverage, and only for IP that does not have other sufficient protection. To define safety goals and where to implement functional safety features requires thorough analysis of potential system failure modes, and then quantitatively proving whether safety mechanisms cover these faults.”
The right balance point also depends on the intended market. “For IoT and small devices, we can’t just build in lots of redundancy,” says OneSpin’s Darbari. “Half of the time you need these devices to be really small and have good power characteristics.”
In avionics, safety is assured by duplication, and it utilizes diverse design and architecture. This adds considerable design and verification expense and cannot be justified for most markets.
“Safety and security protection comes at a cost,” Shuler says. “If a system can’t meet near real-time latency requirements and huge processing throughput requirements, then people could be injured or killed. But if the system is too expensive to be developed and fielded economically, then perhaps the whole industry loses an opportunity to save human lives.”
Not all faults are visible during design at the RT level, and fault simulation is not capable of evaluating all of the faults at the system level.
Systemic failures
Finding systemic failures is the cornerstone challenge of modern verification, and is simply stated as how to determine the design does everything in the specification and meets all of the requirements. While the industry has a plethora of tools to address this challenge, it is one of the toughest challenges that the industry faces.
“How do we know we have done enough?” asks Darbari. “Coverage can direct you towards gaps, but you also need to consider completeness. Have all of the requirements been verified properly? Were there any over-constraints in the testbench, were there hidden bugs in the implementation?” These are the questions that keep verification engineers up at night.
Formal verification is one area that is seeing a lot of advances in recent years.
Verification a single simple concept. It is the comparison of two models, each developed independently, such that the probability of a common design error in both models is small. Those two models are most commonly defined as being the design and the testbench.
The industry is getting closer to that capability. “Sequential equivalence checking allows you to take two copies of the design and prove that they are functionally equivalent,”
Malicious faults
For random and systemic safety analysis, the industry has a track record and has built solutions that help make them tractable problems, but security is an evolving area. Security is significantly farther behind in terms of understanding the problem, building solutions, analyzing impact and measuring effectiveness.
Security is about protecting the system from malicious attacks and this goes beyond the notions of functional verification. Functional verification is about ensuring that intended functionalities work correctly. Security is about ensuring that there are no weaknesses that can be exploited to make the system perform unintended functionality. This is about handling the known unknowns and the unknown unknowns.
“There are some best practices in the industry but there is no good set of metrics for assessing how secure something is,” says Mike Borza, member of the technical staff for Synopsys’ Security IP. “People tend to make qualitative statements about it, and they also tend to use the best practices to evaluate the security of a device. You find things such as security audits that look to assess the common vulnerabilities that we know about, and what is being done to mitigate or eliminate those. Unfortunately, that is the state of the art.”
Tomi Engdahl says:
Foo Yun Chee / Reuters:
EU antitrust authorities have opened an investigation into Qualcomm’s proposed acquisition of NXP Semiconductors — EU antitrust authorities opened on Friday an investigation into U.S. smartphone chipmaker Qualcomm’s (QCOM.O) $38-billion bid for NXP Semiconductors (NXP.N) …
EU antitrust regulators to investigate $38 billion Qualcomm, NXP deal
http://www.reuters.com/article/us-nxp-m-a-qualcomm-eu-idUSKBN1902AK
Qualcomm, which supplies chips to Android smartphone makers and Apple (AAPL.P), is set to become the leading supplier to the fast growing automotive chip market following the deal, the largest-ever in the semiconductor industry.
The European Commission listed a raft of concerns about the combined company’s ability and incentives to squeeze out rivals and jack up prices.
Tomi Engdahl says:
The Week In Review: Manufacturing
https://semiengineering.com/the-week-in-review-manufacturing-165/
Market research
Earlier this year, the IC and equipment markets were projected to be flat. More recently, though, analysts have raised their forecast, including Pacific Crest Securities. “We are raising our 2017 capex outlook meaningfully, with the upside coming predominantly from Samsung,” said Weston Twigg, an analyst with Pacific Crest Securities, in a report. “We’re raising our 2017 semiconductor capex outlook to +18% from +10% and are establishing our 2018 outlook at +2%.
“We now model 2017 fab equipment spending at $40.3 billion. Samsung is the main driver, as we believe it has: (1) become more aggressive with its 3D NAND ramp at Pyeongtaek, (2) recently accelerated its 7nm foundry ramp, and (3) decided to move ahead with a planar NAND fab conversion to DRAM (line 16),” he said. “We project modest 2% growth in 2018, with memory capex up 2%, logic up 1%, and foundry up 5%, leading to fab equipment demand of roughly $41.1 billion.”
The latest update from SEMI’s World Fab Forecast report reveals record fab spending for 2017 and 2018. Korea, Taiwan and China will all see large fab investments. In 2017, over $49 billion will be spent on equipment alone, a record for the semiconductor industry, according to SEMI. Records will shatter again in 2018, when equipment spending will pass $54 billion, according to SEMI.
Tomi Engdahl says:
Linear – Fast high side protected n-channel MOSFET driver provides 100% duty cycle capability (LTC7000/-1)
http://www.electropages.com/2017/06/linear-fast-high-side-protected-n-channel-mosfet-driver-100-duty-cycle-capability/?utm_campaign=2017-06-12-Electropages&utm_source=newsletter&utm_medium=email&utm_term=article&utm_content=Linear+-+Fast+high+side+protected+n-channel+MOSFET+driver+provides+100%25+duty+…
Linear Technology’s LTC7000/-1 is a high speed, high side N-channel MOSFET driver that operates up to a 150V supply voltage. Its internal charge pump fully enhances an external N-channel MOSFET switch, allowing it to remain on indefinitely. The device’s powerful 1ohm gate driver can drive large gate capacitance MOSFETs with very short transition times, ideal for both high frequency switching and static switch applications.
The device operates over a 3.5V to 135V, 150VPK input supply range with a 3.5V to 15V bias voltage range. It detects an overcurrent condition by monitoring the voltage across an external sense resistor placed in series with the drain of the external MOSFET.
Tomi Engdahl says:
Mentor tries the low end, again, with PADS Maker
http://www.edn.com/electronics-products/electronic-product-reviews/other/4458447/Mentor-tries-the-low-end-again-with-PADS-Maker
For the second time in recent years, Mentor is taking a stab at entry-level PCB CAD.
In late 2014, EDN reported on a Mentor-DigiKey collaboration called Designer that was to bring lower-midrange capabilities to users for $600. It’s unclear how long this software remained active, but I can’t find any trace of it today.
Mentor has again teamed with DigiKey to release the $499 PADS MakerPro and the free PADS Maker. And good news for the abandoned Designer folks: these PADS systems will import your files.
Contrast and compare
Not surprisingly, the free version is fairly limited, though not as much as some other free CAD software. The largest board supported is 25 in2, 1,500 connections are allowed (unclear if that means nets or pins), and 6 layers (4 single layers max). What’s a “single layer” you ask? Could it be a “signal” layer? I’m already unimpressed by the documentation.
In true big-company fashion, a license key is still required, and it only lasts a year. I find that troubling. If Mentor drops support, your software will soon die. Unlike some other free ECAD software, designs remain private and local as opposed to being shared in the cloud.
The MakerPro version has no connection limit, a maximum PCB size of 50 in2, and handles up to 8 layers (6 single [sic]).
Unexpectedly, the Pro license is perpetual.
Tomi Engdahl says:
eTesters.com provides a searchable database of test and measurement equipment organized by topic and consisting solely of definitive manufacturer information.
https://etesters.com/
Tomi Engdahl says:
Emerging SD Card Uses Push Controller Development
http://www.eetimes.com/document.asp?doc_id=1331877
xternal media such as SD cards are not going away despite steady expansion of onboard storage capacity in smartphones, and controller companies are keeping up with emerging application areas by leveraging expertise in the SSD domain.
Silicon Motion Technology recently introduced what it said is the first merchant SD controller that supports the latest SD 6.0 specifications and meets the new A2 application performance rating with a minimum random read/write performance of 4,000/2,000 IOPS. The SD Specification 6.0 was announced earlier this year at the Mobile World Congress by the SD Association (SDA). It expands support for mobile devices with Application Performance Class 2 (A2) more than doubling random read and write speeds guaranteed in the entry level App Performance Class 1 (A1), which was announced late last year.
In a telephone interview with EE Times, Robert Fan U.S. general manager at Silicon Motion, said the company’s latest SD controllers demonstrate the evolution of the storage media as they must support bandwidth-intensive applications such as 4K video recording and playback and AR/VR, as well as better random read and write performance. Expandable memory cards with Silicon Motion’s new controller will also provide sufficient performance so users can run Android 6.x/7.x applications directly from their cards.
While there’s been plenty of speculation over the years that SD cards and other removable cards would fade away, Fan said the opposite is true, even as smartphones gain more onboard storage capacity. “The non-iPhone market has grown, especially in China,” Fan said.
Tomi Engdahl says:
EC Refs Whistle Qualcomm-NXP Deal
Qualcomm’s increased isolation in the world is palpable
http://www.eetimes.com/document.asp?doc_id=1331878
The European Commission Friday (June 9) threw down a gauntlet by officially opening an in-depth investigation into the proposed acquisition of NXP by Qualcomm.
The move is a monkey wrench in the two chip companies’ merger, adding at least four months to the resolution process. The Commission has “until 17 October 2017, to take a decision” on this matter, according the EC.
It’s uncertain to judge the impact on the eventual merger. Qualcomm and NXP had announced expectations to close the deal at the end of 2017.
Since last October, when the Qualcomm-NXP union was revealed, a lot has happened.
Tomi Engdahl says:
Mergers: Commission opens in-depth investigation into Qualcomm’s proposed acquisition of NXP
http://europa.eu/rapid/press-release_IP-17-1592_en.htm
The European Commission has opened an in-depth investigation to assess the proposed acquisition of NXP by Qualcomm under the EU Merger Regulation. The Commission has concerns that the transaction could lead to higher prices, less choice and reduced innovation in the semiconductor industry.
Tomi Engdahl says:
Cypress Chairman Resigns Amid Proxy War
http://www.eetimes.com/document.asp?doc_id=1331883&
Ray Bingham stepped down from Cypress Semiconductor Corp.’s board of directors Sunday (June 11) amid a messy proxy fight with the company’s founder and longtime CEO, T.J. Rodgers.
Tomi Engdahl says:
PCI Express Preps Shift to 32G
Acceleration comes amid fragmented efforts
http://www.eetimes.com/document.asp?doc_id=1331862&
Copper interconnects will get another big turn of the crank with a Gen 5 PCI Express delivering 32 GTransfers/s as early as 2019. The PCI Special Interest Group announced the plan at an annual gathering, where it is still putting finishing touches on its 16 GT/s Gen 4 spec.
The news marks a significant acceleration for the widely used computer interconnect, which had hit the pause button for several years as the PC market slowed. It comes at a time when a variety of open interconnects such as CCIX, GenZ, and OpenCAPI may fragment efforts in the space.
PCIe Gen 5 will use 128-/130-bit encoding to deliver up to 128 GBytes/s over 16 4-GB/s lanes. It is expected to provide links for high-end GPUs, machine-learning accelerators, and Ethernet and Infiniband cards running at 400 Gbits/s.
The 32G spec comes at a time when the rise of giant data centers has been driving serdes interconnects to rates up to 56 Gbits/second.
“I think that it will be 2019 before the center point of industry gets to Gen 4, but if [the PCI SIG] stays on its slope, we’ll get to a version 10 of Gen 5 by 2020,” he added.
Tomi Engdahl says:
March of the Touchless User Interfaces
http://www.eetimes.com/author.asp?section_id=36&doc_id=1331859&
The world of user interfaces is rapidly expanding. It’s no longer just touch but it includes a great variety of gestures and speech assistants. What can we expect from such advancements?
“Alexa, play the motion picture soundtrack to Moana.” Just two years after Amazon announced Amazon Echo, “Alexa” is part of the common lexicon. “Okay, Google,” “Siri” and “Hey, Cortana” have joined Alexa in the panoply of speech assistants as consumers migrate toward touchless user interfaces – which now include gesture as well as voice. What can we expect from these new user interfaces – and how will MEMS and sensors suppliers help us to get there?
First, let’s not disparage touch completely. It makes good sense for personal computing devices, among other keyboard-based applications, and will remain dominant for some time to come. Still, there are clear instances when voice is more convenient to use. And for me, my bellwether is always what my teenage girls are doing – typing/swiping or using voice.
Tomi Engdahl says:
OLEDs apps are making the OEM headlines
http://www.electropages.com/2017/06/oleds-apps-are-making-the-oem-headlines/?utm_campaign=&utm_source=newsletter&utm_medium=email&utm_term=article&utm_content=OLEDs+apps+are+making+the+OEM+headlines
Organic Light-Emitting Diode (OLED) displays are front-page news again following the industry rumour that Apple is considering the thin, lightweight screen technology for the forthcoming iPhone 8. It has also distinguished its MacBook Pro with an innovative OLED touch bar. In addition to this, Samsung, a major OLED maker, has featured curved OLED displays in several of its flagship phones and LG’s large OLED TVs are winning plaudits for their vibrancy and sharpness, despite high prices.
But OLED’s success has in some respects been a long time coming. Those with long memories might recall the first wave of OLED display fever 20 years ago when news reports extolled the benefits of the new technology: cheaper, brighter and lighter than LCD screens. What’s more, thin OLED displays could be flexible – soon we could roll up our mobile phones and TVs just like a newspaper. As usual, the reports were far ahead of reality. As every engineer knows, it’s one thing to make a research breakthrough in the lab, and quite another to scale up that discovery into mass production – but we are finally seeing OLED displays as a component that can be part of any project.
Tomi Engdahl says:
2.5D, ASICs Extend to 7nm
GlobalFoundries describes 7nm finFET details.
https://semiengineering.com/2-5d-asics-extend-7nm/
The leading-edge foundry market is heating up. For example, GlobalFoundries, Intel, Samsung and TSMC have recently announced their new and respective processes. The new processes from vendors range anywhere from 10nm to 4nm, although the current battle is taking place at 10nm and/or 7nm.
In fact, one vendor, GlobalFoundries, this week will describe more details about its previously-announced 7nm finFET technology. In addition, the company also announced a new 7nm ASIC offering and revealed its 5nm plans.
GlobalFoundries’ 7nm finFET process, dubbed 7nm Leading-Performance (7LP), is a scaled version of 14nm finFET technology. 7LP promises to deliver 40% more processing power and twice the area scaling than its 14nm finFET technology.
The initial production ramp of 7LP will be based on 193nm immersion and multi-patterning. The company will migrate to EUV lithography when the technology is ready for volume manufacturing.
GlobalFoundries’ 7LP technology is now ready for customer designs at the company’s 300mm fab in Saratoga County, N.Y.
Others also have big plans for 7nm. TSMC’s 7nm technology, dubbed N7, will enter risk production in the second quarter of this year, with volume production in 2018. Then, TSMC will roll out N7+, a process using EUV lithography. Shipments are due in 2019.
For its part, Samsung is developing 8nm, 7nm and 6nm processes. “
Intel plans to ship 10nm finFETs by year’s end. Intel argues that its 10nm process is equivalent to 7nm from the other foundries.
While companies are developing 10nm, 7nm and other variants, they are also working on 5nm. Recently, for example, IBM and its Research Alliance partners, GlobalFoundries and Samsung, revealed more details about the development of so-called nanosheet FETs for the 5nm node.
Samsung is developing nanosheet FETs for 4nm.
Tomi Engdahl says:
Forging a New Distribution Model for Innovators—from Hobbyists to Manufacturers
http://www.electronicdesign.com/industrial-automation/forging-new-distribution-model-innovators-hobbyists-manufacturers
As new types of customers enter the market, electronics equipment distributors are reaching a crossroads on how to meet demands in this fast-evolving industry.
By providing essential supplies and support, distributors of technology components and services are the engines that keep business moving for electronics innovators. However, in the past five years, these distributors have not only seen their customers’ needs change, but also experienced an expansion of their market to include new types of buyers. These two factors prompted a shift in buying behavior, which has ricocheted up and down the electronics-component supply chain.
Professional developers and designers are more dialed in than ever before and not afraid to shop around, while at the same time a new generation of makers and hobbyists are demanding more specialized parts and services. In such a competitive marketplace, distributors need to find new ways to serve customers that best suit their needs—a tall order in fast changing times.
A Changing Customer Landscape
Consumer demand for connected devices and miniaturized wearables has driven rapid growth in the Internet of Things (IoT) sector, with professional makers and hobbyists at the cutting edge of this burgeoning market. That’s because IoT is one of the most exciting and accessible opportunities for a broad range of solution designers, opening the possibility to bring profitable new products to the consumer market than ever before.
However, each IoT or wearable designer may approach the market with different needs. In addition to traditional market incumbents and smaller design houses with previous experience in bringing products to market, new customer groups—professional makers and entrepreneurial hobbyists—may be bringing a product to market for the first time.
Professional designers expect backing from their distributors for high-volume production, which requires careful management of inventory and obsolescence. This sets them apart from traditional hobbyists who find value in broader product lines and have a greater need for technical support. With so many opportunities in these new markets, distributors need to develop a new business model that anticipates the complexity of these differing customers’ needs, with the assurance that meeting these demands will have its rewards.
As developers and designers with differing levels of experience tackle new challenges such as IoT and wearables, they may be entering new markets and applying technologies in new ways. This may mean negotiating compliance challenges within heavily regulated industries such as healthcare and automotive, or developing a deeper knowledge of existing technology as it’s applied in different environments, such as in harsh climates or within flexible applications like clothing.
Traditionally, distributors provide competitive advantages by ensuring components are in stock in high volume and at a competitive price.
The growth of the professional maker and hobbyist sector puts traditional distributors in a bind. For these customer groups, technical support is the biggest area in which a distributor can provide added value. The IoT boom has meant that more makers and hobbyists, many of which may have limited production knowledge, are getting involved with development projects that demand greater levels of connectivity, flexibility, and customization.
Despite the number of plug-and-play modules now available, makers and hobbyists still require higher levels of technical and product support.
Nevertheless, serving the maker and hobbyist market is still demanding. These customers often favor a distributor that carries a broad number of lines, has items in stock, and offers excellent delivery options, technical support, and customer service.
It’s clear that today’s innovators, whether they are professional designers or hobbyists, need the best of both worlds: To work with companies at the scale, size, and global reach of a broad-line distributor, while still having access to the technical support and specialized capabilities to serve makers and hobbyists through all stages of the product lifecycle.
Tomi Engdahl says:
Q’comm Reportedly Taps TSMC’s 7nm
http://www.eetimes.com/document.asp?doc_id=1331893&
Qualcomm will switch back to TSMC to make its 7nm Snapdragon parts after giving its 10nm business to Samsung, according to a report in ET News, a South Korean publication. If correct, the switch will be a huge boost for TSMC and could cause a significant drop in Samsung’s foundry business in 2018.
Qualcomm declined to comment on what a spokeswoman characterized as rumors. Samsung and TSMC did not reply to requests for comment.
The report said Qualcomm started working on its 7nm Snapdragon SoC using TSMC tools in the middle of 2016. It is expected to announce the chip late this year or early next year “after first test wafer is manufactured from TSMC in September and after it is done with designing [its] package and verification process,” the report said.
Qualcomm announced its Snapdragon 835 made in Samsung’s 10nm process at CES in January. The article estimated the Snapdragon 835 business represents about $1.78 billion or 40 percent of Samsung’s foundry revenue.
The article suggested Qualcomm is making the switch for two reasons. Samsung is late with its 7nm node, and the Korean giant lacks the chip-stacking technology TSMC is using in Apple’s current iPhone 7 handset SoCs. TSMC released its first 7nm process design kit late last year while Samsung’s first beta 7nm PDK is due in July, it said.
Tomi Engdahl says:
Trump’s Budget Mixed Bag for Semiconductor Research
http://www.eetimes.com/author.asp?section_id=189&doc_id=1331889&
President Trump’s fiscal year 2018 budget proposal, released recently, contains both good and bad news for semiconductor research priorities.
President Trump’s fiscal year 2018 budget proposal, released recently, contains both good and bad news for semiconductor research priorities. On the positive side, the proposal includes more than $200 million for long-term semiconductor research through the Defense Advanced Research Projects Agency (DARPA), including a new $75 million semiconductor initiative to fund research to progress beyond traditional scaling and to address radically new microsystem materials, designs and architectures. The DARPA funding would be supplemented by significant industry investments.
Tomi Engdahl says:
G’foundries Updates 7nm, EUV Plan
http://www.eetimes.com/document.asp?doc_id=1331887
SAN JOSE, Calif. – Globalfoundries released more details of its 7nm process, claiming it exceeds targets although it is about six months behind its chief rival, TSMC. It also gave an update on its 7nm ASIC flow and plans to use extreme ultraviolet lithography for limited functions, probably in 2019.
GF’s 7LP process will initially use immersion steppers to pack more than 17 million gates/mm2. It reduces die cost by more than 30 percent based on more than a 50 percent shrink from its 14nm node based on fully laid-out chips. The large shrink is needed to compensate for the need to use triple patterning on some levels.
The node, first announced in September 2016, is now expected to offer more than a 40 percent boost in performance and support up to 17 metal layers. Design kits are available with first customer chips expected to launch in the first half of 2018 and hit volumes late next year.
“We’re open for business on 7nm,” said Gary Patton, GF’s chief technology officer.
Tomi Engdahl says:
Germanium Displacing GaAs for RF Transistors
Lowest ever source-drain contacts
http://www.eetimes.com/document.asp?doc_id=1331888&
Germanium is beginning to replace gallium arsenide (GaAs) for fast radio frequency transistors that are less expensive and also compatible with silicon and CMOS. At the 2017 Symposia on VLSI Technology and Circuits in Japan earlier this month, European research institute Imec presented a pair of papers showing gate-all-around (GAA) transistors that outperform standard CMOS below the 10-nanometer node plus have source/drain contacts with billionth-of-an-ohm resistance.
The super fast sub-10-nanometer SiGe GAA transistors used strained germanium p-channels on 300 millimeter wafers to demonstrate their superior electrostatic control, achieved by using high-pressure annealing (HPA), which was also demonstrated by Imec as useful for more traditional FinFET architectures.
Setting the new world record in source/drain resistivity at one billionth of an ohm for p-MOS transistor source/drain contacts, the feat was achieved by virtue of shallow gallium implantation and pulsed-laser annealing, according to Imec.
Tomi Engdahl says:
More Enlightenment on Optane
http://www.eetimes.com/author.asp?section_id=36&doc_id=1331894&
Digging deeper into a transmission electron microscope image of Intel’s Optane by TechInsights.
TechInsights has released some of the results of its analytical work on Intel’s Optane in the form of a TEM of Figure 1. It is from a detailed report TechInsights is preparing with the completed version soon to be available to the public.
Tomi Engdahl says:
Analyst Tempers IoT Chip Forecast
http://www.eetimes.com/author.asp?section_id=40&doc_id=1331895&
It’s still a huge market, but IC Insights sees slower revenue projections for government projections.
There’s little doubt that the Internet of Things represents a massive opportunity for the semiconductor industry, though quantifying the size of that opportunity remains at best a work in progress.
Market research firm IC Insights Inc. recently trimmed its long-term forecast for semiconductor sales driven by IoT, citing lower revenue projections for connected cities applications such as smart meters and infrastructure. The market research firm shaved nearly $1 billion off its 2020 IoT semiconductor forecast, saying it now it expects the total to be about $31.1 billion.
IC Insights still expects IoT chip sales to rise by 16 percent in 2017 to reach $18.3 billion. But the firm reduced its compound annual growth rate (CAGR) projection of IoT chip sales to 14.9 percent from 2015 to 2020, down from a previous CAGR estimate of 15.6 percent.
The firm still expects IoT chip sales for connected cities to post a CAGR of 8.9 percent between 2015 and 2020, but the estimate is down from an original forecast of 9.7 percent.
Tomi Engdahl says:
Janko Roettgers / Variety:
Sources: Google hires Manu Gulati, who led Apple’s chip development for almost eight years, as Lead SoC Architect
Google Hires Key Apple Chip Architect to Build Custom Chips for Pixel Phones (EXCLUSIVE)
http://variety.com/2017/digital/news/google-manu-gulati-pixel-chips-1202464014/
Tomi Engdahl says:
Affordable spintronics can replace silicon
The research team, headed by Christian Klinke from the University of Hamburg, has demonstrated special features in nanocrystalline nanocrystals. In circular polarized light on nanofibers of lead sulfide, the electrons can be guided and generated direct current.
Achievement leads to colloidal spintronics with Rashban spin-Orbit interaction. Spin-related electrical transport phenomenon in colloidal materials opens up a promising path towards future cheap spintronic structures. The effect found can be tuned on the electric field of the grille and the thickness of the sheet.
Researcher Erik Jonsson from the University of Texas has for its part designed a new kind of computer system that is made of carbon and may one day replace the current transistor.
A fully developed carbon-based spintronic switch acts as a logical gateway. It is based on the fundamental principle of electromagnetism. In traditional silicon-based computers, transistors can not take advantage of this phenomenon.
In the Friedman Spintronic Circuit Plan, electrons move through carbon nanotubes, creating magnetic fields that affect the flow of power in close graphene nanoplate. This gives you cascading logic gates that are not physically interconnected.
Since communication between graphene bands occurs electromagnetically instead of the physical movement of electrons, Friedman expects that communication is much faster, possibly at terahertz clock frequencies.
Source: http://www.etn.fi/index.php/13-news/6470-edullinen-spintroniikka-voi-korvata-piin
Tomi Engdahl says:
Modeling On-Chip Variation At 10/7nm
https://semiengineering.com/modeling-chip-variability-107nm/
Timing and variability have long been missing from automated transistor-level simulation tools. At advanced nodes, an update will be required.
Simulation, a workhorse tool for semiconductor design, is running out of steam at 10/7nm. It is falling behind on chips with huge gate counts and an enormous number of possible interactions between all the different functions that are being crammed onto a die.
At simulation’s root is some form of SPICE, which has served as its underpinnings ever since SPICE was first published 44 years ago. But simulation now is being stretched in many ways that were never considered when it was first introduced.
Consider, for example, modeling of on-chip variation. Even though statistical timing analysis tools might indicate that the paths are okay, for example, flop hold constraints may not model enough variation. Failure to accurately account for that variation can delay or even prevent timing closure.
Tomi Engdahl says:
G’foundries Updates 7nm, EUV Plan
http://www.eetimes.com/document.asp?doc_id=1331887
Globalfoundries released more details of its 7nm process, claiming it exceeds targets although it is about six months behind its chief rival, TSMC. It also gave an update on its 7nm ASIC flow and plans to use extreme ultraviolet lithography for limited functions, probably in 2019.
GF’s 7LP process will initially use immersion steppers to pack more than 17 million gates/mm2. It reduces die cost by more than 30 percent based on more than a 50 percent shrink from its 14nm node based on fully laid-out chips. The large shrink is needed to compensate for the need to use triple patterning on some levels.
Tomi Engdahl says:
Google Ramps Mobile SoC Team
http://www.eetimes.com/document.asp?doc_id=1331898&
Google is ramping up a team to build mobile SoCs for tablets and smartphones. The Web giant posted nearly 200 job openings in its hardware group including at least half a dozen specifically for mobile SoC designers.
Google launched its Pixel smartphones in October 2016 based on Qualcomm’s Snapdragon SoC. At that time, Google also hired David Foster, who formerly ran the Lab126 group that built Amazon’s Kindle and other devices. Foster attended the event where the company also debuted its Google Home speakers and other consumer systems.
Tomi Engdahl says:
Riding Mobileye Coattails, MIPS Juices CPU IP
http://www.eetimes.com/document.asp?doc_id=1331891&
MADISON, Wis. — Imagination Technologies revealed a key to its effort to make MIPS processing cores indispensable in automotive and industrial applications that require functional safety by rolling out Wednesday (June 13) a high-performance, multi-threaded MIPS CPU IP called MIPS I6500-F.
Despite Imagination’s recent decision to put the company’s MIPS business on the block as it fights for survival in the midst of a “dispute resolution procedure” with Apple, Imagination has not stalled its MIPS engineering goals. The mission of the I6500-F is to breathe new life into Imagination’s MIPS portfolio.
The team designed the I6500-F with a single purpose: Enabling a new generation of SoCs critical to more powerful, compute-intensive systems demanding functional safety.
MIPS revealed that the I6500-F is already at the heart of Mobileye (soon to become a part of Intel)’s upcoming EyeQ5 SoC, scheduled for sampling in 2018. With processing power of 12 Tera operations per second and power consumption below 5W, EyeQ5 will be one of the key SoCs powering the highly anticipated BMW/Intel/Mobileye’s autonomous car platform.
Tomi Engdahl says:
IMS 2017: 10 Things Not 5G
http://www.eetimes.com/document.asp?doc_id=1331872&
Tomi Engdahl says:
Q’comm Reportedly Taps TSMC’s 7nm
http://www.eetimes.com/document.asp?doc_id=1331893&
Qualcomm will switch back to TSMC to make its 7nm Snapdragon parts after giving its 10nm business to Samsung, according to a report in ET News, a South Korean publication. If correct, the switch will be a huge boost for TSMC and could cause a significant drop in Samsung’s foundry business in 2018.
Tomi Engdahl says:
Paris Accord: As U.S. Drops Out, Chipmakers Double Down
Industry sees bottom-line benefits of sustainability
http://www.eetimes.com/document.asp?doc_id=1331896
The semiconductor industry has responded to President Trump’s plan to pull the United States out of the Paris Climate Accord with resounding reaffirmations of the industry’s commitment to sustainable and energy-efficient manufacturing practices.
Semiconductor companies including AMD, IBM, and Intel, alongside other tech giants such as Apple, Google, and Microsoft, have signed an open letter expressing their commitment to action on climate change. For chip companies, adopting sustainable processes appears to be as much a matter of sound business practice as of social responsibility.
Tomi Engdahl says:
Gallery: Everything We Saw At IMS 2017
http://www.mwrf.com/components/gallery-everything-we-saw-ims-2017?NL=MWRF-001&Issue=MWRF-001_20170615_MWRF-001_825&sfvc4enews=42&cl=article_1_b&utm_rid=CPG05000002750211&utm_campaign=11614&utm_medium=email&elq2=09546ba8893d42fb9f0a813a7b6ac012
Last week, Microwaves & RF chronicled the the 2017 International Microwave Symposium in Hawaii, the annual powwow for companies and engineers in the high-frequency industry. Here are some views of the show floor, taken by our editors, where we got the inside track on the latest products and trends.
Tomi Engdahl says:
Inside FD-SOI And Scaling
GlobalFoundries’ CTO opens up on FD-SOI, 7nm finFETs, and what’s next in scaling.
https://semiengineering.com/inside-fd-soi-scaling/
SE: In logic, GlobalFoundries is shipping 14nm finFETs with 7nm in the works. The company is also readying 22nm FD-SOI technology with 12nm FD-SOI in R&D. Why develop both finFETs and FD-SOI?
SE: There is some confusion where FD-SOI and finFETs compete in the market. Can you elaborate?
Patton: I am a big fan of finFETs. I spend a lot of my time on 7nm. We are trying to get that ready for customer tape-outs early next year. It’s a great technology if you are focused on performance. If you are making large chips and you have a lot of wire capacitance, you love the drive current of a finFET device.
But if you are making smaller chips, where the gate capacitance is a bigger issue, then the finFET has a little bit of a disadvantage. Also, it’s a much more complex process. Not everybody is making a million wafers for their products. It’s a more expensive process. And it has more complexity with double-, triple- and quadruple- pattering, as well as the complexities with RF and analog design in a finFET device.
SE: What about FD-SOI?
Patton: FD-SOI is really a technology optimized for the low-cost IoT, battery-powered, low-end mobile and automotive applications.
SE: Do you push one technology over another?
Patton: We’re agnostic. We’re not telling customers that you have to do finFETs or FD-SOI. We want customers to use the technology that fits their application.
SE: Who are the early adopters for 22nm FD-SOI?
Patton: Automotive is definitely one of the strong ones. The camera space is another, and some of the battery-powered IoT.
Tomi Engdahl says:
Architecture First, Node Second
Even the biggest proponents of scaling have changed their tune.
https://semiengineering.com/architecture-first-node-second/
A couple of rather important changes have occurred in the move from 16/14 to 10/7nm (aside from more confusing naming conventions). First, companies that require more transistors—processor companies such as Intel, AMD, IBM and Qualcomm—have come to grips with the realization that they can pack more logic onto a die, but they can’t access those transistors as easily as in the past. And second, most have concluded that shrinking features alone is no longer good enough for achieving 35% or greater improvements in performance and/or power. So while the industry will continue shrinking down to 7 and 7+ (yet another confusing number), the real focus has shifted to the architecture.
That architecture is only partly about the on-chip logic, which is the data processing piece. The underlying shift involves changes in the flow of data. Systems are becoming more distributed—think about the sensors in a car, for example, or a cloud versus a classic data center—and processing of data needs to happen wherever it can be done fastest, cheapest, and using the least amount of power. That often isn’t a single-chip solution, in part because it takes power to move large amounts of data and in part because not all data types are the same. Video data is different than text, for example.
This is why there is so much attention being paid to interconnect standards such as Gen-Z, CCIX, OpenCAPI, and to new memory types (ReRAM, 3D Xpoint, phase-change), which can help reduce latency.
“With EUV coming, we’ll get to 7nm and 5nm,” Venu Venugopal, vice president of engineering in Cisco’s Core Software Group, said during a panel at this week’s GSA Silicon Summit 2017. “But architecture, by far, moves the needle the most.”
Tomi Engdahl says:
Hybrid Memory Cube Powers Galaxy Quest
http://www.eetimes.com/document.asp?doc_id=1331902
Radio astronomy is getting more data intensive, and Hybrid Memory Cube (HMC) is helping to process the large amounts of information being pulled from the sky.
Astronomy is one of the oldest observational sciences, said Simon Ratcliffe, technical lead for scientific computing for the Square Kilometre Array (SKA) in South Africa. It’s possible to see only 20,000 stars with the naked eye through an optical telescope. “It’s not a lot of data if you’re a scientist,” he said in a recent webinar. Radio astronomy, however, is turning into a data science.
Radio telescopes such as MeerKAT, under construction on the Northern Cape of South Africa, and the biggest and most sensitive in the southern hemisphere until SKA is completed in 2024, are quite data intensive. Ratcliffe said that even though only 16 out of 64 MeerKAT antennae are operational so far, it’s been able to detect 1,500 new galaxies in a relatively quiet corner of the universe that astronomers have never been able to see before.
As the antennae are moved further and further apart, he added, you gain resolution and see finer details.
The signal processing is where Micron’s HMC comes into play in the form of SKARAB, the digital processing platform for the MeerKAT telescope. It succeeds the ROACH-2 (Reconfigurable Open Architecture), and features 3,600 signal processing elements. The high performance HMC allows the engineers to match processing power to memory size and data bandwidth.
SKARAB improves on ROACH with upgraded interconnectivity from a data rate of 10Gbps to 40Gbps expected from each the MeerKAT antenna. Kapp said it wasn’t enough to simply add more memory. SKARAB boards are founded on field-programmable gate arrays (FPGAs), with new generations of SKARAB expected to become available every two to three years, matching the release of new FPGA chips. “FPGA is ideally suited for correlation,” he said. “The problem we need to solve was memory to match the processing depth and width. Depth is easy as the chips keeping getting bigger, but the width has not.” HMC’s serial interface combined with FPGA’s migration to serial interfaces, combined with the openHMC controller led to selection of HMC as the memory of choice for the SKARAB platform, Kapp added.
Tomi Engdahl says:
Western Digital Sues to Halt Toshiba Sale
http://www.eetimes.com/document.asp?doc_id=1331903&
Western Digital Corp. (WD) has asked a California court to halt the sale of Toshiba Corp.’s semiconductor business pending the results of arbitration between the two companies on the matter.
WD said Wednesday (June 14) that several of its SanDisk subsidiaries are seeking preliminary injunctive relief in Superior Court in San Francisco, arguing that ani-transfer provisions in the agreements between the two companies require that Toshiba obtain WD’s consent prior to any transfer of the memory chip joint ventures between the two companies.
Toshiba and Sandisk have been partners in NAND flash technology development and manufacturing since the late 1990s. WD acquired Sandisk for $19 billion last year.
Tomi Engdahl says:
MediaTek Chooses TSMC for 7nm
http://www.eetimes.com/document.asp?doc_id=1331904&
MediaTek, the second-largest designer of mobile phone chips after Qualcomm, says it has chosen Taiwan Semiconductor Manufacturing Co. (TSMC) to make 7nm products.
While it did not disclose a timeframe for the products, MediaTek said it is cooperating closely with its long-term fab partner at the new node.
“Low-power computing is the focus of TSMC and MediaTek,” said Rick Tsai, the new co-CEO of MediaTek, during an investor event at the company headquarters in the Hsinchu Science Park. “We hope TSMC’s leading-edge technology will help us create new business.”
Tsai, who was president and CEO at TSMC from 2005 to 2009, is switching roles from boss at the world’s biggest foundry to a key customer.
“TSMC has a very competitive node at 7nm,” Tsai said. “TSMC’s extreme ultraviolet (EUV) approach is good.”
MediaTek’s choice may be another sign that TSMC has gained an advantage over rival Samsung in the race to deliver 7nm silicon. MediaTek competitor Qualcomm appears to have also chosen TSMC for the 7nm version of its Snapdragon line of smartphone chips, according to media reports. Qualcomm was the first company to make 10nm chips, using Samsung as its foundry this year.
Tomi Engdahl says:
Cam Simpson / Bloomberg:
US semiconductor industry phased out chemicals discovered to be reproductive toxins in the 1990s but failed to ensure that their Asian suppliers did the same
American Chipmakers Had a Toxic Problem. Then They Outsourced It
https://www.bloomberg.com/news/features/2017-06-15/american-chipmakers-had-a-toxic-problem-so-they-outsourced-it
Twenty-five years ago, U.S. tech companies pledged to stop using chemicals that caused miscarriages and birth defects. They failed to ensure that their Asian suppliers did the same.
Results in epidemiology often are equivocal, and money can cloud science (see: tobacco companies vs. cancer researchers). Clear-cut cases are rare. Yet just such a case showed up one day in 1984 in the office of Harris Pastides, a recently appointed associate professor of epidemiology at the University of Massachusetts at Amherst.
Scientists from the University of California at Davis designed one of the biggest worker-health studies in history, involving 14 SIA companies, 42 plants, and 50,000 employees.
In epidemiology, follow-up studies usually get bigger and tougher, and for that reason they often contradict one another. But by December 1992, something rare had happened. All three studies—all paid for by the industry—showed similar results: roughly a doubling of the rate of miscarriages for thousands of potentially exposed women. This time the industry reacted quickly. SIA pointed to a family of toxic chemicals widely used in chipmaking as the likely cause and declared that its companies would accelerate efforts to phase them out. IBM went further: It pledged to rid its global chip production of them by 1995.
Pastides felt vindicated. More than that, he considered the entire episode one of the greatest successes in public-health history, as do others. Despite industry skepticism, three scientific studies led to changes that helped generations of women.
Two decades later, the ending to the story looks like a different kind of tale. As semiconductor production shifted to less expensive countries, the industry’s promised fixes do not appear to have made the same journey, at least not in full. Confidential data reviewed by Bloomberg Businessweek show that thousands of women and their unborn children continued to face potential exposure to the same toxins until at least 2015. Some are probably still being exposed today. Separate evidence shows the same reproductive-health effects also persisted across the decades.
The risks are exacerbated by secrecy—the industry may be using toxins that still haven’t been disclosed. This is the price paid by generations of women making the devices at the heart of the global economy.
a series of cancer cases in South Korea’s microelectronics industry drew her interest
Physics drives the design of microchips, but their production is mostly about chemistry. In a basic sense, chemicals and light combine to photographically print circuits onto silicon wafers. Gordon Moore, a founder of Intel and a major figure in the creation of the modern chip in 1960, is a chemist.
“There was just no knowledge of these things, and we were pouring stuff down into the city sewer system.”
As Kim learned in her scientific review, one critical chemical cocktail in the printing process is called a photoresist. It’s a light-sensitive compound that allows circuit patterns to be photographically printed on the chips.
The toxic ingredients were called ethylene glycol ethers, or EGEs. They also became key ingredients in solvent mixtures known as strippers, which are used to clean the chips during printing.
Yet in virtually every study published since the 1990s, Kim read one form or other of the same phrase: The global semiconductor industry had phased out EGEs in the mid-1990s, signaling the end of reproductive-health concerns. The statements made sense.
Not only had IBM and other companies publicly announced that the use of EGEs had been discontinued, but the chemicals also had become classified as Category 1 reproductive toxins under international standards, and European regulators had placed them on a list of the most highly toxic chemicals known to science, designating them Substances of Very High Concern.
After the outcry in the U.S. in the 1990s, chemical companies said they’d changed the formulations for the photoresists and other products they supplied to chipmakers, including those in Asia. But testing data obtained by Bloomberg Businessweek show that changes weren’t made quickly or, in some cases, completely.
Tests showed 2-ME in 6 of the 10 photoresist samples
The industry was in effect trading exposure in U.S. workers for exposure in women overseas