Chip Market Brightens in 2017. The semiconductor industry may yet have been flat in 2016, but expects it is expected that the electronics industry rebounds in 2017, probably in the first half. Wall Streeter predicts return to 5% growth. Total IC business growth is expected to be around five percents for few years to come.There seems to several promises to this direction, especially in memory business. Chips Execs See Maturing Industry article says that pessimism about immediate revenue and R&D growth is a sign of a maturing industry.
Thanks to both rising prices and volume sales, the memory sector is expected to lead overall semiconductor sales growth. Sales of memory chips will increase 10% next year to a new record high of $85.3 billion, according to the latest report from IC Insights. NAND flash will grow almost as fast at 10% next year. The average annual growth rate for the memory market is forecast to be 7.3% from 2016-2021. Every year we need 5.6% more bits than previous year, and the unit prices are increasing on both DRAM and Flash.
There will be also other growth sectors. The data center will be the fastest growth segment next year, rising 10%, followed by automotive at 9% and communications at 7%. Consumer and industrial markets growing at about 4% in line with the overall industry. PCs will be the big drag on 2017, declining 2%.
China Dominates Planned Chip Fabs as more than 40% of front end semiconductor fabs scheduled to begin operation between 2017 and 2020 are in China, a clear indication that China’s long-stated ambition to build a significant domestic semiconductor industry is taking shape.
Trump Win Could Mean Big Questions for Manufacturing as while Trump vowed to keep American manufacturing jobs, he offered little in the way of stated policy other than the promise to punish companies that sent manufacturing job outside the US. Questions about trade also could directly affect US manufacturing. How that plays out is a big unknown.
Europe will try to advance chip manufacturing, but not much results in 2017 as currently there is almost no leading-edge digital chip manufacturing left in Europe as the local companies have embraced outsourcing of digital semiconductor manufacturing to foundries. The European Commission intends to reconvene a high-level group of European CEOs and executives to exchange views on Europe’s 10/100/20 nanoelectronics and chip manufacturing project and make adjustments as necessary for a wave of European Union investment supposedly starting in 2020. The two most advanced wafer fab locations left in Europe in terms of deep sub-micron miniaturization belong to Intel in Leixlip, Ireland and Globalfoundries in Dresden, Germany.
Smaller geometries are to be taken into use and researched in 2017. Several chipmakers ramp up their 10nm finFET processes, with 7nm just around the corner. As TSMC, GF/Samsung Battle at 7nm the net result is in the course of 18 months chip designers will see at least three variants of 7nm — separate immersion variants from TSMC and Globalfoundries and the EUV version from GF/Samsung. Intel has yet to detail its 7nm node.
At the same time R&D has begun for 5nm and beyond, but Uncertainty Grows For 5nm, 3nm as costs are skyrocketing. Both 5nm and 3nm present a multitude of unknowns and challenges. To put this in perspective, there are roughly two silicon atoms in 1nm of line width in a chip. Etching Technology Advances as atomic layer etch (ALE) moves to the forefront of chip-making technology—finally. TSMC recently announced plans to build a new fab in Taiwan at a cost of $15.7 billion targeted for TSMC’s 5nm and 3nm processes, which are due out in 2020 and 2022.
Moore’s Law continues to slow as process complexities and costs escalate at each node. Moore’s Law is dead, just not in the way everyone thinks. SiFive believes open source hardware is the way forward for the semiconductor industry. Technological advances keep allowing chips to scale, but the economics are another story – particularly for smaller companies that can’t afford chips in the volumes. The solution, according to San Francisco-based startup, SiFive, is open-source hardware, specifically an architecture developed by the company’s founders called RISC-V (pronounced “risk-five”). Done right SiFive, which was awarded Startup of the Year at the 2016 Creativity in Electronics (ACE) Awards, believes that RISC-V will do for the hardware industry what Linux has done for software. For example 5th RISC-V Workshop Points to Growing Interest in the RISC-V Platform.
Sensors are hot in 2017. These tiny, powerful solutions are creating the interface between the analog and the digital world. Data is everywhere, and sensors are at the very heart of that. While no one really knows what technology’s next “killer application” will be, we are confident that any killer app will rely on sensors.Appliance autonomy promises to make life simpler, but this field has still lots of to improve even after year 2017.
Interface ICs will continue to help simplify high-bandwidth designs while making them more robust and reliable. Application areas that will benefit include automotive, communications, and industrial. Both wired and wireless interface solutions have plenty of applications.
Analog’s status is rising as more sensors and actuators are added into electronic devices, pressure is growing to more seamlessly move data seamlessly back and forth between analog and digital circuitry. IoT pushes up demand for analog content and need for communication between these two worlds will continue to grow. Analog and digital always have fit rather uncomfortably together, and that discomfort has grown as SoCs are built using smaller feature sizes. The demand for analog silicon has always existed in the embedded space, but the advent of the Internet of Things (IoT) is increasing the demand for connected mixed-signal content. At 28nm and 16/14nm, standard “analog” IP includes a fair amount of digital content.
It seems that hardware designer is a disappearing resource and software is the king in 2017. It is becoming less and less relevant in what format the device is used in many applications. Card computers are standard products and are found in many different card formats that can be used in very many applications. Embedded development is changing to more and more coding. More software designers that understand some hardware are needed, but it is not easy to leap to move to the hardware to software.
The power electronics market is moving at very fast pace. Besides traditional industrial, renewable, and traction sectors, new applications such as energy-storage systems, micro-grids, and dc chargers are emerging. As the automotive world moves to electric vehicles, this creates challenges for IGBT and SiC-MOSFET ICs, and their associated gate drivers. New packages for high-voltage IGBTs and high-voltage SiC-MOSFETs are introduced.
More custom power distribution and higher voltages on data center computer systems in 2017. OpenRack and OpenCompute projects are increasing the distribution voltage inside the server itself. This approach, plus transitioning to new materials such as gallium nitride in the power-conversion systems, can reduce overall power consumption by 20% and increase server densities by 30-40%.”
Power Modules and Reference Designs will be looked at in 2017 even more than earlier in power electronics. The semiconductor and packaging technologies used in power modules have advanced considerably, and the industry is developing modules today that are denser, less expensive, and easier to use. Designers want to rely on power modules to speed up designs and optimize space using smaller, easy-to-use power modules. Module manufacturers hope that engineers will increasingly choose a module over a discrete design in many applications.
The bi-directional DC/DC converter has been around for a while, but new applications are quickly emerging which necessitate the use of this architecture in so many more systems. Battery back-up systems need bi-directional DC/DC converters. Applications today require better energy efficiency and such systems as green power with solar or wind generation, need storage so that when there is no wind or sun available the electricity flow is not interrupted.
Power supplies need to become more efficient. Both European Union’s (EU) Code of Conduct (CoC) Tier 1 and CoC Tier 2 efficiency standards are to be taken into use. The European Union’s CoC Tier 1 effectively harmonizes the EU with US DoE Level VI and became effective as a voluntary requirement from January 2014, two years ahead of Level VI. Its adoption as an EU Ecodesign rule is currently under review to become law with an implementation date of January 2017. The key difference between the CoC requirements and Level VI is the new 10% load measure, which imposes efficiency requirements under a low-load condition where historically most types of power supplies have been notoriously inefficient. CoC Tier 2 further tightens the no-load and active mode power consumption limits.
During 2016, wireless-power applications started to pick up across many fields in the semiconductor industry, and it will continue to do so. Wireless power will continue to gain traction with increased consumer demand. Hewlett Packard, Dell, jjPlus, and Witricity have already announced products based on Airfuel standards. And, products based upon the Qi standard will continue to grow at a rapid pace.
Other prediction articles:
In Power & Analog 2017 Forecast: What Experts Are Saying article representatives from major players in the semiconductor industry share their predictions for 2017 regarding power modules, wireless power, data converters, wireless sensing, and more.
Looking Ahead to 2017 article tells on to what SIA is focused on working with. “U.S. semiconductor technology should be viewed as a strategic national asset, and the Administration should take a holistic approach in adopting policies to strengthen this vital sector,” the letter says
Hot technologies: Looking ahead to 2017 article collection has EDN and EE Times editors explore some of the hot technologies in 2017 that will shape next year’s technology trends and beyond.
1,115 Comments
Tomi Engdahl says:
Turning Signal Integrity Simulation Inside Out
Dr. Zoltan Cendes, one of the biggest names in electromagnetic simulation, says its time for design engineers to take a new approach.
https://www.designnews.com/content/turning-signal-integrity-simulation-inside-out/150286440947413?cid=nl.x.dn14.edt.aud.dn.20170202.tst004t
“My point is, electrical engineers change the world in ways you wouldn’t think.”
All that change however creates its own challenges. Industry leaders are demanding faster and more efficient processes. This in turn means design engineers need new applications and tools to meet these expectations and more intense schedules.
“Electromagnetic simulation has evolved to the point where we can turn it inside out by solving large EM problems with isolated nonlinear circuits,”
What Cendes is talking about is, rather than the traditional method of signal integrity simulation – solving circuits first, and worrying about the physics later – taking a new, physics-based approach that solves the electromagnetic physics first.
Cendes said this physics-based approach will ease a lot of simulation duties and also allow for easier automation of tasks. “Connecting things together is difficult manually, so you want to automate the workflow,” he said. “It allows you to do things more easily and also beyond that you don’t have to be an expert to run the simulation.”
Tomi Engdahl says:
With this engineers can conduct more virtual prototyping, which reduces hands-on engineering time, eliminate error-prone systems wiring, and allows steps to be scripted in software. “In the old days you’d have to label every trace and make sure you’re connecting everything correctly,” Cendes said. “Something like connecting 30 pins can take a long time. But the physics works very well. You can let the software figure it out.”
Source: https://www.designnews.com/content/turning-signal-integrity-simulation-inside-out/150286440947413?cid=nl.x.dn14.edt.aud.dn.20170202.tst004t
Tomi Engdahl says:
System-in-Package Gets 100G Link
EEs struggle to keep fast links on copper
http://www.eetimes.com/document.asp?doc_id=1331294
An emerging 100-Gbit/s standard aims to create a lower-cost alternative to 2.5D chip stacks. Proponents believe that the ultra-short-reach interface could help to spawn an ecosystem for a growing set of system-in-package (SiP) designs.
The effort is one of many trying to craft 100G links in part so next-generation systems in data centers can handle the deluge of mobile and internet traffic. Engineers aim to make changes in chips, boards, and systems to enable 100G on copper, staving off for another generation a move to more expensive optical links.
The Common Electrical Interface 112G for multichip modules is one of the shortest of all of the efforts. Yet it could pave the way for a new class of high-end chips that don’t depend on Moore’s law for performance gains.
Tomi Engdahl says:
Chip Group Sets 2017 Policies
SIA, Trump may clash on trade, immigration
http://www.eetimes.com/document.asp?doc_id=1331296&
The semiconductor industry’s trade group released its policy agenda for 2017 as the industry reported record sales for last year. Some of the policies are likely to clash with priorities of the Trump Administration, which has yet to state plans or make appointments specific to the tech sector.
The Semiconductor Industry Association (SIA) released an eight-point policy plan calling for lower taxes and expanded investments in chip-related research in universities and federal agencies. It also called for “balanced reforms to reduce abusive patent litigation and increased protection of trade secrets” and tougher enforcement to protect chip makers from counterfeiting.
Some measures in the plan may put the industry into conflict with President Trump’s stated views.
Tomi Engdahl says:
UMC to Start 14nm Shipments in Q1
http://www.eetimes.com/document.asp?doc_id=1331290&
-Taiwanese foundry United Microelectronics Corp. (UMC) plans to start shipments of its 14nm FinFET in the first quarter of 2017, according to the company’s CEO.
This represents a general acceleration of UMC’s plans to bring the manufacturing process to market. In April 2016, UMC was talking about commercial production in the second half of 2017. In October 2016, UMC reportedly discussed moving the process to volume production in 2Q17 with Bitcoin mining company BitFury set to be the first customer.
Tomi Engdahl says:
Chip Group Sets 2017 Policies
SIA, Trump may clash on trade, immigration
http://www.eetimes.com/document.asp?doc_id=1331296&
Looking ahead, analysts expect 2017 will be return to historic trends with growth at about five percent. “We expect modest growth to continue in 2017 and beyond,” said John Neuffer, chief executive of the SIA in a statement.
Tomi Engdahl says:
Ask Hackaday: Are Unlockable Features Good for the User?
http://hackaday.com/2017/02/02/ask-hackaday-are-unlockable-features-good-for-the-user/
There are numerous examples of hardware which has latent features waiting to be unlocked by software. Most recently, we saw a Casio calculator which has the same features as its bigger sibling hidden within the firmware, only to be exposed by a buffer overflow bug (or the lead from a pencil if you prefer a hardware hack).
More famously, oscilloscopes have been notorious for having crippled features. The Rigol DS1052E was hugely popular on hacker benches because of it’s very approachable price tag. The model shipped with 50 MHz bandwidth but it was discovered that a simple hack turned it into the DS1102E 100 MHz scope. Tektronix has gotten in on this action as well, shipping modules like I2C, CAN, and LIN analyzation on the scope but requiring a hardware key to unlock
Bottom Line and Getting Hardware to Those Who Need It
I’m going to call this the altruistic reason for this practice. Companies look for the biggest margin, and that is going to be high-end equipment where they can differentiate themselves from competitors and where businesses with purchasing power are the customer. The harware is recognized by those in industry as something they want to use.
The Effect of an Entry Level Model
There are several benefits to a lower-priced, entry-level model. Now, students, hobbyists, and the curious are able to get their hands on the hardware. From the company’s point of view this builds brand loyalty; the product works well and they like it. When these users get a larger budget (like getting hired as a hardware engineer) and want to upgrade they will think of this company first. The company also continues to sell the pro model at a higher price and make great margins while the companies still benefit from having great tools.
From the user point of view this unlocks faster prototyping, development, and troubleshooting.
It’s Like an App Store
If you are feeling slighted by having hardware that needs a software purchase to unlock its utility, I direct your attention to smartphones. You purchase the hardware (let’s sidestep the unrelated issue of carrier-subsidized phones) and it comes with basic functions even though it’s capable of much more. You extend the capability by purchasing apps which do more with the same hardware.
The Marketing Department Made Us Do It
One thing should be abundantly clear: hardware developers don’t want to follow several parallel designs through to production. But the marketing department will insist on having several options in the line. It’s part of a concept called market segmentation which seeks to tailor products to carefully selected groupings of customers.
Tomi Engdahl says:
You better layer up, Micron’s working on next-generation XPoint
New memory, quad-level cell flash, and increased layering
https://www.theregister.co.uk/2017/02/03/micron_working_on_nextgeneration_xpoint/
Micron is working on two next-generation XPoint products, a new memory, and extending 3D flash beyond 64 layers.
At an analysts’ day it talked about its 3D NAND technology development. It is shipping its gen-1 3D NAND with 32 layers and 384Gb die capacity and moving towards its second generation with 64 layers and 256Gb capacity in a 59mm2 die size. More than half its bit output in the second half of 2016 went into 3D NAND, which means planar, 2D NAND is now falling away.
It believes its way of doing 3D NAND, with a CMOS logic layer underneath the NAND cell layers makes its 32-layer technology competitive with 48-layer 3D NAND from other suppliers. This, we assume, means its 64-layer 3D NAND will be better (faster/cheaper/smaller?) than their competitors’.
Micron is starting to develop 64-layer die manufacturing with output shipping starting by the end of this year.
So you should be able to fit more of them in an SSD, PCIe or M.2 flash drive and have a higher capacity device. Storage BU chief Darren Thomas talked about 8TB 2.5-inch SSDs.
Interestingly, WD has claimed its BICS3 64-layer 3D NAND (256Gb capacity) has the smallest die size in the industry
Tomi Engdahl says:
Gartner has listed electronic component main buyers of last year. Samsung and Apple fighting over the number one spot in the flat, this time the Korean company rose by a small margin to first spot.
Samsung bought last year components of 31.7 billion dollars, or 9.3 percent of all purchased components. Apple’s figures were 29.9 billion and 8.8 per cent.
Source: http://www.etn.fi/index.php/13-news/5784-samsung-nousi-applen-ohi-ostajana
Tomi Engdahl says:
Q’comm-NXP Faces Trump, China Hurdles
http://www.eetimes.com/document.asp?doc_id=1331289
Qualcomm’s $39 billion acquisition of NXP, expected to close at the end of this year, could hit a snag, according to a recent report by the Capitol Forum.
The report sees problems — potentially a double whammy — for the pending deal. First, China’s MOFCOM (Ministry of Commerce), increasingly driven by industrial policy, could target the Qualcomm-NXP deal by demanding material divestitures as a condition of clearance. Second, CFIUS (Committee on Foreign Investment in the United States) could object to concessions Qualcomm and/or NXP might offer to MOFCOM — on the grounds that they are selling sensitive technologies to China.
In an interview with EE Times, lawyer Ashley Chang, the author of the Capitol Forum’s report, said her report does not conclude that MOFCOM would kill the deal. But MOFCOM could “throw a wrench” by prolonging merger review, she cautioned.
Tomi Engdahl says:
AI Tapped to Improve Design
Electronics center explores machine learning
http://www.eetimes.com/document.asp?doc_id=1331300
Nine companies and three universities have launched a research effort to see if machine learning can solve some of the toughest problems in electronics design. The center is one of many efforts across the industry trying to tap into the emerging technology.
Like many ideas in tech, “it all started in a coffee shop one afternoon,” said Elyse Rosenbaum, director of the Center for Advanced Electronics through Machine Learning (CAEML).
“We were facing common problems. We needed behavioral models that interfaced across electro-migration and circuit domains and didn’t know how to go about getting them, given that colleagues were interested in different applications,” Rosenbaum said in a panel on the topic at the DesignCon event here.
Tomi Engdahl says:
System-in-Package Gets 100G Link
EEs struggle to keep fast links on copper
http://www.eetimes.com/document.asp?doc_id=1331294
An emerging 100-Gbit/s standard aims to create a lower-cost alternative to 2.5D chip stacks. Proponents believe that the ultra-short-reach interface could help to spawn an ecosystem for a growing set of system-in-package (SiP) designs.
The effort is one of many trying to craft 100G links in part so next-generation systems in data centers can handle the deluge of mobile and internet traffic. Engineers aim to make changes in chips, boards, and systems to enable 100G on copper, staving off for another generation a move to more expensive optical links.
The Common Electrical Interface 112G for multichip modules is one of the shortest of all of the efforts.
Tomi Engdahl says:
Chip-Package-Board Issues Grow
http://semiengineering.com/chip-package-board-issues-grow/
Success will depend on new tools, a better understanding of who’s responsible, and new methodologies for getting designs out the door more quickly.
As systems migrate from a single die in a single package on a board, to multiple dies with multiple packaging options and multiple PCB form factors, it is becoming critical to move system planning, assembly, and optimization much earlier in the design-through-manufacturing flow.
This is easier said than done. Multiple tools and operating systems are now used at each phase of the flow, particularly for complex GPUs and CPUs for the latest handheld mobile devices. Trying to bridge these worlds to be able to analyze tradeoffs between various physical components, software and packaging options is difficult in a single-vendor environment.
“This is no easy task because it is essentially a serial process,”
The number of tradeoffs that needs to be considered up front is growing significantly.
Tomi Engdahl says:
Betting On Wafer-Level Fan-Outs
http://semiengineering.com/betting-on-fan-outs/
Chipmakers focus on packaging to reduce routing issues at 10nm, 7nm. Tool and methodology gaps remain.
Advanced packaging is starting to gain traction as a commercially viable business model rather than just one more possible option, propelled by the technical difficulties in routing signals at 10nm and 7nm and skyrocketing costs of device scaling on a single die.
The inclusion of a fan-out package for logic in Apple’s iPhone 7, based on TSMC’s Integrated Fan-Out (InFO) technology, has garnered most of the headlines in this space, but there is much more happening in this market. Even within the iPhone 7, there are 43 other wafer-level packages on the main PCB, plus wafer-level packages in the Lightning cable and earbuds, according to Jan Vardaman, president of TechSearch International. She noted that Hisilicon and MediaTek are expected to follow with their own application processor packaging. Others, such as Oppo and Vivo, China’s top two smart phone makers, already are using some version of advanced packaging, as well.
“There is a continued proliferation of packages,” Vardaman said. “The big discussion now is about heterogeneous integration. The problem is that phone boards are running out of space, so they need to come up with a way to minimize the package footprint.”
Tomi Engdahl says:
Optimizing Multi-Gigabit Serial Interfaces
http://electronicdesign.com/communications/optimizing-multi-gigabit-serial-interfaces?NL=ED-003&Issue=ED-003_20170206_ED-003_124&sfvc4enews=42&cl=article_1_b&utm_rid=CPG05000002750211&utm_campaign=9537&utm_medium=email&elq2=94219cbcb87144d08b09530c80f611d1
High-speed serial interfaces are the primary I/O architecture of most of today’s communications products. Virtually all electronic devices in use now incorporate fast serial data transfers. Examples include ASIC and FPGA connections on a printed-circuit board (PCB), board-to-board connections, or short cables. Multiple interface standards exist to carry such data.
PCIe is used in computers, SATA and SAS generally target storage products, and Ethernet is employed in networking. Other serial standards are used in telecom, medical, and consumer products. And gigabit data speeds are the norm. With serial rates up to 28 Gb/s and more, the design challenge is maintaining signal integrity over any distance. Careful design of the signal path and the inclusion of equalization have proven to produce the desired result.
Goals of Signal Integrity
The main design objectives of any serial link are a low bit error rate (BER), minimal jitter, and no inter-symbol interference (ISI). Typical BERs are in the 10-10 to 10-18 range. Jitter is the rapid time shift in the leading and trailing edges of a pulse. It’s similar to a low-deviation frequency modulation caused by clock instability, PLL variations, and noise.
A common measurement of good signal integrity is the eye diagram, which is an oscilloscope display of repeating and overlapping bit time periods (unit intervals or UIs) (Fig. 1). The rise and fall times define the pattern.
With fast rise and fall times, the “eye” becomes wide open
The typical signal path is a differential-pair transmission line. The transmission line is implemented as stripline, a pair of parallel copper traces on a printed-circuit board (PCB), or copper wires in a cable. The signal path also includes the connections to the ICs on the PCB and through connectors. Total signal path length varies from a few inches to several feet in most equipment.
The goal is to maintain a constant characteristic impedance throughout the path.
Green Box Testing
The key to optimum signal integrity and minimal BER is proper setting of the transmitter FIR coefficients. The TX doesn’t know the characteristics of the channel, so the settings will initially not be the best possible. These settings are an issue in any product using multi-gigabit serial links such as routers, switches, and security equipment.
The approach taken by Green Box (GB) testing is to sweep the coefficients over a range and make measurements to establish a pattern that will indicate when the channel is optimized. The outcome is a graphical plot of BER for each pair of TX coefficient settings. The outputs with no errors are colored green. Readings with errors but less than the RX can record are colored yellow, while maximum errors are recorded as red.
The basic test procedure is to connect the transmitter to a pseudorandom-binary-sequence (PRBS) generator set to a bit pattern typical of what’s mandated by the interface protocol.
Tomi Engdahl says:
TI Sees New Exponential Drivers
http://www.eetimes.com/author.asp?section_id=36&doc_id=1331315&
Tomorrow’s exponential growth in semiconductors will be fueled by a combination of specialized processes and design methodologies as transistor scaling becomes increasingly expensive, said the chef technologist of Texas Instruments.
The International Solid State Circuits Conference (ISSCC) has been a celebration of CMOS transistor scaling. But in his ISSCC plenary talk TI’s CTO, Ahmad Bahai, asked to take a different view. Rather than count the number of transistors we can render in deep submicron CMOS, he described a combination of factors including clever design as well as specialized packaging.
Shrinking CMOS geometries are essential for smaller appliances and longer battery life. But mobile handsets are no longer the only application offering exponential growth. The next 20 years will offer a broader variety of exponentials, enabled by specialized design, processes and manufacturing.
Tomi Engdahl says:
TSMC Calls for New EDA Paradigm
http://www.eetimes.com/document.asp?doc_id=1331312&
Engineers need a new class of tools to keep up with the complexity of designing today’s semiconductors, said a keynoter at the International Solid State Circuits Conference (ISSCC) here Monday (Feb. 6). Separate tools need to target today’s four major markets using new techniques and assumptions including machine learning, said Cliff Hou, vice president of R&D at TSMC.
“We need a new design paradigm to overcome chip design challenges,” said Hou. “It’s time for us to evolve our design paradigm, we’ve only covered a small portion of” the design space, he said.
Over the last 10 years the industry has been driven by mobile, building its design databases around smartphone SoCs. “Now we realize mobile is OK as a starting point but we also have to optimize circuits for automotive, high- performance systems and IoT where the considerations are very different,” Hou said, showing four different SRAM designs TSMC uses just for a range of mobile and wearable designs.
Tomi Engdahl says:
Western Digital Unveils First-Ever 512Gb 64-Layer 3D NAND Chip
https://hardware.slashdot.org/story/17/02/06/212219/western-digital-unveils-first-ever-512gb-64-layer-3d-nand-chip
As great as these solid state drives are now, they are only getting better. For example, SATA-based SSDs were once viewed as miraculous, but they are now looked at as slow — PCIe-based NVMe drives are all the rage. To highlight the steady evolution of flash storage, Western Digital today unveiled the first-ever 512 gigabit 64-layer 3D NAND chip. “The launch of the industry’s first 512Gb 64-layer 3D NAND chip is another important stride forward in the advancement of our 3D NAND technology, doubling the density from when we introduced the world’s first 64-layer architecture in July 2016.
Western Digital unveils first-ever 512 gigabit 64-layer 3D NAND chip
https://betanews.com/2017/02/06/western-digital-512-gigabit-64-layer-3d-nand-chip/
“The launch of the industry’s first 512Gb 64-layer 3D NAND chip is another important stride forward in the advancement of our 3D NAND technology, doubling the density from when we introduced the world’s first 64-layer architecture in July 2016. This is a great addition to our rapidly broadening 3D NAND technology portfolio. It positions us well to continue addressing the increasing demand for storage due to rapid data growth across a wide range of customer retail, mobile and data center applications,” says Dr. Siva Sivaram, executive vice president, memory technology, Western Digital.
Western Digital further explains that it did not develop this new technology on its own. The company shares, “The 512Gb 64-layer chip was developed jointly with the company’s technology and manufacturing partner Toshiba.
Tomi Engdahl says:
Intel Shows 2.5D FPGA at ISSCC
EMIB forms lower cost 2.5D bridge
http://www.eetimes.com/document.asp?doc_id=1331317
Intel gave the most detailed look at its lower cost alternative to 2.5D packaging in a paper on its Stratix X FPGA at the International Solid State Circuits Conference (ISSCC) here. In the same session, AMD showed its Zen x86 processor sports a 10 percent smaller die than Intel’s latest 14nm CPUs.
The Stratix X uses Intel’s Embedded Multi-die Interconnect Bridge (EMIB) to link the FPGA with four external transceivers. The bridge is made using silicon die mounted in a BGA substrate which is significantly smaller than the silicon substrates used in the CoWoS process developed by TSMC and used by rival FPGA vendor Xilinx and GPU designer Nvidia.
EMIB uses a combination of 55 micron micro-bumps and 100+ micron flip-chip bumps to support up to 24 transceiver channels with 96 I/Os each. They deliver 2 Gbits/second/pin at 1.2 pJ/bit/die using a proprietary protocol.
Currently, the bridge links four 28 GHz serdes to the FPGA. Intel has a road map to faster serdes
Tomi Engdahl says:
1000 times more efficient nano-LED opens door to faster microchips
https://www.tue.nl/en/university/news-and-press/news/02-02-2017-1000-times-more-efficient-nano-led-opens-door-to-faster-microchips/
The electronic data connections within and between microchips are increasingly becoming a bottleneck in the exponential growth of data traffic worldwide. Optical connections are the obvious successors but optical data transmission requires an adequate nanoscale light source, and this has been lacking. Scientists at Eindhoven University of Technology (TU/e) now have created a light source that has the right characteristics: a nano-LED that is 1000 times more efficient than its predecessors, and is capable of handling gigabits per second data speeds. They have published their findings in the online journal Nature Communications.
The researchers in Eindhoven believe that their nano-LED is a viable solution that will take the brake off the growth of data traffic on chips. However, they are cautious about the prospects. The development is not yet at the stage where it can be exploited by the industry and the production technology that is needed still has to get off the ground.
Tomi Engdahl says:
Germaniumtransistori outperforms silicon
A group of scientists from the Dresden University of Technology has introduced the first transistor based on germanium and which can be programmed in electron and hole conduction. Germanium is a promising material for future suuriskaalaisen integration of transistors, because it is superior in hole mobility.
Germanium also has a lower band gap, which is why germanium transistors can be operated at low voltages and low power use compared to silicon.
According to scientists, the results show for the first time a combination of low operating voltages and lower off-state leakage. The results are key to new energy-efficient circuits.
Source: http://www.etn.fi/index.php/13-news/5804-germaniumtransistori-paeihittaeae-piin
Tomi Engdahl says:
Nexperia
https://en.wikipedia.org/wiki/Nexperia
Nexperia is the future name of the Standard Products business of NXP Semiconductors (formerly Philips Semiconductors), an industry leading supplier of Discrete, Logic and PowerMOS semiconductors focused on the automotive, industrial, computing, consumer, and wearable application markets.
Tomi Engdahl says:
Market for Power Semiconductors in Automotive to Rev Up by $3 Billion by 2022
http://powerelectronics.com/pmics/market-power-semiconductors-automotive-rev-3-billion-2022?NL=ED-003&Issue=ED-003_20170208_ED-003_605&sfvc4enews=42&cl=article_2_b&utm_rid=CPG05000002750211&utm_campaign=9601&utm_medium=email&elq2=4914a23b8a314969bd128ce83cbbd0a7
The global market for power semiconductors used in cars and light passenger vehicles will grow by more than $3 billion in the next six years, according to new analysis released by IHS Markit.
The report, entitled “Power Semiconductors in Automotive-2017,” forecasts the total market for power semiconductors (discretes, power modules, and power ICs) to increase from $5.5 billion in 2016 to more than $8.5 billion in 2022. Revenue will grow at an annual rate of 7.5% from 2015 to 2022, the report predicts.
“Increasing electrification in vehicles generally—and in hybrid and electric vehicles specifically —is energizing the market for power semiconductors in vehicles,”
“Staying connected via smartphones and tablets is the modern way of life and to this end, today’s car drivers are opting for Bluetooth, cellular technologies, and other telematics functions.”
https://technology.ihs.com/586870/power-semiconductors-in-automotive-report-2017
Tomi Engdahl says:
Will PMIC On-Demand Replace Catalog Power Devices?
http://electronicdesign.com/pmics/will-pmic-demand-replace-catalog-power-devices?NL=ED-003&Issue=ED-003_20170208_ED-003_605&sfvc4enews=42&cl=article_1_b&utm_rid=CPG05000002750211&utm_campaign=9601&utm_medium=email&elq2=4914a23b8a314969bd128ce83cbbd0a7
There is a new trend to customize power-management integrated circuits on-demand using interconnected power blocks, adding flexibility, and potentially disrupting the power device business.
Most consumer electronics products rely on power-management integrated circuits (PMICs). As those consumer devices evolve, designers face the constant challenge of trying to reduce board footprint and decrease power consumption. Over the years, programmable analog devices like field-programmable analog arrays (FPAAs) have been used very successfully. Now, a new developer called AnDAPT is paving the way toward customized, integrated power-management solutions.
AnDAPT claims that its on-demand power-management technology can be configured exactly to the power characteristics of a particular system without worrying about analog issues, such as varying interface voltage, interface current, noise, and impedance matching. Its solutions use analog power blocks with scalable integrated MOSFETS (SIMs) to increase current capabilities. These analog power blocks are called Adaptive Multi-Rail Power (AmP) platform ICs; they are interconnected with digital circuitry in a way comparable to field-programmable gate arrays (FPGAs). Because of the digital interconnect fabric, AmP platform ICs can be configured precisely to the power characteristics of a particular system.
Tomi Engdahl says:
Nexperia – the new name in Discretes, Logic and MOSFET devices
https://silica.avnet.com/wps/portal/silica/manufacturers/nexperia/!ut/p/z1/04_Sj9CPykssy0xPLMnMz0vMAfIjo8zi3S1NPQ2dnQ18DXwczQwcvUxDDI0Mjd3dLE30w1EVuJv7OBs4Blg6uoaE-Bi4G5jqRxGj3wAHcDQgrD8KVQkWF6ApMAqzACnw9w0M8vH0CoYpwOOGgtzQCINMT0UAmixkzA!!/dz/d5/L2dBISEvZ0FBIS9nQSEh/
Nexperia is a dedicated global leader in Discretes, Logic and MOSFET devices. This new company became independent at the beginning of 2017. Focused on efficiency, Nexperia produces consistently reliable semiconductor components at high volume: 85 billion annually. The company’s extensive portfolio meets the stringent standards set by the Automotive industry. And industry-leading small packages, produced in their own manufacturing facilities, combine power and thermal efficiency with best-in-class quality levels.
Tomi Engdahl says:
UBM Announces 2017 Golden Mousetrap Award Winners
https://www.designnews.com/content/ubm-announces-2017-golden-mousetrap-award-winners/88471597947454?cid=nl.x.dn14.edt.aud.dn.20170208.tst004t
It was a packed house as the editors of Design News presented the 2017 Golden Mousetrap Awards, held in conjunction with Pacific Design & Manufacturing in Anaheim, Calif.
Tomi Engdahl says:
Narottam Medhora / Reuters:
Nvidia beats estimates with Q4 revenue of $2.17B, up 55% YoY, vs. $2.11B expected, as its GPU sales grow 57% to $1.85B, automotive business up 37.6% to $128M
Graphics-chip maker Nvidia’s revenue beats expectations
http://www.reuters.com/article/us-nvidia-results-idUSKBN15O2W1
Tomi Engdahl says:
Fully digital PLL to shrink radio
The Belgians IMECin and Holst Centre’s technology centers, together with Röhm presented a fully digital phase-control loop of San Francisco’s ISSCC conference.
Dutch researchers say the PLL is one of the largest radio part of power consumers. Additionally, it may be responsible for nearly a third of the radio circuit cards required by the sector.
ADPLL circuit is implemented in 40-nm CMOS process. It takes silicon space of only 0.18 square millimeters
ADPLL-component can be implemented, for example, all the different ultra low power Bluetooth radio (Bluetooth low energy) significantly existing circuits at lower cost and lower power consumption.
Source: http://www.etn.fi/index.php/13-news/5819-taysin-digitaalinen-pll-kutistaa-radion
Tomi Engdahl says:
What Can Be Cut From A Design?
Doing more with less equates to bigger design challenges.
http://semiengineering.com/what-can-be-cut-from-a-design/
A long-standing approach of throwing everything into a chip increasingly is being replaced by a focus on what can be left out it.
This shift is happening at every level, from the initial design to implementation. After years of trying to fill every square nanometer of real estate on a piece of silicon with memory and logic, doubling the number of transistors from one process node to the next, it’s becoming harder technologically and financially to keep up that pace. Heat, power, complexity and rising costs per transistor after 28nm have made it less attractive to continue doing things the way they were done in the past.
“Complexity has increased substantially in terms of how we manage 16, 10 and 7nm designs and to be able to get them to work as expected,”
Tomi Engdahl says:
Routing Signals At 7nm
Teklatech’s CEO talks about the challenges of scaling and how to minimize IR drop and timing issues.
http://semiengineering.com/routing-signals-at-7nm/
Tomi Engdahl says:
Devices Threatened By Analog Content?
http://semiengineering.com/devices-threatened-by-analog-content/
With few measurable methods to assess analog quality, it’s not clear how that can impact safety-critical applications.
As the amount of analog content in connected devices explodes, ensuring that the analog portion works properly has taken on a new level of urgency.
Analog circuitry is required for interpreting the physical world and for moving data to other parts of the system, while digital circuitry is the fastest way to process it. So a sensor that gives a faulty reading in a car moving at high speed or a medical device, for example, could be dangerous. The problem is that analog test is nowhere even close to the maturity of digital test, and analog designs are so unique that establishing that kind of consistency is difficult.
In a recent blog, Stephen Pateras, product marketing director within the Silicon Test Solutions group of Mentor Graphics, talked about the wide gap between the quality of digital parts on an SoC and the analog mixed-signal content. “The majority of field failures in automotive ICs now occur within the mixed-signal portion of the chip.”
Moving Automotive Test Into The Analog Domain
Automotive test solutions risk overlooking the majority of field failures in automotive ICs.
http://semiengineering.com/moving-automotive-test-into-the-analog-domain/
Tomi Engdahl says:
Annual Laser Market Review & Forecast: Where have all the lasers gone?
http://www.laserfocusworld.com/articles/print/volume-53/issue-01/features/annual-laser-market-review-forecast-where-have-all-the-lasers-gone.html?cmpid=enl_lfw_lfwlasersourcesnewsletter_2017-02-09
Tomi Engdahl says:
Probing Those Tiny Millimeter-Wave ICs
http://mwrf.com/blog/probing-those-tiny-millimeter-wave-ics?NL=MWRF-001&Issue=MWRF-001_20170209_MWRF-001_189&sfvc4enews=42&cl=article_2_b&utm_rid=CPG05000002750211&utm_campaign=9560&utm_medium=email&elq2=40da5c10dfe44f75bace690e56ab8e5b
Semiconductors, notably integrated circuits (ICs), are helping electronic design engineers in general to achieve unprecedented levels of miniaturization with multiple-function circuits, be they combinations of components or complete receiver/transmitter front ends. Of course, such miniaturization also carries the challenge of testing these circuits, and the first look at a measurement for one of these ICs may be on a wafer or in die form.
Testing is no longer the simple practice of running a test cable between a coaxial component and the test port of a vector network analyzer (VNA). When it comes to testing at the chip level, it is time to get to know more about on-wafer probes.
Tomi Engdahl says:
TI Sees New Exponential Drivers
http://www.eetimes.com/author.asp?section_id=36&doc_id=1331315&
Tomorrow’s exponential growth in semiconductors will be fueled by a combination of specialized processes and design methodologies as transistor scaling becomes increasingly expensive, said the chef technologist of Texas Instruments.
Tomi Engdahl says:
Intel Shows 2.5D FPGA at ISSCC
EMIB forms lower cost 2.5D bridge
http://www.eetimes.com/document.asp?doc_id=1331317&
Intel gave the most detailed look at its lower cost alternative to 2.5D packaging in a paper on its Stratix X FPGA at the International Solid State Circuits Conference (ISSCC) here. In the same session, AMD showed its Zen x86 processor sports a 10 percent smaller die than Intel’s latest 14nm CPUs.
The Stratix X uses Intel’s Embedded Multi-die Interconnect Bridge (EMIB) to link the FPGA with four external transceivers. The bridge is made using silicon die mounted in a BGA substrate which is significantly smaller than the silicon substrates used in the CoWoS process developed by TSMC and used by rival FPGA vendor Xilinx and GPU designer Nvidia.
Tomi Engdahl says:
DesignCon Engineer of the Year Casts Her Focus on Signal Integrity
Heidi Barnes would like to see more attention on signal integrity at the university level.
https://www.designnews.com/content/designcon-engineer-year-casts-her-focus-on-signal-integrity/14549356147406?cid=nl.x.dn14.edt.aud.dn.20170207.tst004t
For Heidi Barnes, electronic signal integrity is a mission.
Barnes, selected this week by her colleagues as the DesignCon 2017 Engineer of the Year, believes that improvements in signal integrity will yield better cloud communications, greater availability of digital information, and more energy-efficient server farms.
“It all has to do with speed,” she told Design News. “The amount of digital information that people want to consume and use in the cloud and in the IoT – all of it demands signal and power integrity.”
Tomi Engdahl says:
Mark Hachman / PCWorld:
With PC market in decline, Intel shifts its strategy to “data center first”, using newest manufacturing technologies for server chips like Xeon before PC CPUs
Intel demotes PCs, giving datacenter chips first crack at new technologies
Intel’s following the money into higher-margin businesses.
http://www.pcworld.com/article/3168319/components-processors/intel-demotes-pcs-giving-datacenter-chips-first-crack-at-new-technologies.html
With Intel’s forecasts projecting the PC could be the smallest moneymaker five years from now, the company has gone “data center first”—giving Intel’s server business first crack at new manufacturing technologies.
It’s another sign of massive change within Intel, as the traditional PC business is shoved to the side. In a slide presented during Intel’s investor day on Thursday, the company showed off how the total available market (TAM) for its PC CPU business was just $30 billion or so, less than half that of the data center.
The TAM, as its known, projects the maximum available revenue Intel could pull in if it owned the entire market—which won’t happen. It’s an excellent guide to which segments Intel is prioritizing, however: the data center, non-volatile memory like flash and its new Optane, plus mobile communications and various embedded segments.
Historically, if Intel jumped ahead to a new manufacturing technology, its PC chips would get first crack. Now, Intel’s premium fab lines are reserved for the Xeon and other chips being shipped to cloud providers and the data center.
Intel’s priorities: the cloud, not the PC
Intel’s always had a strong interest in the server market, and a quick look at Intel’s price list shows why: Desktop Core chips command $300 or so apiece, while a single Xeon chip for servers can be priced up to almost $9,000.
That doesn’t mean the PC is dead, but it isn’t commanding the lion’s share of attention at Intel anymore.
Kraznich, though, spoke glowingly of Optane’s desktop future. “Every single gamer is going to want 3D Xpoint,”
Tomi Engdahl says:
New Memories And Architectures Ahead
So far there is not widespread adoption, but many see change as inevitable.
http://semiengineering.com/new-memories-and-architectures-ahead/
Memory dominates many SoCs, and it is rare to hear that a design contains too much memory. However, memories consume a significant percentage of system power, and while this may not be a critical problem for many systems, it is a bigger issue for Internet of Things (IoT) edge devices where total energy consumption is very important.
Memory demands are changing in almost all systems. While new memories and memory architectures have been on the drawing board for a long time, adoption still is not widespread. However, many in the industry believe the tipping point is near.
SRAM and DRAM have been the workhorses of the memory hierarchy for the past 50 years, with flash being adding into the mix more recently. All of these memory structures have problems scaling at smaller geometries, partially resulting from the fact that they are all surface-level constructs.
The newer memory technologies, based on resistance switching, are metal layer constructs, which eliminate many of the fabrication issues.
The list of new memories vying for attention include Phase-Change memory (PCM), Ferroelectric RAM (FeRAM), Magneto-resistive RAM (MRAM), Resistive RAM (RRAM or ReRAM), spin-transfer torque RAM (STT-RAM), Conductive Bridging RAM (CBRAM) and Oxide-based resistive memory (OxRAM).
Computing total energy
The total energy consumed by memory has several components, all of which must be considered. These include:
• Memory cell maintenance power;
• Read, write and erase power;
• Interface power, and
• Architectural optimizations.
Different applications may balance these in different ways, along with other attributes such as persistence and performance.
Consider DRAM. “DRAM is cost competitive although not ideal,” says Ternullo. “It uses a capacitive cell that has to be refreshed. As you increase density, the cell capacitance goes down and—thanks to the laws of physics—you have to refresh more often.”
Other memory types, such as SRAM, can have a significant passive and dynamic power component just to maintain their state.
And while non-volatile memory (NVM) may have zero retention current, you cannot forget the surrounding logic.
Then there is the energy required to read, write and possibly erase the memory locations. Several of these costs will be memory technology related. “For many types of flash memory, write current tends to be higher than read current,”
Tomi Engdahl says:
“Come on Feel the Noise”—Measuring LDO Performance
http://electronicdesign.com/test-measurement/come-feel-noise-measuring-ldo-performance?NL=ED-003&Issue=ED-003_20170213_ED-003_255&sfvc4enews=42&cl=article_1_b&utm_rid=CPG05000002750211&utm_campaign=9662&utm_medium=email&elq2=a7bc6ba976024f4194eb33ba497828c0
With all due respect to heavy-metal band Quiet Riot (Fig. 1), who covered the song in the title (and the British band Slade who did the original 1973 version), if you can in fact “Feel the Noise” from your linear regulator, something is seriously wrong. Although seeing, smelling, or tasting the noise would arguably be worse!
When specifying an LDO’s noise performance, we can distinguish between two types of noise, each one with its own datasheet parameter.
Internally Generated Noise
Intrinsic noise is generated in the device itself. It’s characterized by an output spectral-noise-density graph in the datasheet, which shows how the noise, expressed in μV/√Hz, varies over frequency.
Externally Generated Noise and PSRR
The power-supply rejection ratio (PSRR), also called the power-supply ripple rejection, describes how well the LDO rejects noise from an external source that appears on its input. This external noise can originate from a switching power supply, parasitic coupling, or elsewhere. The PSRR compares the output ripple and the input ripple over the frequency range of interest for the application.
Measuring LDO Noise Performance
When characterizing an LDO and measuring its noise performance, it‘s important to ensure that the results reflect only the noise we’re interested in.
The LDO to be tested (the device under test, or DUT) is mounted on an evaluation module (EVM) and powered by an external power supply.
For lowest noise, a purely resistive load is used for the DUT. A battery is preferred as the power source, but this may not be practical for high-current DUTs. Bench power supplies are readily available, but tend to be noisy with spikes at the 50- or 60-Hz line frequency. A linear supply is preferable if available.
A coupling capacitor after the DUT blocks its dc output and only passes the ac noise component to the downstream circuitry. Such a capacitor should have a 3-dB cutoff an order of magnitude lower than the lowest frequency being measured.
This leads to a large-valued component when measuring frequencies down to 10 Hz, say, when used with a coaxial cable of 50-Ω characteristic impedance. The capacitor in Figure 6 is a parallel array of numerous smaller capacitors totaling 5100 μF. It’s housed in its own shielded box with coaxial connectors.
Figure 7 shows the recommended test setup to measure PSRR performance. The EB5061B Network analyzer generates both dc and an RF noise signal, then compares the input and output voltages to arrive at the results.
Conclusion
LDOs are widely used to provide low-noise power in many sensitive analog and RF applications, and it’s important to be able to verify the LDO datasheet parameters in the lab.
Tomi Engdahl says:
Make schematic symbols understandable
http://www.edn.com/electronics-blogs/anablog/4457641/Make-schematic-symbols-understandable
Good schematics have a predictable flow. This flow requires inputs to the be on the left and top, while outputs are on the right and bottom. This is not cast in concrete, but it’s pretty important if you want other engineers to be able to read your schematic at a glance.
Tomi Engdahl says:
Microsemi wants to mobile phone base stations
Microsemi is after the recent Actel-kauapn the world’s third largest manufacturer of FPGA circuits. Now it wants to challenge Intel Xilinx and Altera also owned a cell phone network base stations with new Polar Fire series chips.
Polar Fire reaches 500 in the register or logic element size – this is a medium-sized midrange-circuits.
Marena emphasize that the Polar Fire-family is designed ground up specifically for midrange-logic.
Micro Semin FPGA are flash-based, so they have many advantages compared to competitors’ larger SRAM-based circuits.
Source: http://www.etn.fi/index.php/13-news/5837-microsemi-haluaa-kannykkaverkkojen-tukiasemiin
More:
PolarFire FPGA Family
Lowest Power, Cost Optimized, Mid-Range FPGAs
https://www.microsemi.com/products/fpga-soc/fpga/polarfire-fpga
Tomi Engdahl says:
Rohde & Schwarz introduces 6 GHz oscilloscope at DesignCon 2017
http://www.edn.com/electronics-products/designcon/4457502/Rohde—Schwarz-introduces-6-GHz-oscilloscope-at-DesignCon-2017
At DesignCon 2017, Rohde & Schwarz introduced the RTO2064, a 6-GHz, four-channel oscilloscope. This model moves the RTO2000 series top model from 4 GHz (RTO2044) to 6 GHz when using two channels. On four channels, the RTO 2064′s bandwidth drops to 4 GHz
Tomi Engdahl says:
DesignCon 2017: PAM4 measurements are solidifying, but remain in flux
http://www.edn.com/electronics-blogs/rowe-s-and-columns/4457432/DesignCon-2017–PAM4-measurements-are-solidifying–but-remain-in-flux
Chris Loberg from Tektronix opened by stating “PAM4 is catching on. In 2014, there was one standard, now there are 12, including one with 56 Gsps. 112 Gsps standards are coming.” While that may be true, there are still problems to solve. While PAM4 and forward error correction (FEC) may have solved the bandwidth problem (for now), they’ve created a new set of technical problems that have yet to be solved. This year’s panel discussion focused on some of those issues.
“nobody will pay for better PCB. We are all too cheap so we need ways to get around that.” He continued, “A 56 Gbps NRZ eye is closed so what do we do? Channels can have 30 dB to 50 dB of loss.” While a 56 Gbps PAM4 signal operates at 14 GHz (as opposed to 28 GHz NRZ, but at 12 dB worse SNR. That results in more complexity. FEC lets engineers relax BER by over a million, from 1E-12 to 1E-06 and even higher. “We only pay a small cost, a 3% to 6% overhead. But, it’s not that easy. There are new issues to resolve such as bit patterns and eye masks.”
Liu’s team ran a 68-hour BER test with raw bit-error ratio (BER) at 10E-6. “After turning on the FEC, we achieved error-free operation over a long weekend,” she said.
In addition to achieving the error-free operation, the FEC engine can report settings and provide an error signature, telling the engineers how many coded words couldn’t be corrected, of which there were none in this test. “Using DSP, we can relax the raw BER to 1E-5 or even 1E-4,”
But, she noted that FEC can’t always reduce BER from 1E-5 to 1E-15. It depends on the error signature. Low-frequency jitter, compression, and tuning of the channel can affect probability of error.
Because FEC lets you use higher raw BER, it reduces test time. You don’t have to wait as long to measure raw BER because FEC reduces it from 1E-10 to 1E-12 to as low as 1E-4. “Consistency of FECs is still poor,”
Inphi’s Mark Marlett is trying to support customers who are developing 400 Gbps optical systems. He’s running into issues with 400G because of emerging optical standards, which are not yet stable
While he admitted that engineers still need to predict BER, he questions if we still need jitter derivation. For example, he noted that at the chip makers, the focus is less on signal integrity and more on error correction, saying “FEC is a game changer.”
Marty Miller from Teledyne LeCroy spoke next about test patterns, which he describes as one of his favorite subjects. He pointed to a conflict between T&M companies and chip companies, saying “Chip makers don’t like complex bit patterns. While PRBS patterns are easier to use, they suffer because worst-case conditions are so rare that tests can miss them.”
He even claimed that you can predict an eye diagram from the BER. One such pattern being proposed is SSPRQ, which Miller described as a shorter, but more complex pattern than PRBS
“The test people were whining that PRBS31 is too long of a pattern,” he said. “We tried to convince the industry to drop it. We got our wish.” He noted that SSPRQ patterns can produce sufficient stress on systems, but with shorter patterns than PRBS31.
“SSPRQ has the right properties. It has the right stress points and has similar statistical properties as PRBS31 (over 2 billion symbols), but is shorter. Unfortunately, SSPRQ patterns break everything.”
My chip broke so it (the test pattern) can’t be right, he’s heard from chip makers. But, SSPRQ is now part of communications standards and Zivny said engineers aren’t sure what to do.
“Are there PAM mask tests?” asked one engineer. LeCheminant responded by noting that eye masks were shot down by optical standards groups, citing no correlation between eye masks and system performance. Instead, fiber-optics engineers rely heavily on TDECQ.
It’s clear from the 2017 closed eye panel that PAM4 isn’t the perfect solution to the bandwidth problem posed by NRZ, but it’s the best one we have, at least for now.
Tomi Engdahl says:
Piezo Flexure Actuators, Nanopositioners, and Other Piezo Mechanisms for Precision Motion Control Applications
http://www.pi-usa.us/blog/piezo-flexure-actuators-and-other-piezo-mechanisms-for-precision-motion-control-applications/
Flexure-guided and motion-amplified actuators and positioning stages provide convenience and performance for the OEM designer and scientist.
Piezo actuators, a special form of electro-ceramics, are the gold standard when it comes to precision, speed, and force in a small package.
At the heart of piezoelectric flexure actuators is a stack of layers of specialized ceramic, only a few dozen microns thick, interleaved with electrodes, and sintered into a solid structure. The most common piezo ceramic for high-performance positioning applications is PZT (lead-zirconate-titanate), a ferroelectric ceramic. This material is useful for positioning because PZT ceramic exhibits a small, but almost linear dimensional change as voltage is applied across the electrodes. This provides a precise, controllable motion input to the engineer’s mechanism. Position changes on the order of nanometers can be achieved without difficulty.
The operation of the piezo ceramic element is characterized by four factors:
a) precision; b) speed; c) short travels; and d) high force.
Tomi Engdahl says:
Test More Complex For Cars, IoT
http://semiengineering.com/test-becoming-more-complex/
Safety-critical markets add new challenges for testing methodology, which can affect functionality, reliability and yield.
With increasing focus on safety-critical semiconductors—driven by ADAS, IoT, and security—functional safety concerns are going through the roof. Engineering teams are scrambling to determine how to conduct better in-field or online testing because test no longer can be an afterthought.
This has been a common theme across the automotive ecosystem for the past few years, and as the automotive electronics market continues to ramp it has taken on a new sense of urgency. But along with that, the methodologies for conducting those tests and the ramifications of the power involved in those tests are coming under increased scrutiny because of their impact on yield, quality, and the long-term reliability of systems.
But the actual test modes can be so complex that to test in situ, or to do a full system emulation, is difficult. So test modes are put into a chip to be able to take advantage of whatever internal BiST is possible, such as subsystem that does not require the full stack of the protocol or of the algorithms to verify its existence.
There is some overhead associated with test, however. Compared with functional mode, for example, test mode adds power challenges.
Finally, it is important to perform specific design and simulation checks to verify testing on low power designs including:
Low power verification of the DFT structures and power-aware test patterns;
Static checks after DFT implementation, and
Validation of correct power behavior during Verilog simulation of generated test patterns.
Test has always been the bogeyman where the worst pathological situations are created on the tester.
“Even more interesting isn’t scan, but it’s things like LBiST and MBiST where it’s not sitting on the tester but now it’s in the product,”
Tomi Engdahl says:
Leadless MOSFET Power Package Achieves Near-GaN Switching Losses
http://powerelectronics.com/discrete-power-semis/leadless-mosfet-power-package-achieves-near-gan-switching-losses?NL=ED-003&Issue=ED-003_20170215_ED-003_437&sfvc4enews=42&cl=article_1_b&utm_rid=CPG05000002750211&utm_campaign=9700&utm_medium=email&elq2=2ae0900f362a43a6b4631f0fad630186
Modern semiconductors facilitate faster switching speeds and lower losses to support designers. A new leadless power package drives down on-state resistance and provides close to “GaN-like” switching losses, making a significant step forward in hard switching applications.
Newly available SMD power semiconductors support fast switching and reduce the parasitic inductance associated with the long leads on packages like the TO‑220 or TO‑247. However, the thermal management challenge is historically difficult using SMDs.
This is particularly true in high-power PFC (power factor correction) circuits and it is the main reason that TO‑220 and TO‑247 packages are still preferred by many engineers for this type of application. Now, newly available TO-LeadLess (TOLL) packages (Fig. 1) matched with latest-generation superjunction MOSFET technology, offer the opportunity to migrate even high-power PFC circuits to SMD solutions.
The small size of the TOLL package is ideal for modern, dense SMPS designs where high current capability combined with low thermal resistance (RTHJC) results in less waste heat.
Packaging is important in Infineon Technologies’ CoolMOS process
The TOLL package also offers a Kelvin Source connection that reduces the parasitic source inductance being fed back to the gate voltage, resulting in both faster switching and cleaner gate waveforms.
The TOLL package also has very low parasitic inductance (approximately 1 nH) when compared with the TO247 package (~15 nH). Thus, the bouncing of the signal ground is much lower, which reduces the voltage peaks at transition.
Tomi Engdahl says:
Battling Fab Cycle Times
http://semiengineering.com/battling-fab-cycle-times/
Why it’s taking longer to manufacture chips at 10/7nm and what can be done about it.
The shift from planar devices to finFETs enables chipmakers to scale their processes and devices from 16nm/14nm and beyond, but the industry faces several challenges at each node.
Cost and technical issues are the obvious challenges. In addition, cycle time—a key but less publicized part of the chip-scaling equation—also is increasing at every turn, creating more angst for chipmakers and customers alike. In fact, cost, technical hurdles and cycle time are all contributing to the ongoing slowdown of Moore’s Law.
Cycle time is the amount of time it takes to process a wafer lot in a fab from start to finish. Typically, a wafer lot consists of 25 wafers, which move through various process steps in a fab. An advanced logic process could have from 600 to 1,000 steps or more.
For instance, 3D NAND and finFETs are complex 3D-like structures with more layers, as compared to their planar counterparts. It takes more steps to process them, increasing the cycle time in a fab.
To combat the increase in cycle times, chipmakers want faster equipment, with patterning tools being the top priority. In response, equipment vendors are making tools with higher throughputs. The tools can also process more advanced and smaller structures.
Despite the throughput gains, cycle times are still increasing amid the shift towards more multiple patterning steps and other processes. “Our process and product complexity have gone up faster than the productivity improvements of the tools,”
Generally, the most common metric for cycle time in the fab is “days per mask layer.” On average, a fab takes 1 to 1.5 days to process a layer. The best fabs are down to 0.8 days, Leachman said.
A 28nm device has 40 to 50 mask layers. In comparison, a 14nm/10nm device has 60 layers, with 7nm expected to jump to 80 to 85. 5nm could have 100 layers. So, using today’s lithographic techniques, the cycle times are increasing from roughly 40 days at 28nm, to 60 days at 14nm/10nm, to 80 to 85 days at 7nm. 5nm may extend to 100 days using today’s techniques, without extreme ultraviolet (EUV) lithography.
the cycle time in the fab increases at the start of a process, but drops as the technology matures
“The cost per memory cell or transistor is still coming down. It’s probably coming down a lot slower than it used to as we move toward the end of Moore’s Law,” Leachman said. “But the speed at which we get them is not coming down. It’s going up. That’s the big challenge. It’s worth a lot of money, and it’s a hard problem that we are not doing very well at.”
The issues involving cycle time start in the photomask shop. In the flow, a chipmaker designs an IC, which is then translated into a file format. Then, a photomask is developed based on that format.
So the mask and lithography are tied together. Today, chipmakers use 193nm wavelength lithography to print tiny features on a wafer. In reality, though, 193nm lithography reached its limit at 80nm half-pitch.
To extend 193nm lithography, chipmakers use a reticle enhancement technique (RET) called optical proximity correction (OPC). OPC makes use of tiny shapes, or sub-resolution assist features (SRAFs).
At 20nm, though, the SRAFs became too dense on the mask, making it more difficult to print discernible features on the wafer.
To solve the problem, logic vendors moved to multiple patterning. In multiple patterning, “the original mask shapes are divided between two or more masks”
“Each mask is then printed separately, eventually imaging the entire set of originally-drawn shapes onto the wafer.”
erm turnaround time (TAT), which is the time to produce and ship a mask.
In total, the TAT is about 7.28 days for a 28nm mask
Write times are the biggest culprit. As stated above, an IC design is translated into a file format. The format is translated into a set of instructions for an e-beam mask writer. This process is called mask data preparation (MDP).
Once the mask is completed, it is transported to the fab. In a theoretical fab with 50,000 wafer starts per month, a plant may require the following equipment, according to UC Berkeley:
• 50 scanners/steppers plus wafer tracks;
• 10 high-current and 8 medium-current ion implanters;
• 40 etch machines, and
• 30 CVD tools, according to UC Berkeley.
A fab also requires cleaning systems and process control tools.
To get everything working in unison, fabs use various factory automation technologies.
Besides the logistics, fab managers are concerned about other matters. “The manager cares about cost, cycle time and predictable yield,”
In fact, the biggest contributor to cycle times is wait times.
“But the higher utilization you run in the fab, the longer the queue time effect you have.”
The finFET manufacturing process starts with patterning, which is the biggest bottleneck in terms of cycle time
Not long ago, a 193nm scanner had throughputs of 100 wafers an hour. “Now, the scanners are 275 wafers an hour with even better precision,”
It could be a different ball game if the industry adopts EUV. For example, cycle times could drop
Multi-patterning also requires thin films using a slow process called atomic layer deposition (ALD).
Tomi Engdahl says:
Better Chips, Better Cars
The foundry perspective on automotive chip manufacturing.
http://semiengineering.com/better-chips-better-cars/
There are literally thousands of electronic components in a new car, and those numbers are only going to increase as cars become smarter, safer, greener, and increasingly connected.
As automakers and Tier 1 and Tier 2 companies shift their focus from mechanical to a combination of mechanical and electrical, there is an ongoing race among fabless companies to come up with innovative technologies for everything from ADAS to infotainment to better connectivity.
Tomi Engdahl says:
What’s Next For NOR Flash?
NOR remains viable amid a decline in growth.
http://semiengineering.com/whats-next-for-nor-flash/
The flash memory market is the tale two of cities.
Today, NAND and NOR are the two main flash memory types. Over the years, the NAND flash market has exploded. Targeted for data storage, NAND flash has moved into flash cards, solid-state storage drives (SSDs) and other products. The excitement for NAND continues to mount, as the technology is moving from planar to a 3D structure. In fact, 3D NAND is still in the early stages and the market is also exploding.
Amid the boom for NAND, NOR got lost in the shuffle. Typically, NOR is used for code storage.
“The NOR market is a shadow of its former self,” said Jim Handy, an analyst with Objective Analysis. “It was up around $3.5 billion a few years ago, and is now around $1 billion. It lost out when the cell-phone market went to smartphones, which don’t use NOR. The old standby applications still use it: set-top boxes, PC BIOS, candy bar phones and others. But the unit demand hasn’t grown very fast for those applications and the prices have declined an average of 30%/year, so the revenues have declined significantly.”
Still, NOR flash is used for a multitude of applications. Today, the NOR market can be divided into two segments—standalone devices and embedded applications. Cypress, Macronix, Micron, Winbond and others sell standalone NOR devices.
Of the two segments, embedded NOR is arguably the most dynamic market. The embedded chip market itself is exploding on several fronts, such as automotive, industrial, medical, wireless and others.
The highest-volume MCUs tend to use old processes like 90nm and 130nm,” Handy said. “It will be a long time before many start to use the sub-20nm processes that require finFETs.”
MCUs integrate several components on the same chip, such as a CPU, SRAM, embedded memory and peripherals.
Then, embedded memory, such as EEPROM and NOR flash, are used for code storage and other functions. “The difference is whether it has one transistor per bit cell (NOR) or two (EEPROM). Most MCU makers use EEPROM and others use NOR,” Handy said.
Embedded NOR is robust. “It does one job really well,”
The mainstream market for embedded NOR flash is at 40nm and above, although the industry is beginning to migrate towards smaller geometries
Embedded NOR has some limitations, however. Write speeds are slow. It requires more masks at each node, thereby impacting cost and complexity.
Tiwari and others believe that 28nm will be a long-lasting node for embedded flash and chips in general. But can NOR scale beyond 28nm?
What’s next?
To be sure, the automotive industry would need an embedded flash memory that can scale. “Therefore, we expect that some of the automotive applications would move to a SIP solution with SuperFlash memory fabricated at the 2xnm or 4xnm nodes,” he said. So, instead of scaling embedded NOR to 16nm/14nm and beyond, Microchip’s SST sees a scenario where NOR is integrated into a system-in-package (SIP) scheme. The MCU could be part of the SIP as well.
Tomi Engdahl says:
What Are FeFETs?
How this new memory stacks up against existing non-volatile memory.
http://semiengineering.com/what-are-fefets/
The memory market is going in several different directions at once. On one front, the traditional memory types, such DRAM and flash, remain the workhorse technologies in systems despite undergoing some changes in the business. Then, several vendors are readying the next-generation memory types in the market.
As part of an ongoing series, Semiconductor Engineering will explore where the new and traditional memory technologies are heading. In this segment, Stefan Müller, chief executive of Ferroelectric Memory Co. (FMC), sat down with Semiconductor Engineering to discuss memory technology and other topics. Startup FMC is developing ferroelectric FETs (FeFETs), a new memory type. The technology can also be applied to logic.
Müller: With respect to existing memory solutions, several hurdles are rising as the industry marches along Moore’s Law. The current embedded NVM or eNVM market is dominated by embedded NOR-type flash, which does the job well and will be around for a long time. However, embedded NOR flash increases in cost on top of the logic base technology, as you scale to more advanced process nodes.
due to intrinsic electrostatics, conventional embedded flash or eFlash cells and their high voltage pumps do not scale and remain power hungry during write operations.
SE: What are the challenges with other memory types?
Müller: In the DRAM world, there are significant technological challenges to be overcome, especially when you look at scaling to 1xnm and beyond. DRAM is still based on a 1T-1C memory cell that has trouble scaling, and has a certain cost adder to it due to the stacked capacitor. Moreover, it is obviously volatile and therefore consumes power even in the idle state. Regarding standalone NVM NAND flash, the industry is pushing hard for 3D integration with companies like Samsung, Micron and Toshiba in the lead. 3D NAND is difficult and requires highly customized process flows and fabs. The industry is still learning how to produce 3D NAND in high volume, and is experiencing growing pains transitioning from 2D to 3D.
Müller: Standard FRAM is based on a 1T-1C memory cell in which the ferroelectric film is implemented in the capacitor. FRAM has not scaled beyond the 130nm technology node due to the fact that only planar capacitors can be used and the traditional ferroelectric films are not scalable.
In comparison, the hafnium oxide based FeFET from FMC is a totally different memory cell in which the ferroelectric actually replaces the gate dielectric of a CMOS transistor. With the ferroelectric film thicknesses thinned down below 5nm, it is therefore scalable to the latest technology nodes.
Müller: You can think of the FeFET as a logic transistor that can maintain its logic state even when power is removed. In general, you replace the conventional logic gate dielectric with a ferroelectric material, a dielectric that remembers the electric field to which it had been exposed. With FMC’s proprietary hafnium oxide, the standard gate dielectric can be made ferroelectric
SE: Briefly, how do you make FeFETs?
Müller: As published at this year’s IEDM, currently only two additional masks are required for embedding FeFET next to standard CMOS logic. Since FMC’s FeFETs are actually derived from the CMOS baseline process, the ease of integration is a major advantage for FeFETs when compared to other emerging memory technologies.