Chip Market Brightens in 2017. The semiconductor industry may yet have been flat in 2016, but expects it is expected that the electronics industry rebounds in 2017, probably in the first half. Wall Streeter predicts return to 5% growth. Total IC business growth is expected to be around five percents for few years to come.There seems to several promises to this direction, especially in memory business. Chips Execs See Maturing Industry article says that pessimism about immediate revenue and R&D growth is a sign of a maturing industry.
Thanks to both rising prices and volume sales, the memory sector is expected to lead overall semiconductor sales growth. Sales of memory chips will increase 10% next year to a new record high of $85.3 billion, according to the latest report from IC Insights. NAND flash will grow almost as fast at 10% next year. The average annual growth rate for the memory market is forecast to be 7.3% from 2016-2021. Every year we need 5.6% more bits than previous year, and the unit prices are increasing on both DRAM and Flash.
There will be also other growth sectors. The data center will be the fastest growth segment next year, rising 10%, followed by automotive at 9% and communications at 7%. Consumer and industrial markets growing at about 4% in line with the overall industry. PCs will be the big drag on 2017, declining 2%.
China Dominates Planned Chip Fabs as more than 40% of front end semiconductor fabs scheduled to begin operation between 2017 and 2020 are in China, a clear indication that China’s long-stated ambition to build a significant domestic semiconductor industry is taking shape.
Trump Win Could Mean Big Questions for Manufacturing as while Trump vowed to keep American manufacturing jobs, he offered little in the way of stated policy other than the promise to punish companies that sent manufacturing job outside the US. Questions about trade also could directly affect US manufacturing. How that plays out is a big unknown.
Europe will try to advance chip manufacturing, but not much results in 2017 as currently there is almost no leading-edge digital chip manufacturing left in Europe as the local companies have embraced outsourcing of digital semiconductor manufacturing to foundries. The European Commission intends to reconvene a high-level group of European CEOs and executives to exchange views on Europe’s 10/100/20 nanoelectronics and chip manufacturing project and make adjustments as necessary for a wave of European Union investment supposedly starting in 2020. The two most advanced wafer fab locations left in Europe in terms of deep sub-micron miniaturization belong to Intel in Leixlip, Ireland and Globalfoundries in Dresden, Germany.
Smaller geometries are to be taken into use and researched in 2017. Several chipmakers ramp up their 10nm finFET processes, with 7nm just around the corner. As TSMC, GF/Samsung Battle at 7nm the net result is in the course of 18 months chip designers will see at least three variants of 7nm — separate immersion variants from TSMC and Globalfoundries and the EUV version from GF/Samsung. Intel has yet to detail its 7nm node.
At the same time R&D has begun for 5nm and beyond, but Uncertainty Grows For 5nm, 3nm as costs are skyrocketing. Both 5nm and 3nm present a multitude of unknowns and challenges. To put this in perspective, there are roughly two silicon atoms in 1nm of line width in a chip. Etching Technology Advances as atomic layer etch (ALE) moves to the forefront of chip-making technology—finally. TSMC recently announced plans to build a new fab in Taiwan at a cost of $15.7 billion targeted for TSMC’s 5nm and 3nm processes, which are due out in 2020 and 2022.
Moore’s Law continues to slow as process complexities and costs escalate at each node. Moore’s Law is dead, just not in the way everyone thinks. SiFive believes open source hardware is the way forward for the semiconductor industry. Technological advances keep allowing chips to scale, but the economics are another story – particularly for smaller companies that can’t afford chips in the volumes. The solution, according to San Francisco-based startup, SiFive, is open-source hardware, specifically an architecture developed by the company’s founders called RISC-V (pronounced “risk-five”). Done right SiFive, which was awarded Startup of the Year at the 2016 Creativity in Electronics (ACE) Awards, believes that RISC-V will do for the hardware industry what Linux has done for software. For example 5th RISC-V Workshop Points to Growing Interest in the RISC-V Platform.
Sensors are hot in 2017. These tiny, powerful solutions are creating the interface between the analog and the digital world. Data is everywhere, and sensors are at the very heart of that. While no one really knows what technology’s next “killer application” will be, we are confident that any killer app will rely on sensors.Appliance autonomy promises to make life simpler, but this field has still lots of to improve even after year 2017.
Interface ICs will continue to help simplify high-bandwidth designs while making them more robust and reliable. Application areas that will benefit include automotive, communications, and industrial. Both wired and wireless interface solutions have plenty of applications.
Analog’s status is rising as more sensors and actuators are added into electronic devices, pressure is growing to more seamlessly move data seamlessly back and forth between analog and digital circuitry. IoT pushes up demand for analog content and need for communication between these two worlds will continue to grow. Analog and digital always have fit rather uncomfortably together, and that discomfort has grown as SoCs are built using smaller feature sizes. The demand for analog silicon has always existed in the embedded space, but the advent of the Internet of Things (IoT) is increasing the demand for connected mixed-signal content. At 28nm and 16/14nm, standard “analog” IP includes a fair amount of digital content.
It seems that hardware designer is a disappearing resource and software is the king in 2017. It is becoming less and less relevant in what format the device is used in many applications. Card computers are standard products and are found in many different card formats that can be used in very many applications. Embedded development is changing to more and more coding. More software designers that understand some hardware are needed, but it is not easy to leap to move to the hardware to software.
The power electronics market is moving at very fast pace. Besides traditional industrial, renewable, and traction sectors, new applications such as energy-storage systems, micro-grids, and dc chargers are emerging. As the automotive world moves to electric vehicles, this creates challenges for IGBT and SiC-MOSFET ICs, and their associated gate drivers. New packages for high-voltage IGBTs and high-voltage SiC-MOSFETs are introduced.
More custom power distribution and higher voltages on data center computer systems in 2017. OpenRack and OpenCompute projects are increasing the distribution voltage inside the server itself. This approach, plus transitioning to new materials such as gallium nitride in the power-conversion systems, can reduce overall power consumption by 20% and increase server densities by 30-40%.”
Power Modules and Reference Designs will be looked at in 2017 even more than earlier in power electronics. The semiconductor and packaging technologies used in power modules have advanced considerably, and the industry is developing modules today that are denser, less expensive, and easier to use. Designers want to rely on power modules to speed up designs and optimize space using smaller, easy-to-use power modules. Module manufacturers hope that engineers will increasingly choose a module over a discrete design in many applications.
The bi-directional DC/DC converter has been around for a while, but new applications are quickly emerging which necessitate the use of this architecture in so many more systems. Battery back-up systems need bi-directional DC/DC converters. Applications today require better energy efficiency and such systems as green power with solar or wind generation, need storage so that when there is no wind or sun available the electricity flow is not interrupted.
Power supplies need to become more efficient. Both European Union’s (EU) Code of Conduct (CoC) Tier 1 and CoC Tier 2 efficiency standards are to be taken into use. The European Union’s CoC Tier 1 effectively harmonizes the EU with US DoE Level VI and became effective as a voluntary requirement from January 2014, two years ahead of Level VI. Its adoption as an EU Ecodesign rule is currently under review to become law with an implementation date of January 2017. The key difference between the CoC requirements and Level VI is the new 10% load measure, which imposes efficiency requirements under a low-load condition where historically most types of power supplies have been notoriously inefficient. CoC Tier 2 further tightens the no-load and active mode power consumption limits.
During 2016, wireless-power applications started to pick up across many fields in the semiconductor industry, and it will continue to do so. Wireless power will continue to gain traction with increased consumer demand. Hewlett Packard, Dell, jjPlus, and Witricity have already announced products based on Airfuel standards. And, products based upon the Qi standard will continue to grow at a rapid pace.
Other prediction articles:
In Power & Analog 2017 Forecast: What Experts Are Saying article representatives from major players in the semiconductor industry share their predictions for 2017 regarding power modules, wireless power, data converters, wireless sensing, and more.
Looking Ahead to 2017 article tells on to what SIA is focused on working with. “U.S. semiconductor technology should be viewed as a strategic national asset, and the Administration should take a holistic approach in adopting policies to strengthen this vital sector,” the letter says
Hot technologies: Looking ahead to 2017 article collection has EDN and EE Times editors explore some of the hot technologies in 2017 that will shape next year’s technology trends and beyond.
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Tomi Engdahl says:
Keysight adds 50/70/100 MHz oscilloscopes for educators, small labs
http://www.edn.com/electronics-products/electronic-product-reviews/other/4458079/Keysight-adds-50-70-100-MHz-oscilloscopes-for-educators–small-labs
Taking aim at rivals Rigol and Tektronix, Keysight Technologies has introduced a series of four oscilloscopes aimed at educators, small labs, and perhaps individuals. The InfiniiVision 1000 X-Series of two-channel oscilloscopes has bandwidths of 50 MHz, 70 MHz, and 100 MHz (upgradeable from 70 MHz with a software key) with prices starting at $449
Two of the four models have built-in 20-MHz function generators, something missing from the Tektronix 1000B series. All four models have a 5-digit frequency counter and a 3½-digit DVM, both of which you can activate with a code you get from registering your oscilloscope.
With the 1000 X-Series, Keysight adds a Bode Plot. That’s one feature you won’t find on competitive oscilloscopes nor on any other Keysight oscilloscope (at least for now, perhaps). That feature is especially helpful to educators who want to show students a circuit’s frequency response with having to manually plot points or export them to a PC. Besides an FFT function, the 1000 X-Series have math functions such as peak-to-peak, max, min, average, Frequency, period pulse width, and duty cycle.
Tomi Engdahl says:
MEMS: Improving Cost And Yield
http://semiengineering.com/mems-improving-cost-and-yield/
Second in a series: New packaging options could help boost profitability, but testing and thermal issues remain problematic.
There are several reasons for this:
• MEMS chips are like black boxes. In fact, they often are hermetically sealed because many of these devices need to work in a vacuum. That makes testing much more difficult.
• Yield depends on other factors than just the MEMS device. Frequently these chips are packaged with other chips. Some are heat and pressure sensitive, and because it’s difficult to test these devices there is no simple way to determine reliability.
• The competition for many of these devices is too high to warrant more investment, but the process of creating these chips can be slow and expensive. That disconnect limits innovation both in the process and in the MEMS devices themselves.
Tomi Engdahl says:
New tinyAVR® MCUs Increase System Throughput While Lowering Power Consumption in Embedded Applications
https://www.microchip.com/en/pressreleasepage/new-tinyavr-mcus-1617?utm_source=Facebook&utm_medium=Social&utm_term=FY17Q4&utm_content=MCU8&utm_campaign=Post
Microchip Continues Expansion of AVR Microcontroller Product Line with
Addition of Three New tinyAVR Devices
Tomi Engdahl says:
560V Input, No-Opto Isolated Flyback Converter
http://www.linear.com/solutions/7334?utm_source=DN559&utm_medium=customnl&utm_campaign=EEWeb
a flyback converter with a wide input range from 20V to 450V
The LT®8315 is a high voltage flyback converter with an integrated 630V/300mA switch. The LT8315 eliminates the need for an opto-coupler, complicated secondary-side reference circuitry, additional start-up components, and an external high voltage MOSFET.
In standby mode, the LT8315’s preload is usually less than 0.1% of full output power, the quiescent current is lower than 100μA—important for applications requiring high efficiency in always-on systems.
The LT8315’s high voltage input capability is easily applied in nonisolated solutions. Nonisolated converters do not require the transformer of an isolated converter, instead adopting a relatively inexpensive off-the-shelf inductor as the magnetizing component.
The LT8315 operates at a wide input voltage range of 18V to 560V, delivering up to 15W of isolated output power. It requires no opto-coupler, and includes rich features such as low ripple Burst Mode® operation, soft-start, programmable current limit, undervoltage lockout, temperature compensation, and low quiescent current.
Tomi Engdahl says:
TE Connectivity unveils ‘Sliver’ internal cabled interconnects for DC servers, switching, routers, storage up to 25G
http://www.cablinginstall.com/articles/2017/03/te-sliver-dc.html?cmpid=enl_cim_cimdatacenternewsletter_2017-03-14
TE Connectivity (TE), a specialist in connectivity and sensors, recently announced the launch of its new Sliver internal cabled interconnects, which the company says “provide one of the most flexible solutions in the market for making internal input/output (I/O) connections on the board.” According to TE, “this new technology simplifies design and helps lower overall costs by eliminating the need for re-timers and costlier, lower-loss printed circuit board (PCB) materials, while reaching speeds up to 25 gigabits per second (Gbps) with the use of TE high speed cable.
“Our new Sliver internal cabled interconnect system has been enthusiastically adopted by our initial customers as a solution to data rate increase challenges,” commented Melissa Knox, product manager of Data and Devices at TE Connectivity. “It is a flexible, robust, and cost effective connector and cable assembly solution providing improved performance and extended reach while also saving space and lowering design costs for a range of data rate signals within data networking applications.”
“TE’s Sliver products can be used across many applications, data rates, and protocols (including PCI Express, SAS, and Ethernet). There are several interconnectivity options, including chip-to-chip, board-to-board, chip-to-front panel I/O, and high-speed card edge. It is a scalable platform that can be extended in increments of eight differential signal pairs for convenient and efficient pin configurations.”
“The new Sliver internal cabled interconnects also solve the design challenge of making products as small as possible with a 0.6mm contact pitch.”
Sliver Internal Cabled Interconnects
http://www.te.com/global-en/products/connectors/rectangular-connectors/mid-board-copper-connectors.html
0.6mm contact pitch
Receptacle includes robust metal shell with cable latching
Vertical and Right Angle receptacle options accepts Sliver cable assemblies or PCB plug-in cards
Cable assemblies incorporate our high-speed, low-loss 33 AWG cable and can support both 85 and 100 ohm environments
12G & 25G options provide economic solutions for a variety of applications
Tomi Engdahl says:
Power Impacting Cost Of Chips
The cost of designing a power delivery network is rising, and that’s not likely to change.
http://semiengineering.com/power-impacting-chip-profits/
The increase in complexity of the power delivery network (PDN) is starting to outpace increases in functional complexity, adding to the already escalating costs of modern chips. With no signs of slowdown, designers have to ensure that overdesign and margining do not eat up all of the profit margin.
The semiconductor industry is used to problems becoming harder at smaller geometries, but until recently power was rarely viewed as an extraordinary expense.
“In the good old days, before 130 and 180nm, the power grid usually was an afterthought and people did not even spend a lot of time to look at IR drop,” says Jerry Zhao, product management director, power signoff at Cadence. “People now spend more time to close power than timing because there are so many variables.”
A lot has changed in that time. “From being a non-issue, designers started to realize the issues surrounding power integrity,”
How we got to this point
The power delivery network started life as an almost invisible part of the infrastructure of a chip and had negligible impact on power, performance and area (PPA). “Back in the ’90s the chip power ‘plumbing’ was implemented according to rules of thumb, and the sign-off check was about connectivity,” says Bjerregaard. “I’ve heard of one or two ASIC engineering runs that failed simply because power or ground pins were not electrically connected.”
But most of the problems were solved by using more wires for the PDN, which was not a great concern because metal layers were being added.
So the PDN got more complex because it used more wires.
In fact, according to TSMC, the resistance of metal layers has doubled between the 40nm and 7nm nodes.
Analysis became essential. “In the ’00s, power integrity sign-off with dedicated IR drop analysis tools – static at first, then dynamic – became the norm,” says Bjerregaard. “There were specific voltage drop criteria to meet, that could be specified as 10% static/17% dynamic voltage drop. As long as you were within the margins, you were fine.”
But even then, timing and power became interrelated. “Timing constraints were impacted by voltage drop, so they had to create margins,” says Zhao. “When the voltage drops, you have to consider what happens to the clock.”
“Supply noise hurts the clock by creating jitter. Jitter is important because it reduces timing margin and can limit the speed of logic circuits, or even cause them to fail.”
The problem space continues to grow. “Inductance (L) became important from a system-level perspective,” adds Brad Brim, senior staff product engineer at Cadence. “It is not just the inductance of the package. Coupled with the die capacitance, it can cause resonance, and that causes things such as droop. For FPGAs or large processors, it was not just the inductance but the amplitude of the current plus the di/dt. So whenever you had high switching activity and really high currents, that is when the L came into play.”
As current density increase, additional problems come into play. “Electromigration (EM) gets more severe as you get down in node geometry,” says Zhao. “This affects the reliability of the chips.”
Self-heating is another problem created by the 3D structure of the finFET. Heat is trapped inside the transistor and it heats the wires above it.
The situation today
Today, at 10nm and 7nm, things are coming to a head. “Power is now deeply entangled with everything,” says Bjerregaard. “Metal has become a scarce resource because routability is determining area, and so designers are scrambling to achieve the desired area utilization. At the same time, more metal is needed in the power grid to accommodate the increasing power density. In addition, on-chip decaps cannot solve the problems as they are getting less effective and have shorter reach.”
Power switching adds another layer. “You needed to make sure that the inrush current would not break the network, especially the blocks close to the ones that are switching,”
Tighter integration between the analysis and implementation tools has enabled designers to analyze the complex interdependency between power, voltage drop and timing. “Accurate power and IR drop analysis enable optimal power grid design without over-design,”
Tomi Engdahl says:
Satisfy Today’s Spectrum Emissions Demands
http://mwrf.com/commercial/satisfy-today-s-spectrum-emissions-demands?NL=MWRF-001&Issue=MWRF-001_20170316_MWRF-001_7&sfvc4enews=42&cl=article_2_b&utm_rid=CPG05000002750211&utm_campaign=10136&utm_medium=email&elq2=63ac9d3ac43f47118f96b19f4d2db27f
Meeting complex spectrum emissions standards requires test solutions that can effectively perform intermodulation distortion (IMD) and RF interference measurements. The signal analyzer lies at the heart of many of these test solutions.
The brief lists three steps that should be followed when making compliance-based spectrum emissions measurements. The first step is to simply select the correct signal analyzer.
Another key aspect is to have wide digitizing bandwidths.
For wireless spectrum emissions measurements, one must consider a number of parameters. These include spurious-free dynamic range (SFDR), IMD, frequency range, and sensitivity. In addition, measurement applications must accommodate the standards of interest. Analysis bandwidth can also be significant in terms of making fast adjacent-channel-power-ratio (ACPR) measurements, as well as locating time-varying spurious emissions.
The second step is to optimize the signal analyzer—correctly setting its attenuation value, for instance. Furthermore, when selecting the resolution bandwidth (RBW), it should allow for a sufficient displayed average noise level (DANL).
The final step involves finding and measuring time-varying spurious and RF interference signals. Real-time spectrum-analysis (RTSA) capability enables signal analyzers to discover and measure these signals.
Tomi Engdahl says:
Qualcomm doesn’t want you to call its Snapdragon processors ‘processors’ anymore
https://opensource.com/article/17/3/operate-relays-control-gpio-pins-raspberry-pi?sc_cid=7016000000127ECAAY
Take note, tech writers: as of this morning, Qualcomm’s Snapdragon processors are no longer processors. Henceforth, the company would like you to refer to Snapdragon as a “platform.” In a post this morning, the San Diego-based chip – sorry processor – maker has detailed why it’s replaced one p-word with another. And why it thinks you ought to, too.
Tomi Engdahl says:
Qualcomm Tweaks Snapdragon Brand: No Longer a Processor, Instead a Platform
by Ryan Smith on March 16, 2017 9:00 AM EST
http://www.anandtech.com/show/11204/qualcomm-tweaks-snapdragon-brand-now-platform
While all eyes are on Qualcomm for the impending release of devices containing their high-end Snapdragon 835 SoC, this morning the company has a slightly different kind of announcement to make. After nearly a decade since the launch of the Snapdragon brand, Qualcomm is undergoing a brand redesign of sorts ahead of their next-generation product launches. Starting today, Snapdragon is no longer a processor; instead Snapdragon is a platform.
More formally, Qualcomm will no longer be referring to Snapdragon as the “Snapdragon Processor”, but rather the “Qualcomm Snapdragon Mobile Platform”. Meanwhile at the bottom end of the product stack, the Snapdragon 200 series are getting ejected from the Snapdragon family entirely; they will now simply be part of the “Qualcomm Mobile Platform” family.
This rejiggering of brand names is, in all seriousness, exactly as weird as it sounds. But Qualcomm has some reasonably thought-out logic behind it.
However Qualcomm wants to emphasize that a Snapdragon SoC is more than its CPU. It is a collection of various bits and bobs: a CPU, a GPU, a DSP, a cellular modem, RF transceivers, not to mention the various pieces of software and drivers that Qualcomm develops for their SoCs. Consequently, Qualcomm feels that “platform” is a better all-encompassing word of what they do than “processor”.
The risk for Qualcomm, besides any potential derailment of the Snapdragon brand, is that “platform” is badly overused across the tech industry these days. Windows is a platform, Twitter is a platform, Steam is a platform. Whereas “processor” was a generic term for a specific part of a computer, “platform” is a generic term for just about any kind of computing environment. So while platform is probably a better fit for an SoC, it’s definitely also more generic.
Tomi Engdahl says:
Inside Lithography And Masks
http://semiengineering.com/inside-lithography-and-masks/
Experts at the table, part 1: EUV’s viability still in doubt even as rollout begins. Uptime and cost are top concerns.
SE: What are some of the big challenges from your vantage point?
Fried: At the highest level, what I’m concerned about is the volume driver for any of these technologies. For most of our lives, we knew we were going to do the next technology. We knew why. Then you built it and you had customers. Right now, most people can’t see too far past 7nm, which is what we are all working on. Nobody really knows what is going to fill the fab at 7nm.
Levinson: I have a couple areas of focus. One is trying to finally get EUV lithography into high-volume manufacturing. As an industry, we are going to do it. But it’s going to be painful. And it’s often just the mundane things. For example, there’s equipment reliability. When you are in manufacturing and your tool is down a lot, that’s a very painful place to be. Regarding 5nm and beyond, there are issues at the device level. There are problems with the interconnects. I can make contacts that are so small, and you can fill it with the best metal available. They are still too resistive for anybody to use.
McIntyre: From a litho/EUV perspective, one of the challenges will be to not get complacent and assume EUV is a done deal. One of the more exciting things about this year compared to last year is that the plan really hasn’t changed. We are still on the same trajectory for the insertion of EUV in the 2018 time period, sort of late into 10nm/7nm, and certainly the workhorse for N5. But by far, it’s not a done deal yet.
McIntyre: There are multiple tools out there that are fairly stable, operating at the 125ish-watt range. There are demonstrations above 200 watts. There seems to be a pretty good path in terms of getting to something above 200 watts by the time it gets inserted in HVM.
Hayashi: On the mask side, we need to obtain inspection capabilities. It’s quite difficult to detect all defects. If we can’t detect them, they may end up getting printed on the wafer.
Fujimura: EUV also needs multi-beam mask writing. Fortunately, multi-beam mask writing is ready. That is a great opportunity to take advantage of the things we couldn’t do before. It is needed, particularly for EUV. In EUV, you don’t have double patterning yet.
SE: EUV tool availability is also an issue. On average, the availability or uptime for the current EUV tools in the field is somewhere around 75% or so, although the percentage continues to improve. I assume that is an issue, right?
Levinson: If you are going to do manufacturing, you have to be able to do things in a predictable fashion, so you can go to your customer and say: ‘I will have this many parts ready for you on this date.’
SE: So what are some of the considerations in putting EUV into production?
Levinson: What people will do, of course, is buy enough tools to have redundancy and to get by. But that’s a very expensive proposition.
Fried: I take a pragmatic technology definition approach to where EUV comes in. I agree with the overall assumption that 7nm is the insertion point. But 7nm is the insertion point as an optical replacement. You do not define 7nm based on the capabilities of EUV. You define 7nm for optical with multi-patterning. Where you can insert EUV, you knock out multi-patterning modules. So, you don’t actually take advantage of EUV for anything other than a process cost savings.
Fujimura: The thesis is that it would it be cost-effective to use EUV. The industry knows that the investment in EUV is for the future. And even if doesn’t happen at the next node, it has to happen at the next node after that, and so on.
McIntyre: I agree with one assertion—inserting 7nm with EUV as is, in effect, is more or less a cost savings. Certainly, the next stage could be to really define a node so it takes advantage of EUV.
Tomi Engdahl says:
TFETs Cut Sub-Threshold Swing
http://semiengineering.com/reducing-subthreshold-swing-with-tfets/
Devices are still experimental, but they could solve power issues in scaling.
One of the main obstacles to continued transistor scaling is power consumption. As gate length decreases, the sub-threshold swing (SS) — the gate voltage required to change the drain current by one order of magnitude — increases.
As Qin Zhang, Wei Zhao, and Alan Seabaugh of Notre Dame explained in 2006, SS faces a theoretical minimum of 60 mV/decade at room temperature in conventional MOSFETs. This limitation has helped to drive interest in tunneling field effect transistors (TFETs), among other alternative designs.
In a TFET, a thin dielectric layer rather than a conventional channel lies between the source and drain. The applied gate voltage controls the overlap between the valence band of the material on one side of the dielectric, and the conduction band of the material on the other side.
In the “off” state, there is no overlap and no current flows. In the “on” state, the gate bias pulls the valence band on one side up to the level of the conduction band on the other side.
Building TFETs with low SS and enough tunneling current is not easy, though.
Defects are especially problematic in materials other than silicon.
Semiconductors with narrower band gaps, such as germanium and III-V compounds like InAs, also have much less mature manufacturing processes. TFETs based on III-V semiconductors may need 40 to 100X lower trap density relative to the current state of the art in order to achieve a reasonable “on/off” current ratio with steep subthreshold swing.
As the diversity of proposed devices shows, TFETs are extremely immature, experimental devices at this time. Nonetheless, even these preliminary results suggest that they may offer the industry a way out of its power consumption dilemma.
Tomi Engdahl says:
ODB++ can take a lot of cost, time delay, and quality risk out of the PCB design-to-manufacturing transfer. By eliminating the need to work with multiple low-level files between PCB design and manufacturing, data manipulation is reduced, and the fabrication and assembly process engineering work can begin faster and at a more automated level.
ODB++
https://en.wikipedia.org/wiki/ODB%2B%2B
ODB++ is a proprietary CAD-to-CAM data exchange format[1] used in the design and manufacture of electronic devices. Its purpose is to exchange printed circuit board design information between design and manufacturing and between design tools from different EDA/ECAD vendors.[2] It was originally developed by Valor Computerized Systems, Ltd. (acquired in 2010 by Mentor Graphics[3]) as the job description format for their CAM system.
ODB stands for open database,[4] but its openness is disputed
When in use, ODB++ data is stored in a hierarchy of files and file folders.[13] However, for transmission it is convenient to use common operating system commands that create a single, compressed file that preserves the hierarchy information. For example, on Unix tar and gzip commands can be used.[2] In ODB++(X), the database is contained in a single XML file by default.[9]
ODB++ covers the specification of not only conductor layer artwork and drill data, but also material stack up, netlist with test points, component bill of materials, component placement, fabrication data, and dimension data.
Tomi Engdahl says:
Patterning Problems Pile Up
Edge placement error emerges as the top issue at advanced nodes.
http://semiengineering.com/patterning-problems-pile-up/
Chipmakers are ramping up 16nm/14nm finFET processes, with 10nm and 7nm now moving into early production. But at 10nm and beyond, chipmakers are running into a new set of problems.
While shrinking feature sizes of a device down to 10nm, 7nm, 5nm and perhaps beyond is possible using current and future fab equipment, there doesn’t seem to be a simple way to solve the edge placement error (EPE) issue.
EPE basically is the difference between the intended and the printed features of an IC layout.
EPE basically is the difference between the intended and the printed features of an IC layout. It involves patterning of tiny features in precise locations. For example, a feature could be a line, and that line has right and left edges. But in a device, the line and its edges must be precise and placed in exact locations. Then, a contact may land on that line in the device. If these are not precise and exact, that results in misalignment, or an EPE. And if one or more EPE issues crop up in the production flow, the device is subject to shorts or poor yields, which could cause the entire chip to fail.
“That’s really what gates Moore’s Law,”
EPE sounds trivial, but the challenges are escalating and piling up at each node. The problems are caused by a host of issues in the fab.
“The total error budget has gone up because we’ve added a lot of process steps. So, we get difficulties in scaling because we can’t place the features exactly where we want them anymore.”
It’s still possible to pattern the features in exact places at advanced nodes, but the process becomes more expensive and difficult.
What is EPE?
Nearly two decades ago, lithographers devised a term called edge placement error, which involves several arcane patterning and metrology concepts. But the topic began to heat up at the 22nm/20nm logic node, when chipmakers moved from single to multiple patterning techniques in the fab.
Today, chipmakers use 193nm wavelength lithography to print features on a wafer. In reality, though, 193nm lithography reached its limit at 80nm pitch or 40nm half-pitch.
To extend 193nm lithography at 20nm and beyond, chipmakers moved from single patterning to multiple patterning.
In multiple patterning, “the original mask shapes are divided between two or more masks,”
“Each mask is then printed separately, eventually imaging the entire set of originally-drawn shapes onto the wafer.”
Multiple patterning enables the industry to extend IC scaling, but it also increases the complexity. A 28nm device has 40 to 50 mask layers. In comparison, a 14nm/10nm device has 60 layers, with 7nm expected to jump to 80 to 85. 5nm could have 100 layers.
On top of that, the device has migrated from a planar to a 3D-like finFET structure starting at 22nm, a move that presents several new and difficult challenges in the fab, namely patterning.
Tomi Engdahl says:
The proximity is important to R & D
the proximity of important R & D
News
- 03/21/2017
A study carried out at Aalto University, the companies want to produce technologically demanding products close to the product development. On the other hand the manufacturing of a standardized, the farther away from production is transferable.
The centralized operating model, most of the breeding value of the product remains in Finland. choice of manufacturing location still affected by other factors than price – is often the case of mutual dependencies between the company’s operations.
“If the market or product development intimacy are important aspects of the company, invested in manufacturing is likely the company’s home country, or very close to it,” says postdoctoral researcher Timo Seppälä Aalto University and the Research Institute of the Finnish Economy Etlasta.
“Many companies often end up manufacturing to China to invest, because there’s all been so affordable. On the other hand, President Trump has outlined the return of all manufacturing to the United States. ”
Source: http://www.uusiteknologia.fi/2017/03/21/tuotekehityksen-laheisyys-tarkeaa/
Tomi Engdahl says:
ARM unveils Dynamiq multicore chip designs for faster AI and cloud computing
http://venturebeat.com/2017/03/20/arm-unveils-dynamiq-multicore-chip-designs-for-faster-ai-and-cloud-computing/
Chip design firm ARM has unveiled its Dynamiq technology to make better multicore processors that can handle artificial intelligence, cloud computing, and new kinds of devices.
Cambridge, England-based ARM said in a press call that the new designs (ARM designs chips and its partners incorporate them into their own manufactured chips) will be available in ARM Cortex-A processors coming to market later this year in automotive, networking, server, and “primary compute devices.”
The new processors will enable flexible multicore processing — in which a computing device has to juggle many different tasks of varying sizes at once. It will also emphasize “heterogeneous compute,” or using different kinds of cores or processors in the same machine
ARM considers Dynamiq to be the biggest micro-architectural shift since ARM announced its 64-bit computing architecture in 2011. In the next five years, ARM estimates that its chip partners will ship 100 billion chips, compared to 50 billion chips shipped in the past five years.
Tomi Engdahl says:
Tiny liquid battery cools chips while powering them
The “flow” battery could be used in solar cells that store their own power.
https://www.engadget.com/2017/03/20/tiny-liquid-battery-cools-chips-while-powering-them/
cientists from IBM and ETH Zurich university have built a tiny “flow” battery that has the dual benefit of supplying power to chips and cooling them at the same time. Even taking pumping into account, it produces enough energy to power a chip while dissipating much more heat than it generates. The result could be smaller, more efficient chips, solar cells that store their own energy or devices used for remote monitoring that don’t require external power sources.
“Redox flow” batteries that use liquid electrolytes are normally used on a large scale to store energy. For instance, Harvard Researchers recently created one that can last over ten years with very little degradation, making it ideal to store solar or wind energy.
Tomi Engdahl says:
Challenges Grow For IP Reuse
http://semiengineering.com/challenges-grow-in-ip-reuse/
Methodologies for integration become a competitive tool as complexity and possible options skyrocket.
As chip complexity increases, so does the complexity of IP blocks being developed for those designs. That is making it much more difficult to re-use IP from one design to the next, or even to integrate new IP into an SoC.
What is changing is the perception that standard IP works the same in every design. Moreover, well-developed methodologies for reuse can give a chipmaker a competitive advantage. The final shape of the design depends on various factors, such as application demand, and interfacing or power requirements, all of which increase the number of possible configurations.
There are numerous efforts underway to help minimize those challenges, including standard protocols like AMBA AXI or ways to tie them together with an on-chip interconnect.
Tomi Engdahl says:
Users Talk Back On Standards Process
http://semiengineering.com/users-talk-back-about-standards-process/
How does a standard get created? A lot of hard work and balancing different opinions can be frustrating, but that communication is vital.
Tomi Engdahl says:
The current development of integrated circuits terminated in 2024
IRDS or International Roadmap for Devices and Systems have called IEEE Circuits report drawn up by the development of the road, or roadmap. The organization plans to announce the first official IRDS report next November. It is, however, trickled preliminary data, for example in the form of technical documents. According to them, the current circuits and the development of a smaller scale of the ends around the year 2024.
The forecast would mean in practice that Moore’s Law would cease to exist. The reason for this is the interaction of the physical structures of circuits so small that a smaller scale a silicon-based chips, no longer possible.
There are currently going through the first 11 or 10-nanometer steps in logic circuits. In 2019, the process is changed to 8 or 7 nm, and in 2024 already four or three nanometers. In this case, the logic circuitry transistor gate of the physical width is only 10 nanometers, when it is at the moment the most advanced circles is 24 nanometers.
In practice, the circuit connections will three or four nanometers so small that the parasitic phenomena prevent their reliable operation.
Development does not mean the end of the electronics. Instead of silicon, and the end of the era of CMOS process, it means yes.
Source: http://www.etn.fi/index.php/13-news/6061-nykyisten-mikropiirien-kehitys-paattyy-2024
Tomi Engdahl says:
IRDS Reports
http://irds.ieee.org/reports
Tomi Engdahl says:
Quantum phenomena in semiconductor packages
University of Kansas researchers are experimenting with electrons quantum movement between different atomic layers. They can give rise to new kinds of electronics and photonics applications of van der Waals materials.
The researchers sample contains layers MoS2-, WS2- and MoSe2 materials. All three are semiconductor materials and react to light in different colors.
Results shows potential applications of van der Waals materials for electronics and photonics.
- The electrons can appear on the first floor, then on the third floor, without ever visiting the second floor, says University of Kansas Hui Zhao. His group has just detected the electrons against such common sense movement of the laser research in the laboratory experiments at the University.
According to Zhao’s verification of quantum transport of electrons, coupled with van der Waals forces between the atomic layer is encouraging news to researchers. It allows them to develop new materials.
These so-called. van der Waals materials can be optionally used in the future, for example in solar cells and in electronics.
Sources:
http://www.etn.fi/index.php/13-news/6064-kvanttiliiketta-atomikerrosten-valilla
http://www.uusiteknologia.fi/2017/03/24/kvantti-ilmioita-puolijohdepaketeissa/
Tomi Engdahl says:
Waveguide Has Many Miles to Go
Waveguide technology has been written off as obsolete for some time, but nothing has replaced it yet.
http://mwrf.com/components/waveguide-has-many-miles-go?NL=MWRF-001&Issue=MWRF-001_20170323_MWRF-001_840&sfvc4enews=42&cl=article_1_b&utm_rid=CPG05000002750211&utm_campaign=10251&utm_medium=email&elq2=44db245241fd4dcc9c886143fd12f0cc
Waveguide suppliers are truly the “old-timers” of the RF/microwave industry, selling a transmission-line technology that most users would rather replace with something newer. For all its bulk compared to an alternative, such as a coaxial cable with connectors, waveguide is still the lowest-loss way to get a high-frequency electromagnetic (EM) signal from point A to point B. And it does get smaller as the frequency pushes higher.
Manufacturers of metal waveguide have been likened to blacksmiths working in a forge
this is a technology that many have predicted would soon vanish, but it is still here, and still in demand.
Millimeter-wave frequencies may be a best friend to metallic waveguides, mainly because coaxial cables—those lighter-in-weight, lower-cost transmission-line alternatives to waveguide—tend to suffer higher losses at higher frequencies, notably at millimeter-wave frequencies above 30 GHz.
Some impressive advances have been made in coaxial-cable and connector technologies over the past decade. They include relatively phase-stable, low-loss cables with connectors commercially available for applications to 110 GHz, such as for connection to a millimeter-wave vector network analyzer (VNA).
In terms of performance, waveguide has extremely low signal losses and reflections, with very little distortion of signal phase—a critical characteristic for phase-modulated communications signals. Waveguide is completely shielded compared to other transmission-line formats
Waveguide are also traditionally more expensive than other transmission-line formats, including microstrip and stripline on printed-circuit boards (PCBs).
Waveguide are fabricated entirely of conductors, such as copper.
Waveguide also tend to be manufactured in smaller quantities
Nonetheless, waveguide appear to be growing in popularity, most likely due to the growth of applications at millimeter-wave frequencies. The 60-GHz band has provided reliable, short-range unlicensed communications links at multi-gigabit data rates using traditionally expensive waveguide components. Such links are often referred to as “the last mile” in communications systems.
Developed and supplied by Pasternack, the waveguide transmitter is tunable from 57.0 to 64.8 GHz.
However, even at lower frequencies, there is sometimes a demand for waveguide components. The 24-GHz band is also an unlicensed portion of the frequency spectrum that is used for radar and communications applications.
The waveguide Gunn oscillator (model FMWGN1001) generates a signal at a center frequency of 24.125 GHz, which can be tuned by 1 GHz above and below that center frequency.
Waveguide technology may be a means of achieving that “last mile” of wireless communications at 60 GHz, and a part of 77-GHz automotive radar systems,
Tomi Engdahl says:
The first single-molecule switch
University of Konstanz, a German research team has succeeded for the first time to develop a single-molecule switch. The researchers describe molekyyliään synthesized as a three-legged spaceship landed on the moon.
Theoretical physicists Fabian Pauly and Safa G. Bahoosh managed together with experimental physicists and chemists to demonstrate a reliable one molecule carried out in the switch, the operation of which is reliably reproducible. The solution is based on the synthesized molecule, which has special properties.
Nitrile electric dipole moment that is a plus-minus reservation makes it possible to control the mechanical, but it also allows the control of electric fields. Field targeting the positive end of the molecule is pressed down and a negative it moves upward.
Source: http://www.etn.fi/index.php/13-news/6052-ensimmainen-yhden-molekyylin-kytkin
Tomi Engdahl says:
Flex circuits: Innovations and processes
http://www.edn.com/electronics-blogs/all-aboard-/4458173/Flex-circuits–Innovations-and-processes
Flex PCBs have been a key enabler of modern high density electronics, but achieving this density requires thinner layers and finer lines. Conventional three-layer flex circuits comprised of copper, polyimide, and bonding adhesives are giving way to thinner, smoother two-layer flex circuits that forego the adhesive layer – the copper is instead deposited directly on the polyimide. These two-layer circuits may be as thin as 30 µm, with line spacing as fine as 15 µm (0.6 mils). It’s imperative, therefore, that the processed panels are handled extremely carefully to avoid causing wrinkles, tension, or scratches.
The inherent physical delicacy of flex circuits poses some key manufacturing challenges that can negatively affect yield and potentially impact a design’s viability. These challenges are being addressed by flex-supporting technologies that enable large-scale FPC (flexible printed circuit) production while ensuring quality yield and output. More flex circuit suppliers are adopting advanced flex manufacturing techniques to enhance manufacturing efficiency, improve yield, and maintain low costs and market competitiveness.
Production design and manufacturing of FPCs is different from rigid PCBs
Special design for manufacturing (DFM) software tools for flex circuits help neutralize production problems during the design stage. These advanced tools are used to fully automate manual editing sessions, reducing errors and critical cycle time.
Laser drilling and routing are common in flex printed circuit production. Ultra-violet laser drilling technology is utilized in high-density flex manufacturing to drill vias under 70 µm directly through the copper and polyimide layers.
To date, advanced flex circuit suppliers have relied primarily on laser direct imaging (LDI) equipment to use with their sheet-based imaging for double-sided flex, rigid flex, and multi-layer flex materials.
The majority of FPC products are either double- or single-sided. Traditionally, these did not always undergo AOI inspection. In the past five years, fine-line flex has become a major part of the smartphone interconnect, resulting in integrated device manufacturers demanding higher quality control of the single- and double-sided FPCs, and making AOI-level inspection mandatory.
Polyimide base material is transparent and presents an inspection challenge.
Tomi Engdahl says:
OFC Debates Road to Photonic ICs
European collaboration fabs 350+ InP devcies
http://www.eetimes.com/document.asp?doc_id=1331512&
Electronic and optical components are destined to merge, but the annual OFC event revived the debate over whether silicon photonics (SiP) or indium phosphide (InP) is the best path.
An academic researcher helping to develop a foundry ecosystem for photonics in Europe made the case for InP in a keynote. But several analysts said that SiP will more likely be the winner.
Electronic and optical components are destined to merge, but the annual OFC event revived the debate over whether silicon photonics (SiP) or indium phosphide (InP) is the best path.
An academic researcher helping to develop a foundry ecosystem for photonics in Europe made the case for InP in a keynote. But several analysts said that SiP will more likely be the winner.
However, Smit admits that SiP has lower costs given supporters such as Intel with access to large 8-in. wafer fabs. “It’s a complex picture, and there’s no single solution for all … [In the end], InP with silicon electronics and SiP may work together,” he said.
Tomi Engdahl says:
Samsung Edges TSMC in 10 nm
http://www.eetimes.com/document.asp?doc_id=1331504&
Samsung appears to be about a quarter ahead of Taiwan Semiconductor Manufacturing Co. (TSMC) with the ramp of 10-nm process technology, according to a veteran chip analyst.
Earlier this year, Samsung and TSMC said that they would launch 10-nm foundry services during the second quarter this year for customers such as Qualcomm, Mediatek, and Huawei’s semiconductor subsidiary, HiSilicon.
Somewhat ahead of schedule, Samsung last week announced that it has shipped 70,000 wafers of 10-nm LPE (low-power early) chips, independent analyst Andrew Lu noted in a report for intelligence provider Smartkarma.
“The 10-nm schedule for Samsung seems to be ahead of TSMC’s 10-nm ramp-up for MediaTek (after numerous design-win cancellations by MediaTek’s 10-nm customers) and Huawei/HiSilicon,” Lu said in the report. Previously, it was widely believed that TSMC was ahead of the competition, according to Lu.
Tomi Engdahl says:
TSMC Tips 7+, 12, 22nm Nodes
http://www.eetimes.com/document.asp?doc_id=1331489&
Trying to cover the waterfront, TSMC disclosed plans for new high-, mid- and low-end processes at an annual event here. They included an enhanced 7nm FinFET node using extreme ultraviolet lithography, a 12nm upgrade of its 16nm process and a 22nm planar technology — its answer to fully depleted silicon-on-insulator (FD-SOI).
The foundry also described enhancements to its two chip-stacking techniques, advances in RF CMOS and work in transistors and materials, paving the way to a 3nm node and beyond. In addition, it previewed design capabilities using machine learning that it will offer before the end of the year.
Among its achievements, TSMC noted 76 percent yields on the 256Mbit SRAM made in its first-generation 7nm node, which will be in volume production next year. It also reported that an ARM Cortex-A72 processor in the node exceeded 4GHz using a new design flow.
TSMC has taped out nearly 800 chips using flavors of its 28nm process. It has shipped 4.5 million 28nm wafers to date, clearly a big sweet spot it aims to defend.
Globalfoundries hopes to capture many of those customers starting this year with 22nm FD-SOI, a lower cost, lower power alternative with similar performance to TSMC’s 16nm FinFET node. TSMC claims its 22nm process provides an easier migration path from 28nm while FD-SOI requires redesigned intellectual property cores.
“Bulk semiconductor technology has been enhanced for 30 years and is used by Intel and Samsung,”
TSMC’s Liu said the foundry expects 70 tape outs of IoT chips this year across its family of ultra-low power processes that range from 55 to 28nm. The 40nm ULP process has been characterized for near-threshold operation driving energy efficiency to 11 microamps/MHz, he said.
Tomi Engdahl says:
EDA Sales Jump Most in Five Years
http://www.eetimes.com/document.asp?doc_id=1331524&
Electronic Design Automation (EDA) sales posted in the largest annual increase in five years in the fourth quarter of 2016, based on broad strength across all product categories and regions, according to the Electronic System Design (ESD) Alliance.
Fourth quarter EDA sales totaled $2.46 billion, an increase of 19 percent compared to the fourth quarter of 2015, the ESD Alliance said. Sales increased by double digit percentages across all regions and most product categories, according to the data published by the organization.
Tomi Engdahl says:
OFC Debates Road to Photonic ICs
European collaboration fabs 350+ InP devcies
http://www.eetimes.com/document.asp?doc_id=1331512&
SAN JOSE — Electronic and optical components are destined to merge, but the annual OFC event revived the debate over whether silicon photonics (SiP) or indium phosphide (InP) is the best path.
An academic researcher helping to develop a foundry ecosystem for photonics in Europe made the case for InP in a keynote. But several analysts said that SiP will more likely be the winner.
TowerJazz Rolls Out Silicon Photonics Process
http://www.eetimes.com/document.asp?doc_id=1331515&
Specialty foundry TowerJazz Thursday (March 23) rolled out a silicon photonic (SiPho) process to complement its silicon-germanium (SiGe) BiCMOS process used for manufacturing optical transceiver electronics.
“We are excited to be entering the silicon photonics foundry space in order to provide solutions to a greater portion of the optical transceiver market for our customers,” said Marco Racanelli, senior vice president and general manager TowerJazz’s RF & High Performance Analog business unit, in a statement.
Silicon photonics is a promising emerging technology for the production of photonic ICs, which transfer data using laser light in less time than conventional ICs.
The silicon photonic process, set to be available in the third quarter, is built to enable a range of optical fiber interconnect Tx and Rx front-end optical ICs, TowerJazz said. The process includes several versions of single-mode silicon waveguides, high speed germanium photodetectors, p-n junction modulators and enablement for edge and grating couplers, according to the company.
Tomi Engdahl says:
Asian Tech Investment in U.S. May Rise
http://www.eetimes.com/document.asp?doc_id=1331503&
INDIANAPOLIS — Taiwan Semiconductor Manufacturing Co. (TSMC) and other Asian tech firms may contribute to a rising tide of investment in the U.S. in response to some expected Trump administration initiatives.
This week, TSMC reiterated comments from Chairman Morris Chang that the company may build a new U.S. fab as early as next year, possibly joining other global firms that are considering manufacturing in the U.S. amid President Donald Trump’s push to create more jobs.
Expected tax incentives and tightened regulations on sensitive U.S. technology by the Trump administration may help to attract more domestic investment from companies such as Apple and its Asian suppliers like TSMC and Foxconn, according to Dick Thurston, former chief counsel for TSMC.
Tomi Engdahl says:
Product Engineers Fill the Gap With Automated Tests
http://www.eetimes.com/author.asp?section_id=36&doc_id=1331519&
At Maxim Integrated, product engineers make sure new products are tested and ready for production.
My first job after earning my BSEE was in the product engineering department at Analog Devices. My first assignment was to evaluate a programmable-gain amplifier (PGA) module prior to production. At that time, we didn’t have automated measurement systems to measure and record the PGA’s output or power consumption. We had to take photos of waveforms, paste them into our notebooks, and record measurements by hand.
And we liked it that way.
Tomi Engdahl says:
EDA Revenue Up 18.9%
PCB and IP buoyed the healthy results for Q4.
http://semiengineering.com/eda-revenue-up-18-9/
Marking the highest quarterly revenue increase in 5 years, the Electronic System Design (ESD) Alliance reported today that EDA revenue increased 18.9 percent for Q4 2016 to $2.455 billion, compared to $2.0645 billion in Q4 2015. The four-quarters moving average was up by 9.2%, which compares the most recent four quarters to the prior four quarters.
Walden C. Rhines, board sponsor for the ESD Alliance MSS, and chairman and CEO of Mentor Graphics commented, “What’s really remarkable is if you look at the full year, the two fastest growing areas were printed circuit board design, and IP so it wasn’t driven, necessarily, by new, leading-edge technology adoption. If you look just at the fourth quarter, the impressive part is again, PCB — it’s way ahead of anything else in fourth quarter, but everything is really strong, and in double digits, for each product type.”
Tomi Engdahl says:
Supporting CPUs Plus FPGAs
http://semiengineering.com/supporting-cpus-plus-fpgas/
Experts at the table, part 1: What the toolchain looks like today and the different mindsets within those flows.
SE: Until recently, the CPU and the FPGA have been considered as two different application areas with two different flows, two different teams and almost a different thought process. Now we are seeing many applications where these two devices are coming together. What kinds of applications are we seeing this happen in?
Orthner: We are seeing a tremendous amount of acceleration in this area. Consider Amazon cloud, and Microsoft with Azure. I am seeing a lot of people getting interested in convolutional neural networks (CNN). That comes up again and again. At the recent FPGA conference in Monterey, probably half the conference was about that. I see applications such as SQL acceleration for people doing database applications, where you run the SQL through an FPGA on the way to your hard drive and you can do all kinds of filtering.
Allan: FPGA and ASIC technologies are overlapping increasingly in their design flows. There is less and less reliance on a technology-centric flow having one side for FPGAs and the traditional ASIC flow.
Burns: We see that too. We see a lot of experimentation, people looking for very high performance, very low power. They will measure power on the CPU, a GPU, and they may need to move to an FPGA or an ASIC. Deep learning, machine vision – all of these kinds of things need to have improved performance per Joule, and are looking for the most effective way to do that. On the FPGA you have much lower power than a GPU or CPU, so you can ask if you need to go to an ASIC and what does that look like.
Burns: This is a key measurement. How many Gigaflops per Joule does this algorithm consume? How many does it need to take? And what is my budget?
SE: What about design problems for this combination?
Schirrmeister: The design problems surface when you put together an FPGA and the rest of the SoC, which essentially may be an array of processors. You have two issues. First, how do you design that itself, which is one area of focus for our tools. And second, if you have a monolithic thing all on the chip, how do you balance the function you put into the processor system versus what you put into the FPGA fabric?
Tomi Engdahl says:
Biz Talk: ASICS
https://www.youtube.com/watch?v=leO8gABABqk
eSilicon CEO Jack Harding talks with Semiconductor Engineering about the future of scaling, advanced packaging, deep learning and security.
Tomi Engdahl says:
Can this SiPh transceiver technology satisfy the bandwidth-guzzlers?
http://www.electropages.com/2017/03/can-thi-siph-transceiver-technology-satisfy-the-bandwidth-guzzlers/?utm_campaign=&utm_source=newsletter&utm_medium=email&utm_term=article&utm_content=Can+this+SiPh+transceiver+technology+satisfy+the+bandwidth-guzzlers%3F
The constant demand for ever-increasing interconnect bandwidth in datacentres means single-mode optical transceivers will need to scale to Tb/s capacity and be tightly integrated with network switches.
For some years industry has been concerned as to whether it will be able to develop the technology to provide the bandwidth capability to meet the demands of the four big bandwidth-guzzling applications; the Internet of Things, cloud computing and data storage and transfer.
Nano-technology specialist Imec has recently demonstrated an 896Gb/s silicon photonics transceiver of just a few mm2, targeting future Tb/s optical links. Silicon photonics (SiPh) is seen as a potential technology platform that could cope with extremely demanding bandwidth and integration targets; including reaching beyond the 100Gb/s technology that is currently available.
The bi-directional 896Gb/s silicon photonics transceiver combines dense arrays of 56Gb/s Germanium-Silicon (GeSi) electro-absorption modulators and GeSi waveguide photo detectors with a multi-core fiber interface. It comprises arrays of 16 GeSi electro-absorption modulators (EAM) and 16 GeSi photo detectors (PD), implemented with 100µm channel pitch on a single silicon chip.
Tomi Engdahl says:
VTT flexible, roll to roll LED display
VTT says has made the first time ledikalvon to include flexible electronics for all manufacturing steps roll-to-roll technology. The demo is to demonstrate that the technology can be prepared that contain, for example, flexible printed electronics LED display very cost-effectively.
At present, all the intelligence, for example, wrist computers is a rigid substrate below the dial. Roll-to-roll technology, the electronics can be printed on the plastic or elastomeric films, with the advantages of thinness, lightness, ductility and transparency. After the LEDs of stacking printed electronics film can be further supremacy of the thermoplastic polymer or thermoplastic elastomers in injection molding.
Source: http://www.etn.fi/index.php/13-news/6072-vtt-taipuisia-ledinayttoja-rullalta-rullalle
Tomi Engdahl says:
Stationary Chargers for EVs — When Cost and Performance Matters
http://powerelectronics.com/charger-ics/stationary-chargers-evs-when-cost-and-performance-matters?NL=ED-003&Issue=ED-003_20170327_ED-003_512&sfvc4enews=42&cl=article_2_b&utm_rid=CPG05000002750211&utm_campaign=10298&utm_medium=email&elq2=e933b26a38e44ec99f8b12dbb9ac0930
More and more electric vehicle (EV) charging points are sprouting up along highways, byways, and driveways. As availability becomes less of an issue, EV owners are starting to look closer at this equipment’s reliability and the energy costs associated with charging. Equipment vendors have to respond.
Purely electric vehicles need to become more convenient for the public to embrace them wholeheartedly. Engineers will have to find ways to extend their range and rapidly charge empty batteries. It takes considerable charging power to deliver that much energy, that fast.
Home stationary chargers’ power is usually limited to the 22 kW dictated by the distribution grids for residential neighborhoods. Commercial charger stations may be connected directly to a public medium-voltage distribution network via a low frequency transformer, which increases power levels to 100 kW and beyond. In this case, more electrical power can mean faster charging.
A stationary charger unit typically consists of the power electronics, control circuitry, communication with the BMS (battery management system), and the user interface. Power electronics, in turn, consist of two parts, PFC (power factor correction) and the dc/dc converter
Tomi Engdahl says:
Products of the Week from APEC 2017
http://powerelectronics.com/power-management/products-week-apec-2017?NL=ED-003&Issue=ED-003_20170328_ED-003_906&sfvc4enews=42&cl=article_1_b&utm_rid=CPG05000002750211&utm_campaign=10311&utm_medium=email&elq2=11f6641828804432b61a53abc70dc3a6
Tomi Engdahl says:
Face-to-Face at APEC: Inside Murata’s Recent Acquisitions
http://electronicdesign.com/power/face-face-apec-inside-murata-s-recent-acquisitions?NL=ED-003&Issue=ED-003_20170328_ED-003_906&sfvc4enews=42&cl=article_2_b&utm_rid=CPG05000002750211&utm_campaign=10311&utm_medium=email&elq2=11f6641828804432b61a53abc70dc3a6
As electrical and electronic components become smaller and thinner, manufacturers are still looking to increase power efficiency via evolutions in semiconductors, packaging, passives, and more.
Many EEs know the Murata name, but Arctic Sand probably doesn’t ring a bell. Even if it did, the two seem like an unlikely match—a global component, module, and materials company and an MIT spinout that claims it’s going to revolutionize power conversion. Murata is probably most known for its capacitors, as it sells 1 trillion per year. When Murata purchased Peregrine Semiconductor at the end of 2014, however, it recast itself as a company with a strong semiconductor offering. Taken that way, the decision to combine Arctic Sand’s architecture with Peregrine’s process technology is a more obvious one.
According to Murata, combining Arctic Sand’s low-power semiconductors with its modular technologies will make it possible to provide integrated solutions with superior conversion efficiency in a range of low-power fields. For some hints, look at some of its recent movements, like combining its power business and putting effort into vertically integrated solutions from passives and packaging to semiconductors.
Tomi Engdahl says:
Semiconductor Outlook Lifted on Surging Memory Prices
http://www.eetimes.com/document.asp?doc_id=1331537&
A prominent semiconductor industry watcher has more than doubled its forecast for industry growth in 2017 on surging average selling prices (ASPs) for DRAM and NAND flash memory.
IC Insights Inc. Wednesday (March 29) said it now expects semiconductor revenue to increase by 11 percent this year due to a substantial upgrade to the forecasts for DRAM and NAND, which the market research firm now expects to grow by 39 percent and 25 percent, respectively. IC Insights had previously forecast that the chip market would grow 5 percent in 2017.
Market watchers generally agree that 2017 should be a year of moderate growth for the semiconductor market after the industry posted a surprise 1 percent increase in sales in 2016, but 11 percent is among the most aggressive predictions to date.
Tomi Engdahl says:
MaxLinear to Buy Exar for $700 Million
http://www.eetimes.com/document.asp?doc_id=1331534&
RF and mixed-signal IC vendor MaxLinear Inc. will acquire rival analog chip maker Exar Corp. for about $700 million in cash, the companies said Wednesday (March 29).
Tomi Engdahl says:
Automotive IC Vendor Ranking Stays Largely Unchanged
http://www.eetimes.com/document.asp?doc_id=1331530&
NXP Semiconductors maintained its leadership position in the automotive semiconductor market last year as a listing of top 10 vendors remained largely unchanged from the year before, according to Semicast Research.
NXP, whose acquisition of Freescale Semiconductor propelled it to the top of the automotive IC vendor ranking in 2015, held roughly 14 percent of the market in 2016, up from 13.6 percent in 2015, Semicast (London) said.
Tomi Engdahl says:
Learn From The Experts
How to maximize the value of prototyping.
http://semiengineering.com/learn-from-the-experts/
I attended the technical track with experts from ARM, NVIDIA, Intel and Synopsys, who talked about their experience in accelerating software development, hardware verification and system validation leveraging prototyping. Their papers and presentations were full of tips and tricks on how to maximize the value from prototyping.
The ARM presenters——both named Peter—explained how the ever-increasing complexity and density of the latest ARM CPU and GPU cores, in addition to the continual demands for improved time-to-market, requires new, improved and innovative verification, validation and debug techniques. They highlighted how increased adoption of prototyping helped ARM to shift-left their IP verification activities and thus provide higher quality IP to their customers.
If you ever wondered how to prototype latch-based designs, the Intel presenter, laid out a step-by-step approach on how to effectively overcome some of the challenges that latch-based designs have typically imposed on FPGA-based prototyping. He went over a case study explaining how Intel was now able to prototype their Atom CPU where originally they could only use an emulator.
Tomi Engdahl says:
Custom Chip Verification Issues Grow
No simple solutions to deal with market-specific requirements and advanced process node issues.
http://semiengineering.com/custom-design-verification-issues-rising/
With the transition to finFETs, design conditions have grown more intense. They now include a wider PVT range and less headroom.
As a result, electronic systems for applications such as mobile, consumer, and automotive increasingly are becoming more difficult to design due to the exacting performance requirements of these applications. This is particularly evident in custom design, including analog/mixed-signal (AMS) design, where interfaces and protocols used for each project are different.
“If the design is relatively simple, it’s not such a big deal,” said Zibi Zalewski, general manager of the hardware division at Aldec. “But when we approach SoC projects for ASICs, and recently FPGAs, it becomes important for current and future projects to keep with the standards, at least company-wise.”
Tomi Engdahl says:
Chip Industry Outlines Post-CMOS Research Focus
http://www.eetimes.com/document.asp?doc_id=1331541&
The Semiconductor Industry Association (SIA) trade group Thursday (March 30) set out a comprehensive list of research priorities for maintaining semiconductor technology innovation in years to come, as the era of conventional CMOS scaling draws to a close and engineers turn to new materials, manufacturing techniques, architectures and structures.
The SIA released a 73-page report, developed in conjunction with Semiconductor Research Corp. (SRC), which outlines 14 areas identified as key areas for research. This list includes items such as cognitive computing, interconnect technology, next-generation manufacturing and power management, among others. The report calls for “robust government and industry investments in new technologies beyond conventional, silicon-based semiconductors.”
Semiconductor Research Opportunities: An Industry Vision and Guide was written over a nine-month period by more than 70 contributors
https://www.semiconductors.org/clientuploads/Research_Technology/SIA%20SRC%20Vision%20Report%203.30.17.pdf
Tomi Engdahl says:
Analog Devices Buys Broadband Amplifier Vendor
http://www.eetimes.com/document.asp?doc_id=1331544&
Analog Devices Inc. (ADI) said Thursday (March 30) it acquired OneTree Microdevices Inc., a privately held supplier of gallium arsenide (GaAs) and gallium nitride (GaN) amplifiers for broadband networks. Financial terms of the deal were not disclosed.
ADI (Norwood, Mass.) said the acquisition of OneTree’s GaAs and GaN amplifier portfolio would enable ADI to support the complete signal chain for next-generation cable access networks.
“OneTree’s expertise aligns with ADI’s strategic focus on GaN technology and extends ADI’s broad portfolio of high performance, RF and microwave signal chain solutions for infrastructure, defense and instrumentation markets,”
Tomi Engdahl says:
4-ch Channel High Resolution Oscilloscope
https://www.eeweb.com/news/4-ch-channel-high-resolution-oscilloscope
Saelig Company, Inc. has launched the PicoScope 4444 High-resolution Differential Oscilloscope which features four true differential input channels and a range of accessories for measurements from millivolt to 1000 V CAT III applications. It has been designed specifically for making accurate voltage waveform measurements on circuits that are not ground-referenced, avoiding the dangers of equipment damage due to short circuits.
The PicoScope 4444 can facilitate differential voltage measurements in the presence of common-mode signals, with 14-bit resolution and 20MHz bandwidth on all four differential channels and 256MSa waveform capture memory. It is ideal for the precise analysis of complex waveforms ranging from biomedical sensors to current probes and 1000 V CAT III power distribution circuits.
The USB-powered PicoScope 4444 is available in two kits that include key accessorie
Tomi Engdahl says:
Qualcomm is now number one in the automobile chips
Semicast Research has published the automotive electronics component suppliers statistics for last year. Ranked first for about 30 billion dollar market rose NXP Freescale’s recent acquisition left the country. Now NXP’s already owned by Qualcomm, which increases to a car circuits, the number one name.
Qualcomm deal, and the division’s standard circuits launched a new Nexperia-at Semicast estimates that Qualcomm’s market share is currently about 13 per cent.
NXP’s market share was 14 per cent last year.
Infineon (10.7%)
Renesas (9.6%)
STMicroelectronics (7.6%)
Automotive electronics component suppliers list has long been stable.
Microchip is eighth largest market share of 2.9 percent (after purchase of Atmel)
Source: http://www.etn.fi/index.php/13-news/6101-qualcomm-on-nyt-ykkonen-myos-autopiireissa
Tomi Engdahl says:
Gallery: The Power Was Definitely On at APEC 2017
http://electronicdesign.com/power/gallery-power-was-definitely-apec-2017?NL=ED-003&Issue=ED-003_20170403_ED-003_708&sfvc4enews=42&cl=article_1_b&utm_rid=CPG05000002750211&utm_campaign=10439&utm_medium=email&elq2=346eb3475f05451b843a032a496b268c
This year’s APEC conference and exhibition, which took place in Tampa, Fla., showcased the latest in power electronics. Electronic Design was at the show to cover news and developments in products, applications, and technology. Many companies were showing gallium-nitride (GaN) reference designs and applications, but silicon carbide (SiC) also is increasingly being considered as a process technology—especially above 1200 V.
Among the applications driving the evolution of power electronics are datacenters, electric vehicles, and wireless charging.
Tomi Engdahl says:
Toshiba Shareholders OK Chip Unit Sale as Bidders Mount
http://www.eetimes.com/document.asp?doc_id=1331546&
Toshiba’s shareholders approved spinning off the company’s semiconductor business into a separate business at a special shareholder meeting Thursday (March 30), paving the way for a sale that could fetch up to $18 billion, according to reports.
Meanwhile, the number of reported bidders in the Toshiba chip business continues to mount, though most of the bidders are unconfirmed.
Japan’s Nikkei news service reported Friday that roughly 10 bidders have emerged in the sweepstakes to land the business, which is second only to Samsung Electronics in NAND flash sales. The bids include a $17.9 billion offer from Broadcom and U.S. private equity firm Silver Lake Partners, Nikkei reported.