Chip Market Brightens in 2017. The semiconductor industry may yet have been flat in 2016, but expects it is expected that the electronics industry rebounds in 2017, probably in the first half. Wall Streeter predicts return to 5% growth. Total IC business growth is expected to be around five percents for few years to come.There seems to several promises to this direction, especially in memory business. Chips Execs See Maturing Industry article says that pessimism about immediate revenue and R&D growth is a sign of a maturing industry.
Thanks to both rising prices and volume sales, the memory sector is expected to lead overall semiconductor sales growth. Sales of memory chips will increase 10% next year to a new record high of $85.3 billion, according to the latest report from IC Insights. NAND flash will grow almost as fast at 10% next year. The average annual growth rate for the memory market is forecast to be 7.3% from 2016-2021. Every year we need 5.6% more bits than previous year, and the unit prices are increasing on both DRAM and Flash.
There will be also other growth sectors. The data center will be the fastest growth segment next year, rising 10%, followed by automotive at 9% and communications at 7%. Consumer and industrial markets growing at about 4% in line with the overall industry. PCs will be the big drag on 2017, declining 2%.
China Dominates Planned Chip Fabs as more than 40% of front end semiconductor fabs scheduled to begin operation between 2017 and 2020 are in China, a clear indication that China’s long-stated ambition to build a significant domestic semiconductor industry is taking shape.
Trump Win Could Mean Big Questions for Manufacturing as while Trump vowed to keep American manufacturing jobs, he offered little in the way of stated policy other than the promise to punish companies that sent manufacturing job outside the US. Questions about trade also could directly affect US manufacturing. How that plays out is a big unknown.
Europe will try to advance chip manufacturing, but not much results in 2017 as currently there is almost no leading-edge digital chip manufacturing left in Europe as the local companies have embraced outsourcing of digital semiconductor manufacturing to foundries. The European Commission intends to reconvene a high-level group of European CEOs and executives to exchange views on Europe’s 10/100/20 nanoelectronics and chip manufacturing project and make adjustments as necessary for a wave of European Union investment supposedly starting in 2020. The two most advanced wafer fab locations left in Europe in terms of deep sub-micron miniaturization belong to Intel in Leixlip, Ireland and Globalfoundries in Dresden, Germany.
Smaller geometries are to be taken into use and researched in 2017. Several chipmakers ramp up their 10nm finFET processes, with 7nm just around the corner. As TSMC, GF/Samsung Battle at 7nm the net result is in the course of 18 months chip designers will see at least three variants of 7nm — separate immersion variants from TSMC and Globalfoundries and the EUV version from GF/Samsung. Intel has yet to detail its 7nm node.
At the same time R&D has begun for 5nm and beyond, but Uncertainty Grows For 5nm, 3nm as costs are skyrocketing. Both 5nm and 3nm present a multitude of unknowns and challenges. To put this in perspective, there are roughly two silicon atoms in 1nm of line width in a chip. Etching Technology Advances as atomic layer etch (ALE) moves to the forefront of chip-making technology—finally. TSMC recently announced plans to build a new fab in Taiwan at a cost of $15.7 billion targeted for TSMC’s 5nm and 3nm processes, which are due out in 2020 and 2022.
Moore’s Law continues to slow as process complexities and costs escalate at each node. Moore’s Law is dead, just not in the way everyone thinks. SiFive believes open source hardware is the way forward for the semiconductor industry. Technological advances keep allowing chips to scale, but the economics are another story – particularly for smaller companies that can’t afford chips in the volumes. The solution, according to San Francisco-based startup, SiFive, is open-source hardware, specifically an architecture developed by the company’s founders called RISC-V (pronounced “risk-five”). Done right SiFive, which was awarded Startup of the Year at the 2016 Creativity in Electronics (ACE) Awards, believes that RISC-V will do for the hardware industry what Linux has done for software. For example 5th RISC-V Workshop Points to Growing Interest in the RISC-V Platform.
Sensors are hot in 2017. These tiny, powerful solutions are creating the interface between the analog and the digital world. Data is everywhere, and sensors are at the very heart of that. While no one really knows what technology’s next “killer application” will be, we are confident that any killer app will rely on sensors.Appliance autonomy promises to make life simpler, but this field has still lots of to improve even after year 2017.
Interface ICs will continue to help simplify high-bandwidth designs while making them more robust and reliable. Application areas that will benefit include automotive, communications, and industrial. Both wired and wireless interface solutions have plenty of applications.
Analog’s status is rising as more sensors and actuators are added into electronic devices, pressure is growing to more seamlessly move data seamlessly back and forth between analog and digital circuitry. IoT pushes up demand for analog content and need for communication between these two worlds will continue to grow. Analog and digital always have fit rather uncomfortably together, and that discomfort has grown as SoCs are built using smaller feature sizes. The demand for analog silicon has always existed in the embedded space, but the advent of the Internet of Things (IoT) is increasing the demand for connected mixed-signal content. At 28nm and 16/14nm, standard “analog” IP includes a fair amount of digital content.
It seems that hardware designer is a disappearing resource and software is the king in 2017. It is becoming less and less relevant in what format the device is used in many applications. Card computers are standard products and are found in many different card formats that can be used in very many applications. Embedded development is changing to more and more coding. More software designers that understand some hardware are needed, but it is not easy to leap to move to the hardware to software.
The power electronics market is moving at very fast pace. Besides traditional industrial, renewable, and traction sectors, new applications such as energy-storage systems, micro-grids, and dc chargers are emerging. As the automotive world moves to electric vehicles, this creates challenges for IGBT and SiC-MOSFET ICs, and their associated gate drivers. New packages for high-voltage IGBTs and high-voltage SiC-MOSFETs are introduced.
More custom power distribution and higher voltages on data center computer systems in 2017. OpenRack and OpenCompute projects are increasing the distribution voltage inside the server itself. This approach, plus transitioning to new materials such as gallium nitride in the power-conversion systems, can reduce overall power consumption by 20% and increase server densities by 30-40%.”
Power Modules and Reference Designs will be looked at in 2017 even more than earlier in power electronics. The semiconductor and packaging technologies used in power modules have advanced considerably, and the industry is developing modules today that are denser, less expensive, and easier to use. Designers want to rely on power modules to speed up designs and optimize space using smaller, easy-to-use power modules. Module manufacturers hope that engineers will increasingly choose a module over a discrete design in many applications.
The bi-directional DC/DC converter has been around for a while, but new applications are quickly emerging which necessitate the use of this architecture in so many more systems. Battery back-up systems need bi-directional DC/DC converters. Applications today require better energy efficiency and such systems as green power with solar or wind generation, need storage so that when there is no wind or sun available the electricity flow is not interrupted.
Power supplies need to become more efficient. Both European Union’s (EU) Code of Conduct (CoC) Tier 1 and CoC Tier 2 efficiency standards are to be taken into use. The European Union’s CoC Tier 1 effectively harmonizes the EU with US DoE Level VI and became effective as a voluntary requirement from January 2014, two years ahead of Level VI. Its adoption as an EU Ecodesign rule is currently under review to become law with an implementation date of January 2017. The key difference between the CoC requirements and Level VI is the new 10% load measure, which imposes efficiency requirements under a low-load condition where historically most types of power supplies have been notoriously inefficient. CoC Tier 2 further tightens the no-load and active mode power consumption limits.
During 2016, wireless-power applications started to pick up across many fields in the semiconductor industry, and it will continue to do so. Wireless power will continue to gain traction with increased consumer demand. Hewlett Packard, Dell, jjPlus, and Witricity have already announced products based on Airfuel standards. And, products based upon the Qi standard will continue to grow at a rapid pace.
Other prediction articles:
In Power & Analog 2017 Forecast: What Experts Are Saying article representatives from major players in the semiconductor industry share their predictions for 2017 regarding power modules, wireless power, data converters, wireless sensing, and more.
Looking Ahead to 2017 article tells on to what SIA is focused on working with. “U.S. semiconductor technology should be viewed as a strategic national asset, and the Administration should take a holistic approach in adopting policies to strengthen this vital sector,” the letter says
Hot technologies: Looking ahead to 2017 article collection has EDN and EE Times editors explore some of the hot technologies in 2017 that will shape next year’s technology trends and beyond.
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Tomi Engdahl says:
Intersil shrinks RS-485 transceiver
http://www.edn.com/electronics-products/other/4458030/Intersil-shrinks-RS-485-transceiver
Housed in a 4×5-mm, 16-lead QSOP, Intersil’s ISL32704E isolated RS-485 differential-bus transceiver is as much as 70% smaller than competing devices. The part offers a bidirectional data transmission rate of 4 Mbps and a working voltage of 600 VRMS for use in industrial IoT networks.
Tomi Engdahl says:
SerDes Signal Integrity Challenges At 28Gbps And Beyond
http://semiengineering.com/serdes-signal-integrity-challenges-at-28gbps-and-beyond/
Challenges of designing high-speed SerDes, and the importance of detailed modeling and highly programmable circuits and debug interfaces.
Tomi Engdahl says:
Will Self-Heating Stop FinFETs
http://semiengineering.com/will-self-heating-stop-finfets/
Central fins can be up to 50% hotter than other fins, causing inconsistent threshold behavior and reliability problems.
New transistor designs and new materials don’t appear out of thin air. Their adoption always is driven by the limitations of the incumbent technology.
Silicon germanium and other compound semiconductors are interesting because they promise superior carrier mobility relative to silicon. FinFET transistor designs help minimize short channel effects, a critical limitation of planar MOSFETs. But there’s no such thing as a free lunch. These innovations also bring limitations and tradeoffs of their own.
For example, the vertical fins of a finFET transistor are wrapped in an oxide layer. Depending on the design, the physical connection between the fins and the silicon bulk is either very narrow or non-existent. Yet they operate at relatively high voltages, thereby generating high current densities and correspondingly high operating temperatures. This combination of increasing operating temperatures and poor heat dissipation can lead to localized thermal effects, commonly known as self-heating.
Hot spots in integrated circuits are nothing new.
Rather than affecting certain circuit blocks, it affects individual fins within a single finFET.
Tomi Engdahl says:
Inside Next-Gen Transistors
http://semiengineering.com/inside-next-gen-transistors/
Coventor’s CTO looks at new types of transistors, the expanding number of challenges at future process nodes, and the state of semiconductor development in China.
SE: What’s the biggest challenge at 10nm and 7nm?
Fried: The middle-of-line interconnect is the battleground right now. Middle-of-line is really hard. It has the dimensional constraints of both the front-end and backend. It has the material constraints of the front-end. It has the design freedom that neither the front-end or backend have, so there are more shapes and constructs to manage than anything else. We saw that difficulty at 22nm. It got bad at 14nm. At 10nm, it’s just almost devastating. And then we are going to do 7nm.
SE: Can you describe the middle-of-line (MOL)?
Fried: You have to get the connections from the lowest levels of interconnects to the transistors. So there is some metallization and then there are contact schemes. And then there are all sorts of different and interesting designs. Do I contact the gate? Do I contact the source/drain? Do I contact both? Do I fly over the gate? There are all sorts of very intricate design constructs that have to be managed. It’s incredibly complicated. There is a lot of topology involved. It has to be very low resistance.
Tomi Engdahl says:
The Evolution Of EUV
Why a number of individual steps ultimately proved so difficult, and how that will play out for future chips.
http://semiengineering.com/the-evolution-of-euv/
EUV systems are beginning to ship to large foundries in volume, setting the stage for one of the biggest leaps in technology the semiconductor industry has ever witnessed.
ASML has emerged as the sole supplier in this market, but it has taken an entire ecosystem to develop EUV. It has taken billions of dollars of investment by ASML, along with enormous cash infusions by Intel and TSMC, contributions from universities and research houses around the globe, and complementary technologies such as photoresists and atomic-level etch by other companies.
But EUV has turned out to be so complex that it has left many scientists and engineers shaking their heads in disbelief. So why did the industry end up backing this technology?
The plasma power source turned out to be such a big issue that many experts were convinced that EUV would never materialize.
“We’ve been ready for EUV for many years already, and every year it was always one more year,” said Meiling.
Still, a lot of things have happened since EUV was supposed to show up, first at 45nm, and then at 28, 16/14nm. For one thing, chipmakers have come to grips with the fact that ever since the end of classical scaling at 90nm, just shrinking features doesn’t necessarily improve performance and lower power. And even with EUV, the price per transistor is no longer decreasing at the same rate as it did prior to finFETs and double patterning.
Whether all of these developments would have progressed this far had EUV hit its initial deadline is speculation. But given all of these developments, it does raise some interesting questions:
• How much of the semiconductor industry will take advantage of EUV for developing chips, and how much will that affect the cost?
• Will EUV be used just for making cuts and holes in critical metal layers, or will it ultimately replace immersion lithography.
• At what process nodes will EUV play a significant role?
• How many semiconductor applications will require smaller nodes, and will it be as standalone chips with more regular structures, such as chiplets in a package, or will it continue to be complex SoCs?
The answers to all of these questions have a direct bearing on the future of this massive development effort. The challenges in developing EUV were enormous.
Tomi Engdahl says:
Impact Of Rising SoC Design Costs On Innovation
http://semiengineering.com/impact-of-rising-soc-design-costs-on-innovation/
While design costs have been rising steadily since 40nm, the acceleration at 7nm and 5nm is worrisome.
If there is one truism in the semiconductor market, it is that rising costs will impact unit demand at some point if they continue long enough. The subject of this blog deals not with device ASPs; but rather with rising SoC design costs, and their effect on the number of designs at the advanced nodes. Even though the mechanism governing each set of numbers is different (device ASPs vs. design costs), the overall impact can be similar. In this case, the number of design starts is impacted by the climate of rising design costs.
Tomi Engdahl says:
Cloud Computing Chips Changing
As cloud services adoption soars, datacenter chip requirements are evolving.
http://semiengineering.com/cloud-computing-chips-changing/
An explosion in cloud services is making chip design for the server market more challenging, more diverse, and much more competitive.
Unlike datacenter number crunching of the past, the cloud addresses a broad range of applications and data types. So while a server chip architecture may work well for one application, it may not be the optimal choice for another. And the more those tasks become segmented within a cloud operation, the greater that distinction becomes.
increasingly the x86 architecture is being viewed as just one more option outside of its core number-crunching base. Cloud providers such as Amazon and Google already have started developing their own chip architectures. And ARM has been pushing for a slice of the server market based upon power efficient architectures.
ARM’s push, in particular, is noteworthy because it is starting to gain traction in a number of vendors’ server plans. Microsoft said last month it would use ARM server chips in its Azure cloud business to cut costs.
Whether ARM-based servers will succeed just because they use less power than an x86 chip for specific workloads isn’t entirely clear. Unlike consumer devices, which typically run in cycles of a couple years, battles among server vendors tend to move in slow motion—sometimes over a decade or more. But what is certain is that inside large datacenters, power expended for a given workload is a competitive metric. Powering and cooling thousands of server racks is expensive, and the ability to dial power up and down quickly and dynamically can save millions of dollars per year. Already, Google and Nvidia have publicly stated that a different architecture is required for machine learning and neural networking.
In looking at the power performance tradeoffs, and how to target the designs properly, there are two distinct things that cloud has accelerated in both the multicore and networking space. “What is common between these chips is that they are pushing whatever the bleeding edge is of technology, such as 7nm,”
Even today, datacenters use 2% of the power in the United States, so they are a humongous consumer. And when it comes to power, it’s not just how much power the chip uses, it’s the HVAC in order to keep the datacenter cool. In essence, you’ve got to keep the dynamic power under target workloads under control, and the area has to be absolutely as small as possible. Once you start replicating these things, it can make a tremendous difference in the cost of the chip overall.
“While there is still a need for enterprise data centers to have a general server/traditional server primarily based on Intel Xeon-core-based processors with a separate NIC card connecting to external networking where the switching and routing occur, we see in these large-scale cloud datacenters that they have a number of specific applications that they feel can be optimized for those applications within the cloud, within that data center,” said Ron DiGiuseppe, senior strategic marketing manager in the Solutions Group at Synopsys.
Seeing through the fog
While equipping the datacenters is one trajectory, a second one is reducing the amount of data that floods into a datacenter. There is increasing interest to be able to use the network fabric to do at least some of the signal processing, data processing, and DSP processing to extract patterns and information from the data. So rather than pushing all of this data up through the pipe into the cloud, the better option is to refine that data so only a portion needs to be processed in the cloud servers.
This requires looking at the compute equation from a local perspective, and it opens up even more opportunities for chipmakers.
A change in thinking
The key to success comes down to thinking about these chip designs very holistically, Kurisu added, “because when it comes to cloud in the datacenter, and if you think about Microsoft Azure or Amazon Web services or any of the others, the types of capabilities that are available from the cloud datacenter down to the actual embedded device, these things need to work in tandem. If you have a robot controller, and you need to do a firmware update—and you want to initiate that from the cloud—how that gets enabled on the end device is tied very explicitly into how the operation is invoked from the cloud side. What is your cloud solution? That’s going to drive what the embedded solution is. You’ve got to think of it as a system, and in that way the stuff that happens in the datacenter is very closely related to the things that might seem very disconnected on the edge. But how the IoT strategy is implemented is somewhat tied together so it all has to be considered together.”
Tomi Engdahl says:
Using and selecting COTS components for space applications
http://www.edn.com/electronics-blogs/out-of-this-world-design/4458274/Using-and-selecting-COTS-components-for-space-applications
For some spacecraft manufacturers, the use of commercial off-the-shelf (COTS) parts is the only option to meet the performance and cost needs of a mission. For many satellite OEMs, the price and long lead-times of fully-qualified components is simply unaffordable. Today, many COTS devices are operating successfully in-orbit and this article discusses their use and selection for space applications.
CMOS scaling, epitaxial fabrication, the use of shallow trench isolation together with TMR HDL coding, SEU mitigation, and sensitivity classification of the configuration bitstream has allowed some ultra deep-submicron, SRAM-based COTS FPGAs to be used for low-dose, three to five-year LEO missions.
Today, several COTS flash-based FPGAs are operating successfully on-board satellites with OEMs adding EDAC and TMR to increase reliability. Their configuration memory is SEU immune and devices can be re-programmed in-orbit.
The use of COTS components must be an integrated part of the complete design process: from initial parts selection and an assessment of their suitability for use in space, how devices are handled and stored once they arrive in goods-in, and hardware design which reflects system reliability, e.g. prototyping early in the development cycle with burn-in can help weed out infant mortality failures, allowing for the use of more reliable components in their normal operating phase.
Tomi Engdahl says:
Supporting CPU Plus FPGA
http://semiengineering.com/supporting-cpu-plus-fpga/
Experts at the table, part 3: Partitioning, security issues, verification and field upgradeability.
Tomi Engdahl says:
EUV Litho Coming Into Commercial Focus
http://www.eetimes.com/document.asp?doc_id=1331623&
Executives from Dutch lithography vendor ASML NV said Wednesday (April 19) that the company expects to ship 20 to 24 extreme ultraviolet (EUV) lithography tools next year as the industry continues edging closer to production deployment of the oft-delayed next-generation lithography technology.
Peter Wennink, ASML’s president and CEO, told analysts following the company’s first quarter financial report Wednesday that the company continues to make progress toward its goals for EUV of 125 wafers per hour productivity and 90 percent light-source availability.
Tomi Engdahl says:
New Method Cuts Cost of GaAs Circuits
MIT Copy/Paste Method Speedy
http://www.eetimes.com/document.asp?doc_id=1331617&
A new copy/paste method for mass production of expensive circuits has just been invented at the Massachusetts Institute of Technology (MIT). After the fabrication of a “donor” wafer topped by graphene, the technique uses a deposit-and-peel-off (copy/paste) method that reduces the cost of the circuitry and makes the cost of the underlying wafer relatively insignificant. The technique could encourage manufacturers to combine silicon (Si) with expensive materials, like gallium arsenide (GaAs) for transistor channels, very easily and inexpensively.
Tomi Engdahl says:
Medical Tests: Merged Technologies Yield Dramatic Insight
http://www.eetimes.com/author.asp?section_id=36&doc_id=1331586&
New devices leverage high-performance, low-cost sensing technologies and signal processing to develop radically new ways to non-invasively address medical-instrumentation challenges.
We’ve seen lots of activities in “wearables” and personal health/wellness devices of many types in the past year, with more to come. These small units can track pulse and respiration, cardiac waveforms, blood oxygen saturation (SpO2) level, and more.
All of the well-deserved attention that these useful medical and fitness products are getting, however, may be obscuring a bigger picture. Engineers, researchers, and scientists are combining advanced sensor types and technologies — along with complex analog and digital signal processing — to provide new insights into a variety of medical issues and to do so in a low- or no-risk, non-invasive way.
Tomi Engdahl says:
DNA, the Ultimate in Data Memory
http://www.eetimes.com/author.asp?section_id=36&doc_id=1331610&
While the role of DNA as a biological memory is well established exploring its potential as a data memory is relatively new. DNA data memory has not quite yet reached the stage where a blob of DNA can have some wires attached to it to write and read its data content, good progress has been made.
The their latest work, published in Science magazine, Yaniv Erlich and Dina Zielinski from Columbia University and the New York Genome Center, mixed some clever biochemistry with some leading edge communications data encoding techniques and added a dash of processing power. The result, under the heading of “DNA Fountain,” is a demonstration of the ability to use DNA to store a complete operating system of 1.4 MBytes, a movie and other files for a total of greater than 2 Mbytes.
This is now possible because at the same time they have provided a new level of efficiency and reliability for the technique. If the DNA-data memory must have an acronym to fit it in the SRAM, DRAM, NVRAM memory spectrum, then biologic archival read rarely memory (BARRM) might be one choice.
Tomi Engdahl says:
Survey Sees Engineering Brain Drain
http://www.eetimes.com/author.asp?section_id=36&doc_id=1331593&
Senior engineers are retiring at an accelerated pace, creating a brain drain impacting all aspects of the supply chain from product creation though delivery.
Many estimates project that half of the engineering workforce will be eligible for retirement in the next few years. This knowledge drain is impacting the ability of organizations to keep pace.
At IEEE GlobalSpec, we hear and see that the pace of engineering and the complexity of the engineer’s role has changed. Engineers are facing real challenges finding solutions and information they need to solve their toughest problems.
Tomi Engdahl says:
Skilled Labor, Free Trade Key Concerns over Brexit
Brexit won’t affect UK influence on standards – NMI
http://www.eetimes.com/author.asp?section_id=36&doc_id=1331591&
The United Kingdom’s electronics industry expresses angst in the time of Brexit.
The UK electronics industry’s main concerns for doing business post-Brexit are continued free trade with Europe, access to skilled workers and collaboration on R&D with European Union companies, according to a survey by UK trade body the National Microelectronics Institute (NMI).
Tomi Engdahl says:
Rambus, Microsoft Heat Up With Cold DRAM
http://www.eetimes.com/document.asp?doc_id=1331608&
A community of computer scientists striving to respond to soaring system demand for real-time data processing has just received some good news.
Rambus revealed Monday (April 17) that the company, in collaboration with Microsoft researchers, will have an early prototype of cryogenic memory in a month, and a more complete one by the end of the year. The new technologies will be essential to data centers, “currently the fastest growing consumer of memory” in the industry, Craig Hampel, chief scientist at Rambus, told EE Times.
Tomi Engdahl says:
TSMC Expects First-Half Smartphone Slump
http://www.eetimes.com/document.asp?doc_id=1331602&
Taiwan Semiconductor Manufacturing Co. (TSMC), the largest foundry for customers in the smartphone business including Apple and MediaTek, says it is expecting an inventory correction in smartphones to continue through the first half of this year.
“Fabless days of inventory (DOI) are still high. Our second-quarter guidance reflects a severe inventory adjustment in the smartphone and PC markets,” TSMC Co-CEO Mark Liu said at an event in Taipei to announce the company’s first-quarter results. “Fabless DOI should return to normal around the end of the second quarter this year.”
The company, a bellwether for the electronics industry, revised its outlook for the overall semiconductor market upward by three percentage points to 7 percent growth this year due to stronger than expected demand for memory products. For the same period, TSMC cut its forecast for overall foundry market growth to 5 percent from the original 7 percent it predicted three months ago. TSMC maintained its expectation for its own growth to be in a range of 5 percent to 10 percent.
The company, which has about half of the overall foundry market, said it expects to increase its market share during the second half of this year as it ramps up production of 10nm products.
TSMC has lagged behind foundry rival Samsung by about three months with the launch of 10nm products.
Tomi Engdahl says:
Gartner Ups Chip Market Growth Forecast to 12%
http://www.eetimes.com/document.asp?doc_id=1331597&
Predictions of 2017 semiconductor market growth continue to get more optimistic as the year rolls on, with favorable conditions in the commodity memory market continuing to be seen as the main driver.
On Thursday (April 13), market research firm Gartner Inc. said it expects semiconductor industry sales to grow 12.3 percent this year, reaching $386 billion. Gartner (Stamford, Conn.) said favorable market conditions that gained momentum in the second half of 2016 have raised the outlook for the chip market in both 2017 and 2018.
But Gartner also cautioned that the rush to add DRAM and NAND flash capacity to capitalize on the market conditions and the rise in manufacturing in China would likely result in a market correction in 2019.
Tomi Engdahl says:
NXP Shows First FD-SOI Chips
Samsung shipping now, GF not yet
http://www.eetimes.com/document.asp?doc_id=1331600&
NXP will ship this year as many as five SoCs made in Samsung’s 28nm fully depleted silicon-on-insulator (FD-SOI) process, including one that has been sampling for six months. Samsung is expected to announce its FD-SOI roadmap in May and is already working on RF and in-house embedded MRAM for it.
An NXP executive showed the first samples of the products at an event here, a key milestone in a long journey for FD-SOI. The next big step is finding an embedded non-volatile memory for the process, given embedded flash is expected to hit limits at 14nm.
A Globalfoundries executive declined to say when it expects to ship the first commercial chip in its 22nm FD-SOI
NXP described four 64-bit ARMv8 and one 32-bit ARMv7 embedded SoCs under its i.MX brand, three now in production in Samsung’s FD-SOI process. Over the next two years, the family will cover a performance range that scales by a factor of 25, five times more than its planar-based i.MX chips, each design optimized for different performance and power characteristics.
Tomi Engdahl says:
DNA, the Ultimate in Data Memory
http://www.eetimes.com/author.asp?section_id=36&doc_id=1331610&
While the role of DNA as a biological memory is well established exploring its potential as a data memory is relatively new. DNA data memory has not quite yet reached the stage where a blob of DNA can have some wires attached to it to write and read its data content, good progress has been made.
The result, under the heading of “DNA Fountain,” is a demonstration of the ability to use DNA to store a complete operating system of 1.4 MBytes, a movie and other files for a total of greater than 2 Mbytes.
Tomi Engdahl says:
Researchers Print Transistors on 2D Thin-Film Materials
http://www.eetimes.com/document.asp?doc_id=1331633&
While video display manufacturers are furiously trying to devise a practical means to manufacture thin-film transistors (TFTs) with the goal of reducing the cost of monitors, TVs, smartphone screens, and the like, a group of researchers in Ireland have just announced a printing process for creating two-dimensional transistors on thin-film materials that could make displays so cheap that they would be literally disposable.
A possible application might be packaging for perishables (e.g., a container of yogurt) that displays an expiration-date countdown. Or white wine labels that alert you when the contents are the optimum temperature for drinking. Or imagine if the wrapping for your 7-Eleven breakfast burrito could alert you when your bus or your Lyft is about to arrive.
Tomi Engdahl says:
KKR, INCJ Team For New Toshiba Bid
http://www.eetimes.com/document.asp?doc_id=1331634&
The U.S. private equity fund KKR will be partnering with a Japanese public-private fund – Innovation Network Corp. of Japan (INCJ) – to bid jointly for Toshiba’s memory unit, Japan’s economic newspaper Nikkei reported Friday.
Tomi Engdahl says:
EUV Litho Coming Into Commercial Focus
http://www.eetimes.com/document.asp?doc_id=1331623&
Executives from Dutch lithography vendor ASML NV said Wednesday (April 19) that the company expects to ship 20 to 24 extreme ultraviolet (EUV) lithography tools next year as the industry continues edging closer to production deployment of the oft-delayed next-generation lithography technology.
Peter Wennink, ASML’s president and CEO, told analysts following the company’s first quarter financial report Wednesday that the company continues to make progress toward its goals for EUV of 125 wafers per hour productivity and 90 percent light-source availability. Wennik alluded to presentations at the recent SPIE Advanced Lithography Conference from Intel, Samsung and TSMC showing their latest results with EUV systems and the status of the EUV infrastructure.
Tomi Engdahl says:
ASML posted strong sales in the quarter. “ASML noted a significant increase in memory demand this year, prompting higher estimates. EUV demand is increasing, with three new orders in the quarter, though shipment and revenue timing remain hard to predict,” Twigg said in a separate report. “ASML’s 2017 demand outlook improved significantly over the last quarter, and its view should be fairly reliable given long lead times for its equipment. As a result, we’re raising our estimates meaningfully. We’re increasingly bullish on the EUV ramp as momentum continues to improve after years of slow progress.”
Source: http://semiengineering.com/the-week-in-review-manufacturing-160/
Tomi Engdahl says:
Enabling Magnetic Tunnel Junctions Array Processing For Embedded STT MRAM
What to considering in optimizing this memory, and key performance metrics to watch.
http://semiengineering.com/enabling-magnetic-tunnel-junctions-array-processing-for-embedded-stt-mram/
Tomi Engdahl says:
Midrange oscilloscope provides 1 GHz bandwidth
http://www.edn.com/electronics-products/electronic-product-reviews/other/4458277/Midrange-oscilloscope-provides-1-GHz-bandwidth
Teledyne LeCroy’s Wavesurfer 510 oscilloscope provides 1 GHz bandwidth while sampling at 10 Gsamples/s simultaneously on each of its four channels. Such a high sample rate gives the WaveSurfer 510 an edge of over other 1 GHz oscilloscopes such as the Rohde & Schwarz RTO2000, Keysight DSOX3104, and Tektronix MDO4000C series.
Prices start at $12,900.
http://teledynelecroy.com/oscilloscope/oscilloscopeseries.aspx?mseries=549
Tomi Engdahl says:
16-bit AWG runs up to eight channels
http://www.edn.com/electronics-products/electronic-product-reviews/other/4458278/16-bit-AWG-runs-up-to-eight-channels
Signals keep getting more complex. Bandwidth requirements for wireless devices keep forcing new standards, which require simulated signals to test receivers. On top of that, electronic warfare needs ever more complicated signals to test communications and radar devices. Researchers in labs around the world need signals to simulate physical phenomena. To keep up the demand for ever more complex signals, Tektronix has introduced the AWG5200 series of arbitrary waveform generators (AWGs).
Available in three base models with two, four, or eight analog outputs, the AWG5200 series has sample rates up to 10 Gsamples/s (2.5 Gsamples/s standard), 16-bit resolution, and 2 Gsamples/ch of waveform memory.
Tomi Engdahl says:
VNA test cables work up to 110 GHz
http://www.edn.com/electronics-products/other/4458272/VNA-test-cables-work-up-to-110-GHz
Outfitted with 1.0 mm stainless-steel connectors, flexible coaxial cables from Pasternack enable measurements to 110 GHz using a vector network analyzer.
Shipped from stock, the VNA test cables cost $6961.75 for a 6 in. length and $7266.65 for a 12 in. length in single-unit quantities.
Tomi Engdahl says:
SiC MOSFET handles up to 1000 V
http://www.edn.com/electronics-products/other/4458284/SiC-MOSFET-handles-up-to-1000-V
Wolfspeed offers the C3M0120100K silicon carbide power MOSFET for renewable energy, electric-vehicle battery charger, high-voltage DC/DC converter, and switch-mode power supply applications. The C3M0120100K provides a maximum drain-source voltage of 1000 V and a continuous drain current of 22 A at 25°C.
N-channel enhancement-mode device include an on-resistance of 120 mΩ, total gate charge of 21.5 nC, output capacitance of 40 pF, and maximum junction temperature of 150°C.
C3M0120100K costs $5.79 each in lots of 1000 units.
http://www.wolfspeed.com/c3m0120100k
Tomi Engdahl says:
22nm Process War Begins
High price of moving to finFETs pushes foundries to offer a less expensive alternative.
http://semiengineering.com/22nm-process-war-begins/
Many foundry customers at the 28nm node and above are developing new chips and are exploring the idea of migrating to 16nm/14nm and beyond. But for the most part, those companies are stuck because they can’t afford the soaring IC design costs at advanced nodes.
Seeking to satisfy a potential gap in the market, GlobalFoundries, Intel and TSMC are racing to develop new processes targeted at 22nm. On paper, 22nm enables faster chips than 28nm and is less expensive to develop than 16nm/14nm.
Time will tell whether 22nm will become a popular node like 28nm, or just a niche, but it does give foundry customers some new options. In fact, from separate foundry vendors, customers have the option to select among three different 22nm technologies—planar bulk CMOS, FD-SOI and finFETs.
Tomi Engdahl says:
Integrated circuit patterns can be copied with graphene
MIT’s engineers and the new technology developed by the LG Electronics Research Center can significantly reduce the manufacturing costs of exotic semiconductor materials at disk level. The new method uses graphene as a kind of “copier” to transfer complex crystalline patterns from the lower semiconductor die to the layer on top of it.
The engineers placed sheet graphene on top of the expensive reel and raised semiconductive material onto it. The graphene is so thin that the circuit patterned disk below will be copied to the surface layer semiconductor.
The graphene is also fairly slippery, so its van der Waals links to the vertical direction are weak, so the engineers could simply peel off the top of the finished sheet easily from the graphene. With the new technology of the research team, manufacturers can introduce silicon more efficient and more expensive semiconductor materials than ever before. The removed semiconductor can be easily transferred to flexible platforms, for example.
Source: http://www.etn.fi/index.php/13-news/6215-piirikuvioita-voi-kopioida-grafeenilla
Tomi Engdahl says:
Molex Collaborates With Fellow Market Leaders On New M12 Push-Pull Standard
Molex, Phoenix Contact, Murrelektronik and Binder drive standardization of a non-proprietary push-pull connection system
http://www.molex.com/molex/news/display_news.jsp?channel=New&channelId=-8&oid=2212&pageTitle=Molex+Collaborates+With+Fellow+Market+Leaders+On+New+M12+Push-Pull+Standard
Tomi Engdahl says:
Not stuck on silicon
Engineers use graphene as a “copy machine” to produce cheaper semiconductor wafers.
http://news.mit.edu/2017/graphene-copy-machine-cheaper-semiconductor-wafers-0419
In 2016, annual global semiconductor sales reached their highest-ever point, at $339 billion worldwide. In that same year, the semiconductor industry spent about $7.2 billion worldwide on wafers that serve as the substrates for microelectronics components, which can be turned into transistors, light-emitting diodes, and other electronic and photonic devices.
A new technique developed by MIT engineers may vastly reduce the overall cost of wafer technology and enable devices made from more exotic, higher-performing semiconductor materials than conventional silicon.
The new method, reported today in Nature, uses graphene — single-atom-thin sheets of graphite — as a sort of “copy machine” to transfer intricate crystalline patterns from an underlying semiconductor wafer to a top layer of identical material.
The engineers worked out carefully controlled procedures to place single sheets of graphene onto an expensive wafer. They then grew semiconducting material over the graphene layer. They found that graphene is thin enough to appear electrically invisible, allowing the top layer to see through the graphene to the underlying crystalline wafer, imprinting its patterns without being influenced by the graphene.
Graphene is also rather “slippery” and does not tend to stick to other materials easily, enabling the engineers to simply peel the top semiconducting layer from the wafer after its structures have been imprinted.
With the group’s new technique, Kim says manufacturers can now use graphene as an intemediate layer, allowing them to copy and paste the wafer, separate a copied film from the wafer, and reuse the wafer many times over. In addition to saving on the cost of wafers, Kim says this opens opportunities for exploring more exotic semiconductor materials.
Tomi Engdahl says:
The oscilloscope also comes from cards – according to Keysight
National Instruments addition Keysight invest also PXIe-frame-based systems. The latest New Technology magazine introduces the technology of PXIe frames and the provision of measurement cards.
In the market, PXI manufacturers clearly have two manufactures over the other: National Instruments and Keysight (formerly known as Agilent). Both of them have a comprehensive range of plug units and
Frames.
An example of this is Keysight’s M924xA, which uses the same technology as the Keysight’s Infiniium family stand alone devices.
National Instruments PXIe5164 is a PXI oscilloscope of approximately the same magnitude
Source: http://www.uusiteknologia.fi/2017/04/25/oskilloskooppi-syntyy-myos-korteista-keysight-mukaan/
Tomi Engdahl says:
JTAG offers mapping tool for Altium Designer
http://www.edn.com/electronics-products/other/4443078/JTAG-offers-mapping-tool-for-Altium-Designer
A free utility from JTAG Technologies, JTAG Maps for Altium Designer PCB design software lets engineers assess JTAG/boundary-scan resources on their design, before committing to layout. The application extension maps boundary-scan nets to the schematic and assists with the design-for-test process.
https://www.jtag.com/en/content/jtag-maps-altium
Tomi Engdahl says:
ECAD & System-level design now “going steady”
http://www.edn.com/electronics-blogs/all-aboard-/4440512/ECAD—System-level-design-now–going-
steady-
One is almost tempted to ask,”Is anyone still buying plain old CAD tools?” A least, that’s the impression I got attending sessions and browsing vendor offerings at PCB West a few weeks ago.
Zuken is one of the companies offering what they term “Product-centric design”. This means you are able to combine multiple PCBs and their interconnects into one project, as well as maintaining physical models of components and interfacing with MCAD software, allowing the PCB designer to quickly confirm at any time that their design is going to physically fit. Since miniaturized products these days rely on “squeezing all the air out” of the enclosure (gotta love that turn of phrase), having that power in one designer’s hands is a good thing.
One session attendee explained how they would make 3-D “prints” of their PCBs, components and all, to demonstrate fit within a similarly printed enclosure. This can be done with or without system-level tools, and is less necessary with them of course, but it’s a nice way to prove out the mechanics – assuming all the component models are correct.
Tomi Engdahl says:
Quick-Turn PCB shop review project: Master collection
http://www.edn.com/collections/4437744/Quick-Turn-PCB-shop-review-project–Master-collection
Tomi Engdahl says:
System design comes to Xpedition
http://www.edn.com/electronics-products/other/4442913/System-design-comes-to-Xpedition
While already selling CAD software that supports multi-board designs and various levels of integration, Mentor’s new Xpedition release fully integrates many system design functions under one roof, including system definition, multi-PCB and cable design, system-level thermal and SI/PI simulation, and MCAD interface.
Tomi Engdahl says:
FFSA combines the advantages of FPGA and ASIC circuits
he FFSA structure (Fast Fit Structured Array), developed by Toshiba, provides a cost-effective alternative to traditional FPGA port matrices. It is specifically designed for designers who want to quickly get their application of performance logic but to significantly outperform ASIC circuits at design costs even at low production volumes.
When system design requires an integrated solution, but no suitable standard circuit is available, the programmable gate matrix FPGA provides a fast and reasonably priced solution for example for protocols or small-scale serial production. The custom-designed ASIC chip for the customer, for its part, is best suited for use when high integration and kernel performance is required, as well as low power consumption typically in a device that is to be manufactured in very large quantities. The production volumes must be so large that the benefit of the declining unit price compensates for the large NRE (Non-Recurring Engineering) costs of the ASIC circuit design.
Previously, FPGA manufacturers have offered designers new approaches such as minimalist FPGAs or replication services that are able to move the plan to a cheaper platform. On the other hand, ASIC suppliers have also offered new product categories such as structured matrices that speed up the circuit’s development cycle and reduce NRE costs.
Recently, Toshiba has come up with the opportunity to provide this special FFSA (Fast Fit Structured Array) design that results in ASIC-like performance but much lower in NRE than in a similar ASIC chip.
FFSA is also cost-effective with small volumes of production and can compete strongly with FPGAs at up to ten thousand copies per annum.
FFSA is a structured matrix that consists of a balanced mix of logic card arrays and fully customizable SRAM memory as well as high-speed transmitter receivers and programmable I / O buffers.
The metal layers of the structured matrix structure are reserved for the circuit tailoring and the lowest metal layers are common to all customers. This allows some of the masks to be manufactured in advance, thus shortening both development and production times and allowing the most part of the total cost to be shared between multiple client applications, thus significantly lowering the NRE cost.
Toshiba will continue to support the FFSA concept by developing new IP blocks that provide strong support for, for example, memory and network devices, as well as industry and digital image processing applications. The most important policy areas include, among other things, metalloid-enabled SRAM blocks that support both single- and two-port SRAMs, registers and ROM blocks.
Source: http://etn.fi/index.php?option=com_content&view=article&id=6219&via=n&datum=2017-04-25_14:47:35&mottagare=30929
Tomi Engdahl says:
Fab Tool Billings Reach 16-Year High
http://www.eetimes.com/document.asp?doc_id=1331645&
The three-month rolling average of billings among semiconductor equipment vendors based in North America hit $2.03 billion in March, its highest total in 16 years, according to the SEMI trade organization.
The three-month average of billings was up 69 percent compared to March 2016, the sixth consecutive month of year-over-year growth. The billings figure was also up 3 percent from February.
“March billings reached robust levels not seen since March 2001,” said Dan Tracy, senior director of industry research and statistics at SEMI, in a statement. “The equipment industry is clearly benefiting from the latest semiconductor investment cycle.”
Tomi Engdahl says:
Solid State Batteries Aim to Top Li-ion
Solid-State Batteries Harvest
http://www.eetimes.com/document.asp?doc_id=1331646&
Batteries could be transformed from our slowest growing technology to our fastest growing advanced technology if Ilika Technologies Ltd. (University of Southampton Science Park, Southampton U.K.) can realize its dream of self-powered systems-on-chip (SoCs).
By eliminating the liquid cores of every other battery technology under the sun — especially the flammable lithium ion (Li-ion) — into the solid-state micron-thin-layers of an SoC, each chip in an electronic circuit could become self-powered, simplifying printed circuit boards and eliminating the big-iron power supplies required today.
Ilika’s solid-state batteries now come in the full range of temperatures (from -40 degrees Celsius up to +150 C.), making them accessible to automotive, industrial IoT and other rugged environments.
The transformation from flammable Li-ion to inflammable solid-state batteries is not going to happen overnight. In fact, the first mass-produced end-user products using them is predicted by Purdy to appear near the end of the decade. The first products to hit the market will likely use free standing solid-state batteries.
Nevertheless, once all the bugs have been worked out, rechargeable solid-state batteries using both solar and vibrational energy harvesting, plus charge-once-and-forget for the 10-year lifetime of the solid-state battery powered product, could become the rule rather than the exception.
Tomi Engdahl says:
For the won: Korean DRAMmer llamas SK Hynix earning buckets
Records highest quarterly operating profit in its history
https://www.theregister.co.uk/2017/04/26/drammer_and_nand_fabber_sk_hynix_earned_buckets_of_won/
Korean DRAMmer and NAND fabber SK Hynix reported revenue rises and record profits in its first 2017 quarter.
It recorded ₩6.29 trillion revenues, up 72 per cent on the year and 17 per cent on the quarter. Net income was ₩1.9 trillion, up a rather impressive 324 per cent year-on-year and, after that, an uninspiring 17 per cent on the quarter.
Tomi Engdahl says:
NXP Semiconductors Sells Shares in Chinese Foundry
http://www.electronicdesign.com/analog/nxp-semiconductors-sells-shares-chinese-foundry?NL=ED-003&Issue=ED-003_20170426_ED-003_498&sfvc4enews=42&cl=article_2_b&utm_rid=CPG05000002750211&utm_campaign=10785&utm_medium=email&elq2=d58d11e1903b429faeca66a28d2b3dc2
NXP Semiconductors has sold its shares of Advanced Semiconductor Manufacturing Corporation, an analog foundry based in Shanghai that fabricates chips for communications, consumer devices, and automobiles. The Dutch chip maker owned around 27.5% of ASMC.
NXP has longstanding ties with the foundry. ASMC was founded by Philips Semiconductor in 1988 and spent years as an exclusive supplier for the Dutch giant, which spun off NXP a decade ago. The foundry went independent in 1995 and now operates two factories in Shanghai, one for eight-inch wafers and another for wafers measuring five or six inches.
Tomi Engdahl says:
Stereax™
http://www.ilika.com/battery-technology/stereax-battery-technology
Ilika’s Stereax™ technology is the first solid state battery designed for the specific needs of the IoT space. The Stereax™ IP family offers compelling advantages over conventional lithium ion batteries, including: smaller footprint, faster charging, longer life span, low leakage and reduced flammability.
The Ilika Stereax™ roadmap focuses on three main battery requirements: miniaturisation, capacity in a small footprint and increased performance. The miniaturisation roadmap looks at increasingly smaller footprints at smaller currents (μA), making them ideal for small sensor driven devices. The capacity roadmap increases the amount of energy for a given active footprint by utilising Ilika’s patented stacking feature, which allows multiple cells to be stacked on top of one another. The performance roadmap focuses on higher energy density solutions that have additional requirements such as extended temperature range support.
Tomi Engdahl says:
Energy Star Program For Homes And Appliances Is On Trump’s Chopping Block
https://yro.slashdot.org/story/17/04/26/1740203/energy-star-program-for-homes-and-appliances-is-on-trumps-chopping-block
Appliance manufacturers and home builders are in Washington, D.C., today to celebrate a popular energy efficiency program, even as it’s slated for elimination in President Trump’s proposed budget. NPR adds:
You probably know the program’s little blue label with the star — the Environmental Protection Agency says 90 percent of U.S. households do. [...] The 25-year-old Energy Star program appears to be targeted simply because it’s run by the federal government. I
Tomi Engdahl says:
UMC Sees Weakening Demand at 28nm
http://www.eetimes.com/document.asp?doc_id=1331651&
United Microelectronics Corp. (UMC), Taiwan’s second largest foundry, said sales of its most advanced technology node have slipped for a third time under strong competition.
The company’s 28nm process fell to 17 percent of overall sales in the first quarter of this year compared with 22 percent in the fourth quarter last year. It’s been a bumpy ride for UMC. The company has seen its portion of overall sales from 28nm decline on a quarterly basis for the third time since ramping up the process technology nearly three years ago, according to company reports.
“There has been some weakness in demand,”
Larger rival Taiwan Semiconductor Manufacturing Co. (TSMC) has successfully defended its cash cow 28nm node after launching it nearly five years ago. TSMC’s 28nm products rose to account for 25 percent of the company’s overall sales
“It feels like there is some oversupply in 28nm,” JPMorgan analyst Gokul Hariharan said on the conference call. Other analysts voiced suspicions that there is pricing pressure in the node that’s also supplied by TSMC and Semiconductor Manufacturing International Corp. of China.
Despite the headwinds, UMC’s utilization rate rose to 96 percent in the first quarter compared with 94 percent in the fourth quarter of last year. Demand has been good for WiFi, FPGA, application processor and baseband chips, according to CEO Yen.
Tomi Engdahl says:
Automotive Strength Drives TI’s First Quarter Sales
http://www.eetimes.com/document.asp?doc_id=1331648&
Texas Instruments Inc. reported better than expected first quarter revenue growth driven primarily by strong sales to the automotive and industrial markets, the company said Tuesday (April 25).
Analysts have been concerned about the potential for a slowdown in the global automotive market following two years of solid growth. But TI’s first quarter results offered evidence that demand for semiconductors in the automotive sector remains significant.
“Automotive demand remained strong, with most sectors growing in double digits,” said Dave Pahl, vice president and head of investor relations at TI, in a conference call with analysts following the quarterly report. “Industrial demand continued to strengthen with broad-based growth,” Pahl added.
Tomi Engdahl says:
Wall Street Journal:
The annual revenue of the semiconductor industry is estimated to have doubled since 2003 to $352B, driven by the proliferation of connected devices and big data
In the Chips: Tech’s Sleeping Giant Becomes a $352 Billion Cash Cow
https://www.wsj.com/articles/chips-ahoy-techs-sleeping-giant-becomes-a-352-billion-cash-cow-1493217440?mod=e2tw
The proliferation of connected devices and big data is handing new clout to chip makers, as a flood of demand pushes up prices
Tomi Engdahl says:
NXP rose to the top of the driver circuits, but only for a moment
For the first time at the top of the list, Philips’s heir apparent NXP.
Market shares and listing investments are now being transformed primarily by acquisitions. NXP’s $ 2.9 billion microcontroller sales are based on the fact that the company grew strongly in June 2015 with the acquisition of Freescale.
One year later, the NXP drivers are counted on the sale of American Qualcomm and probably Qualcomm will rise to the top of the list. Renesas, which has stabilized its sales to about $ 2.5 billion, will continue to grow.
The triple quartet, ie Microchip, is the second manufacturer to increase its market share. With its Atmel acquisition, its microcontroller turnover grew more than two billion dollars last year.
Millionaire drivers include Samsung, STMicroelectronics and Infineon.
Source: http://www.etn.fi/index.php/72-ecf/6242-nxp-nousi-ohjainpiirien-karkeen-mutta-vain-hetkeksi
Tomi Engdahl says:
Can Formal Replace Simulation?
http://semiengineering.com/can-formal-replace-simulation/
Exclusive: Formal leaders discuss the ways in which they are stretching formal tools to the limit to solve an ever-increasing array of tasks.