https://www.darrentoback.com/can-risc-v-linux-of-microprocessors-start-an-open-hardware-renaissance
RISC-V is an interesting open hardware CPU. It is the most promising open CPU design, but can it succeed in competitive CPU market?
https://www.darrentoback.com/can-risc-v-linux-of-microprocessors-start-an-open-hardware-renaissance
RISC-V is an interesting open hardware CPU. It is the most promising open CPU design, but can it succeed in competitive CPU market?
716 Comments
Tomi Engdahl says:
13-Year-Old, Nicholas Sharkey, Creates a RISC-V Core
https://riscv.org/blog/2020/11/13-year-old-nicholas-sharkey-creates-a-risc-v-core/
Tomi Engdahl says:
https://riscv.org/
Tomi Engdahl says:
https://hackaday.com/2020/11/09/the-logic-chip-risc-v-project-reboots/
Tomi Engdahl says:
While taking a little longer than college-level compatriots, Sharkey successfully designed a pipelined RISC-V core during the MYTH course.
13-Year-Old Nicholas Sharkey Demonstrates How Easy It Can Be to Get Started with RISC-V Design
https://www.hackster.io/news/13-year-old-nicholas-sharkey-demonstrates-how-easy-it-can-be-to-get-started-with-risc-v-design-2636c23a9258
Tomi Engdahl says:
BBC Announces RISC-V-Powered Doctor Who-Themed HiFive Inventor Educational Microcontroller Kit
https://www.hackster.io/news/bbc-announces-risc-v-powered-doctor-who-themed-hifive-inventor-educational-microcontroller-kit-8dbffb7a7adb
Narrated by Jodie Whittaker, the Doctor Who-themed kit is powered by SiFive’s RISC-V-based HiFive Learn Inventor board.
Announced last year, the HiFive Learn Inventor is a hand-shaped educational microcontroller board based on a modification of the form factor of the existing BBC micro:bit platform. Where the BBC micro:bit uses proprietary Arm cores, though, the HiFive Learn Inventor is powered by a SiFive FE310 32-bit microcontroller based on the free and open-source RISC-V instruction set architecture.
https://www.hackster.io/news/sifive-launches-learn-inventor-risc-v-development-platform-0472f3d2218a
Tomi Engdahl says:
ULP-RISC-V Coprocessor programming
https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/api-guides/ulp-risc-v.html
The ULP-RISC-V coprocessor is a variant of the ULP, present in ESP32-S2. Similar to ULP, ULP RISC-V coprocessor can perform tasks such as sensor readings while the main CPU stays in low power modes. The main difference from the FSM ULP is this variant can be programmed in C using standard GNU tools.
Tomi Engdahl says:
ESPRESSIF LEAKS ESP32-C3: A WIFI SOC THAT’S RISC-V AND IS ESP8266 PIN-COMPATIBLE
https://hackaday.com/2020/11/22/espressif-leaks-esp32-c3-a-wifi-soc-thats-risc-v-and-is-esp8266-pin-compatible/
Six years on from the emergence of the Espressif ESP8266 we might believe that the focus had shifted to the newer dual-core ESP32. But here comes a twist in the form of the newly-revealed ESP32-C3. It’s a WiFi SoC that despite its ESP32 name contains a RISC-V core in place of the Tensilica core in the ESP32s we know, and uses the ESP8266 pin-out rather than that of its newer sibling. There’s relatively little information about it at the time of writing, but CNX Software have gathered together what there is including a draft datasheet whose English translation is available as a Mega download. As with other ESP32 family members, this one delivers b/g/n WiFi and Bluetooth Low-Energy (BLE) 5, where it differs is the RISC-V 32 Single-core processor with a clock speed of up to 160 MHz. There is 400 kB of SRAM and 384 kB ROM storage space built in.
Tomi Engdahl says:
‘Bunnie’ Huang Dives Deep Into the Security of the RISC-V-Powered Precursor
Built around an FPGA, the Precursor is not only massively hackable but also built with security in mind — and can be potted for protection.
https://www.hackster.io/news/bunnie-huang-dives-deep-into-the-security-of-the-risc-v-powered-precursor-9af3c2d721a8
Tomi Engdahl says:
SiFive Pushes Open Source RISC-V Chip Architecture Closer to Prime Time
https://www.datacenterknowledge.com/hardware/sifive-pushes-open-source-risc-v-chip-architecture-closer-prime-time
The open source RISC-V silicon specification flexes it’s muscle with a new developers’ board its maker, SiFive, is calling a PC.
Tomi Engdahl says:
Are RISC-V chips ready to compete with Arm?
The open-source chip architecture is being more widely used than ever. Is the time right to challenge Arm and x86?
https://techmonitor.ai/hardware/silicon/risc-v-arm-nvidia-intel-open-source
Celebrating its tenth anniversary this year, RISC-V is an open-source processor architecture which is growing in popularity with developers around the world. In recent months there have been signs that RISC-V is ready to go mainstream.
This month (November 2020), semiconductor company SiFive released HiFive Unmatched, a high-performance RISC-V board which it describes as a ‘PC without a box’.
“RISC-V is the first chip of its magnitude that grew up in open source,” says Mark Himelstein, a Silicon Valley tech veteran who recently joined the non-profit RISC-V International organisation as CTO.
“Because of that, it offers flexibility, customisation and the ability to collaborate with others around the world. Thirty years ago creating a computer chip took $100m and a team of 30 people working for three years.
“Last year at the China Academy of Science four undergraduates designed and built a RISC-V chip in four months with a budget of $12,000.
“We’ve seen a renaissance in software and databases and a renaissance in technology; the tools and the fabrication ability that are out there are phenomenal.”
Nvidia: Arm-ed and dangerous?
The chip market continues to be dominated by two architectures; x86 in personal computing and Arm for mobile devices.
Arm’s licensing model, which sees it sell IP to chip manufacturers without producing any silicon itself, has made it the ‘Switzerland’ of the chip market, and remaining vendor-neutral has proved hugely popular with manufacturers. Its designs have taken a dominant position in the mobile phone market, as well as other growing sectors such as IoT devices and connected vehicles.
“Nvidia competes in the same markets as several of Arm’s current clients,” says Alan Priestley, vice-president analyst for technology and service providers at Gartner.
He adds: “If Nvidia attempts any kind of integration there will be concerns.
“Some companies, like Apple, license Arm’s technology and create their own designs, but because Arm is so prevalent in the market others, like Qualcomm and MediaTek, take the standard Arm IP and put it in their products.
Enter RISC-V?
Emerging in 2010 from the Parallel Computing Lab at UC Berkeley in California, RISC-V is a modular instruction set architecture (ISA) which allows developers to build whatever they desire on top of the core instruction set. RISC-V International is now the focal point for a growing community of 750 members in 50 countries around the world.
“It’s built by a community in the same way Linux or Apache were,” says Himelstein. “If you go back to 1990 people would be saying ‘why do Linux?’, but now 30 years later, if you’re not doing Linux you’re not doing anything.
“This thing has the ability to last for the next 50 years,” he continues. “The way they’ve set it up is that there’s the base set of 47 instructions, and you can add extensions on top of that. If the standards aren’t there, people can add them themselves, so Alibaba recently created a cloud-targeted server.”
De-Risc is a consortium of companies building a platform technology for the space industry, based on RISC-V architecture involving software and hardware elements.
“I think RISC-V is an important development. The idea that that there’s a collaborative and open source approach to microprocessor design is really a desirable step.
“It might easily take ten years for RiSC-V to give Arm a really hard competitive time in the market, but it definitely could happen. The fact that it’s open and available for all to see is very much going with the theme of how modern IT development works generally, both in software and hardware.”
Gartner’s Priestley is less confident that RISC-V architecture can topple Arm and Intel, and says deep pockets will be required to build a processor that can truly match Arm’s powerful A-core designs.
“You could build a RISC-V processor to compete with the A-cores but you will have to make a big investment to do it and it’s going to take a company that’s got good architectural design capabilities,” he says. “There’s no reason why it couldn’t be done, but it doesn’t exist at present.
“Someone like Qualcomm might do it if they don’t like the way Nvidia is taking Arm, but it will be years before we see the effect the deal has on the market.”
He believes it’s more likely that RISC-V will “stay at the lower end of the market” and be used for building simple, single-core operations for low-end microcontrollers.
Himelstein is, perhaps unsurprisingly, more optimistic.
He says: “For CIOs and people working in IT, this is exciting because we believe having multiple architectures out there is good for business and good for technology. You don’t have to have a one-size-fits-all solution.
“Having a third choice which reflects the way the world is going in terms of open-source is good for pricing and gives you, as a customer or implementer, a chance to open new markets and attack different workloads.”
Tomi Engdahl says:
CVA6: A Linux-Capable RISC-V CPU
CORE-V CVA6 is a RISC-V CPU that can boot an embedded Linux image.
https://www.hackster.io/news/cva6-a-linux-capable-risc-v-cpu-299a40a5f871
Tomi Engdahl says:
Andes adds to its Linux-ready RISC-V line-up with L2 and multi-core ready models
http://linuxgizmos.com/andes-adds-to-its-linux-ready-risc-v-line-up-with-l2-and-multi-core-ready-models/
Tomi Engdahl says:
RISC-V, the Linux of the chip world, is starting to produce technological breakthroughs
RISC-V, the open standard for chip instructions, is leading to some impressive technical innovation, one of its creators says
https://www.zdnet.com/article/risc-v-the-linux-of-the-chip-world-is-starting-to-produce-technological-breakthroughs/
Tomi Engdahl says:
Micro Magic RISC-V Core Claims to Beat Apple M1 and Arm Cortex-A9
https://www.eetimes.com/micro-magic-risc-v-core-claims-to-beat-apple-m1-and-arm-cortex-a9/
Micro Magic has introduced what it claims is the world’s fastest 64-bit RISC-V core — a device it says outperforms the Apple M1 chip and Arm Cortex-A9. The company feels it has elegantly implemented David Patterson’s original vision for the reduced instruction set computer (RISC) architecture, working comfortably within the power budgets of today’s battery-powered devices.
In late October 2020, Micro Magic issued a terse, two-sentence announcement. It had demonstrated a 64-bit RISC-V core achieving 5GHz and 13,000 CoreMarks at 1.1V. It said a single Micro Magic core running at 0.8V nominal delivers 11,000 CoreMarks at 4.25GHz, consuming only 200mW.
Micro Magic is a privately-held EDA vendor based in California, specializing in three-dimensional TSV (through silicon via) layout tools. It claims to be able to load, view and edit design of over one trillion transistors in real time. The company was founded in 1995, sold to Juniper Networks for $260 million, and in 2004 reborn with the same name by the original founders.
“Using the EEMBC benchmark, we get 55,000 CoreMarks per Watt. The M1 chip is roughly the equivalent of 10,000 CoreMarks in EEMBC terms; divide this by eight cores and 15W total, and that is less than 100 CoreMarks per Watt.” Going on to make a comparison with Arm, he added, “The fastest Arm processor under EEMBC benchmarks is the Cortex-A9 (quad-core), with a figure of 22,343 CoreMarks. Divide this by four cores and 5W per core, and you get 1,112 CoreMarks per Watt.”
Tomi Engdahl says:
http://linuxgizmos.com/64-bit-risc-v-core-claims-10x-better-coremarks-watt-compared-to-other-3-5ghz-cpus/
Tomi Engdahl says:
https://www.tomshardware.com/news/seagate-develops-risc-v-cores
Tomi Engdahl says:
Micro Magic RISC-V Core Claims to Beat Apple M1 and Arm Cortex-A9
https://www.eetimes.com/micro-magic-risc-v-core-claims-to-beat-apple-m1-and-arm-cortex-a9/
Micro Magic has introduced what it claims is the world’s fastest 64-bit RISC-V core — a device it says outperforms the Apple M1 chip and Arm Cortex-A9. The company feels it has elegantly implemented David Patterson’s original vision for the reduced instruction set computer (RISC) architecture, working comfortably within the power budgets of today’s battery-powered devices.
In late October 2020, Micro Magic issued a terse, two-sentence announcement. It had demonstrated a 64-bit RISC-V core achieving 5GHz and 13,000 CoreMarks at 1.1V. It said a single Micro Magic core running at 0.8V nominal delivers 11,000 CoreMarks at 4.25GHz, consuming only 200mW.
Tomi Engdahl says:
http://linuxgizmos.com/codasip-unveils-linux-ready-risc-v-cores-with-ai-and-multi-core-support/
Tomi Engdahl says:
https://www.edn.com/risc-v-enabled-som-aids-embedded-development/
Tomi Engdahl says:
https://riscv.org/blog/2020/12/risc-v-microarchitecture-for-kids-steve-hoover-redwood-eda/
Tomi Engdahl says:
https://bit-tech.net/news/micro-magic-64-bit-risc-v-cpu-runs-at-5ghz-on-1w/1/
Tomi Engdahl says:
BeagleBoard.org Foundation and Seeed Studio have announced a partnership with StarFive to launch the most affordable Linux-capable RISC-V SBC yet, the $149 BeagleV.
$149 BeagleV Is the Most Affordable RISC-V Single-Board Computer Yet — But Supplies Are Limited
https://www.hackster.io/news/149-beaglev-is-the-most-affordable-risc-v-single-board-computer-yet-but-supplies-are-limited-3534004f9c13
Demand is likely to be high, but Hackster readers are invited to skip the queue and pick up a board from the pilot production run.
Tomi Engdahl says:
CES 2021: RISC-V’s journey from experimentation to commercial processors
https://www.edn.com/ces-2021-a-peek-at-risc-vs-journey-from-initial-experimentation-to-commercial-processors/
What’s the RISC-V movement all about? What are the major misconceptions about RISC-V? Has it moved from initial experimentation to practical implementation? At the all-digital CES 2021, a panel discussion hosted by Engadget’s Chris Schodt took a closer look at this research project turned design movement.
Tomi Engdahl says:
Rediscovering RISC-V: Apple M1 sparks renewed interest in non-x86 architectures
https://www.zdnet.com/article/what-risc-v-and-why-you-should-care/
With the runaway success of the new ARM-based M1 Macs, non-x86 architectures are getting their closeup. RISC-V is getting the most attention from system designers looking to horn-in on Apple’s recipe for high performance. Here’s why.
Tomi Engdahl says:
Designed for the company’s XuanTie C910 chip, the open source Android 10 build is ready for porting — and comes ready for QEMU use.
Alibaba’s T-Head Releases Open Source Android 10 Port for RISC-V Chips
https://www.hackster.io/news/alibaba-s-t-head-releases-open-source-android-10-port-for-risc-v-chips-1b3265755785
Designed for the company’s XuanTie C910 chip, the open source Android 10 build is ready for porting — and comes ready for QEMU use.
T-Head, Alibaba’s semiconductor division, has released a port of Android 10 to the RISC-V instruction set architecture — and this time it’s a functional build with a full graphical user interface.
There’s considerable interest in using the free and open source RISC-V architecture in future mobile devices, not least for companies like Huawei who have found themselves at risk of being cut off from licensing proprietary Arm IP. The news that PLCT Lab had successfully booted Android 10 on RISC-V, then, was welcomed late last year – but came with the proviso that it was a minimal system, offering only a simple shell and not the full graphical experience users expect of the Android mobile platform proper.
T-Head’s porting effort is rather further along: The company has showcased a fully-functional build of the Android Open Source Project (AOSP) version of Android 10, running on its in-house XuanTie 910 RISC-V processor
Tomi Engdahl says:
RV64X: A Free, Open Source GPU for RISC-V
https://www.eetimes.com/rv64x-a-free-open-source-gpu-for-risc-v/
A group of enthusiasts are proposing a new set of graphics instructions designed for 3D graphics and media processing. These new instructions are built on the RISC-V base vector instruction set. They will add support for new data types that are graphics specific as layered extensions in the spirit of the core RISC-V instruction set architecture (ISA). Vectors, transcendental math, pixel, and textures and Z/Frame buffer operations are supported. It can be a fused CPU-GPU ISA. The group is calling it the RV64X as instructions will be 64-bit long (32 bits will not be enough to support a robust ISA).
Tomi Engdahl says:
RISC-V based SoC is 5G basestaton on a chip
http://linuxgizmos.com/74100-2/
Tomi Engdahl says:
Featuring CNN, cryptographic, and audio acceleration, plus a Trust-M security chip, the new K210 AI Accelerator is an impressive add-on.
XaLogic Launches Its $38 RISC-V Edge AI K210 AI Accelerator HAT for Raspberry Pi Vision, Voice
Featuring CNN, cryptographic, and audio acceleration, plus a Trust-M security chip, the new K210 AI Accelerator is an impressive add-on.
https://www.hackster.io/news/xalogic-launches-its-38-risc-v-edge-ai-k210-ai-accelerator-hat-for-raspberry-pi-vision-voice-dacc38578b6b
Tomi Engdahl says:
https://www.eetimes.com/can-open-source-hardware-emulate-linux/
Tomi Engdahl says:
Android 10 portattiin avoimelle RISC-V-prosessorille
https://etn.fi/index.php?option=com_content&view=article&id=11698&via=n&datum=2021-02-01_15:06:02&mottagare=30929
Tomi Engdahl says:
RISC-V Processor Designs Emerge
https://www.eetimes.com/risc-v-processor-designs-emerge/
Open source hardware based on RISC-V processor designs has a bit of drift compared to its software counterpart: The framework freezes instruction set architecture (ISA) as a durable long-term component. Here, ISA is the vocabulary that processors understand, so software is written in that vocabulary. How software is coded in that language tells the processor what to do.
Anyone can take the RISC-V ISA and design other aspects such as extensions. What’s the hardware approach has in common with open source software is that RISC-V is free of IP entanglements, and participants can share the results of their design efforts.
In short, RISC-V allows design engineers to innovate, providing them the freedom of choice.
Tomi Engdahl says:
https://semiengineering.com/risc-v-becoming-less-risky-with-the-right-verification/
Tomi Engdahl says:
https://etn.fi/index.php/13-news/11698-android-10-portattiin-avoimelle-risc-v-prosessorille
Tomi Engdahl says:
Can RISC-V Do for GPUs What It’s Done for CPUs?
Can RISC-V handle GPU chores? Work is underway to make it happen through the creation of a small, area-efficient design with custom programmability and extensibility.
https://www.electronicdesign.com/industrial-automation/article/21154315/jon-peddie-research-can-riscv-do-for-gpus-what-its-done-for-cpus?utm_source=EG+ED+IoT+for+Engineers&utm_medium=email&utm_campaign=CPS210209088&o_eid=7211D2691390C9R&rdx.ident%5Bpull%5D=omeda%7C7211D2691390C9R&oly_enc_id=7211D2691390C9R
GPU land has been a proprietary place where the inner workings are the IP and secret sauce of developers like AMD, Intel, Nvidia, and a few others. What if there was a new set of graphics instructions designed for 3D graphics and media processing? Well, there may be.
Tomi Engdahl says:
HANDS-ON: THE RISC-V ESP32-C3 WILL BE YOUR NEW ESP8266
https://hackaday.com/2021/02/08/hands-on-the-risc-v-esp32-c3-will-be-your-new-esp8266/
Tomi Engdahl says:
Exploring The Open Source That Really Goes Into A RISC-V Chip
https://hackaday.com/2021/02/27/exploring-the-open-source-that-really-goes-into-a-risc-v-chip/
Tomi Engdahl says:
Linux Foundation and RISC-V International launch free RISC-V training classes
https://www.zdnet.com/article/linux-foundation-risc-v-international-launch-free-risc-v-training-classes/
The hot new open-source RISC-V chips now have free introductory classes to help you get up to speed with this new hardware.
Tomi Engdahl says:
https://etn.fi/index.php/13-news/11855-risc-v-laajentaa-autojen-jarjestelmiin
Tomi Engdahl says:
Is #OpenSourceHardware a lost opportunity? #software #RISCV #technology
https://buff.ly/38y4k3A
Tomi Engdahl says:
An Insider’s View Of Verifying Custom RISC-V Processor Cores
How RISC-V verification ecosystems support flexibility in approaching a custom processor design.
https://semiengineering.com/an-insiders-view-of-verifying-custom-risc-v-processor-cores/
Tomi Engdahl says:
RISC-V Extension Boasts Dramatic Improvements in Ultra-Low Power IoT Wireless Signal Processing
https://www.hackster.io/news/risc-v-extension-boasts-dramatic-improvements-in-ultra-low-power-iot-wireless-signal-processing-b54b9fd5ce27
Extensions to the open source ISA offer “substantial energy savings” for common IoT protocols including LoRa and Bluetooth Low Energy.
Tomi Engdahl says:
RISC-V: How much is open source? Featuring the new ESP32-C3
https://www.youtube.com/watch?v=VdPsJW6AHqc
When I got these new RISC-V ESP32 boards in my mail, I asked myself: Is this new technology revolutionary as written everywhere? What are the advantages for a typical Maker? Time for a closer look. But pay attention: It will be a rough ride and not for the fainthearted because we will talk about “stacks,” “IP,” “ecosystems,” and a lot about standardization.
If you hang on till the end, you should have enough knowledge to impress your boss. But maybe you will not be happy.
Tomi Engdahl says:
https://semiengineering.com/week-in-review-design-low-power-140/?cmid=f05c93b6-0f56-44a8-a16d-4505a667f76f
Imperas Software released riscvOVPsimCOREV, a free Instruction Set Simulator (ISS) based on the Imperas reference models of the OpenHW Group’s processor RISC-V core IP. The ISS can be configured for the complete range of the OpenHW CORE-V processor IP portfolio, including the RTL-frozen CV32E40P (formally known as PULP RI5CY), the under-development CV32E40S and CV32E40X, plus the upcoming CVA6-32/64 bit (formally known as PULP ARIANE), and will be extended overtime to cover the future roadmap of CORE-V.
Imperas releases free ISS for RISCV-V CORE-V developers in the OpenHW ecosystem
https://www.imperas.com/articles/imperas-releases-free-iss-riscv-v-core-v-developers-openhw-ecosystem
Tomi Engdahl says:
https://semiengineering.com/week-in-review-design-low-power-140/?cmid=f05c93b6-0f56-44a8-a16d-4505a667f76f
Codasip and Veridify Security teamed up to provide secure boot functionality for the Codasip Low Power Embedded RISC-V processors. The new security features are enabled by Veridify’s quantum-resistant security methods that can confirm the firmware used by these processors during the boot process is authentic. It can also be used to enable additional security features like secure firmware updates, authentication, and data protection. The security features will be available in the second half of 2021.
https://codasip.com/2021/03/30/codasip-to-offer-secure-boot-solutions-with-veridify-tools/
Tomi Engdahl says:
https://semiengineering.com/week-in-review-auto-security-pervasive-computing-61/?cmid=f05c93b6-0f56-44a8-a16d-4505a667f76f
Codasip’s Low Power Embedded RISC-V processors will have a secure boot function from IoT and edge IoT security experts Veridify Security as of the second half of 2021. The two companies are partnering to offer Veridify’s security algorithms and tools, which are small enough for the IoT, embedded environment.
https://codasip.com/2021/03/30/codasip-to-offer-secure-boot-solutions-with-veridify-tools/
Tomi Engdahl says:
RISC-V is obviously not considered risk-y, considering that it dominates the mobile phone market and is gaining traction in computers that have been the province of Intel and Arm.
RISC-V Star Rises Among Chip Developers Worldwide
https://spectrum.ieee.org/tech-talk/semiconductors/design/riscv-rises-among-chip-developers-worldwide
Most of the smartphones in our pockets contain computer chips based on Arm architecture, whereas Intel’s x86 architecture reigns supreme among laptops, desktops, and server hardware. But a fast-growing number of companies in the U.S., Europe, and especially Asia have been turning to the open-source chip architecture called RISC-V. It allows even startups to design custom chips without the expensive licensing fees required to use proprietary chip architectures.
Originally developed by researchers at the University of California, Berkeley, starting in 2010, RISC-V represents one of many instruction set architectures (ISAs) that allow programmers and the software they write to directly control computer hardware. The open-source flexibility of RISC-V has made it an increasingly popular chip architecture for companies such as computing storage giants Seagate and Western Digital Corp., China’s e-commerce giant Alibaba, along with government initiatives backed by the U.S. military’s Defense Advanced Research Projects Agency (DARPA).
“There’s a lot of multi-denominational companies that don’t subscribe to having all the wood behind one arrow,” says Mark Himelstein, chief technology officer at RISC-V International.
Tomi Engdahl says:
Based on the ESP32-C3, the new ESP32-C6 adds Wi-Fi 6 connectivity — tweaked, Espressif notes, specifically for the IoT.
RISC-V-Powered Espressif ESP32-C6 Brings the Company’s First Wi-Fi 6 802.11ax Connectivity
https://www.hackster.io/news/risc-v-powered-espressif-esp32-c6-brings-the-company-s-first-wi-fi-6-802-11ax-connectivity-c985553157c9
Based on the ESP32-C3, the new ESP32-C6 adds Wi-Fi 6 connectivity — tweaked, Espressif notes, specifically for the IoT.
Designed for devices that require wireless connectivity with integrated security, the ESP32-C6 is built around a single 32-bit core based on the free and open-source RISC-V instruction set architecture (ISA) and running at up to 160MHz. Alongside that is 400kB of static RAM (SRAM), 384kB flash ROM, support for external flash, and 22 programmable general-purpose input/output (GPIO) pins supporting ADC, SPI, UART, I2C, I2S, RMT, TWAI and PWM.
Wireless connectivity, meanwhile, includes Espressif’s first 802.11ax Wi-Fi 6 block, a major upgrade over the Wi-Fi 4 connectivity of the earlier ESP32-C3, which the company says it has tweaked for Internet of Things (IoT) applications. The chip supports 20MHz bandwidth in 802.11ax or 20/40MHz in 802.11b/g/n mode, supports a station interface, and boosts transmission efficiency and power consumption over Wi-Fi 6 equivalents.
The new part also includes Bluetooth 5 Low Energy (BLE) connectivity and a security block which includes hardware acceleration for SHA and AES plus a hardware random-number generator, HMAC and digital signature system,, RSA-3072 secure boot, and support for encrypting flash content through XTS-AES-128.
Tomi Engdahl says:
Homebrew RISC-V Computer Has Beauty And Brains
https://hackaday.com/2021/04/13/homebrew-risc-v-computer-has-beauty-and-brains/
Tomi Engdahl says:
https://etn.fi/index.php/13-news/12020-risc-v-prosessori-piille-jo-5-nanometrissa
Tomi Engdahl says:
Allwinner launches the first RISC-V application processor
https://www.eetimes.com/allwinner-launches-the-first-risc-v-application-processor/
Allwinner Technology today announced the launch of 「D1」 processor, which is the world’s first mass-produced application processor equipped with T-Head Xuantie 906 based on RISC-V, providing an exciting new smart chipset for immediate use in today’s developing Artificial Intelligence of Things (AIoT) market.