Here are some of my collection of newest trends and predictions for year 2018. I have not invented those ideas what will happen next year completely myself. I have gone through many articles that have given predictions for year 2018. Then I have picked and mixed here the best part from those articles (sources listed on the end of posting) with some of my own additions to make this posting.This article contains very many quotations from those source articles (hopefully all acknowledged with link to source).
The general trend in electronics industry is that the industry growth have been driven by mobile industry. Silicon content in smartphones and other mobile devices is increasing as vendors add greater functionality. Layering on top of that are several emerging trends such as IoT, big data, AI and smart vehicles that are creating demand for greater computing power and expanding storage capacity.
Manufacturing trends
According to Foundry Challenges in 2018 article the silicon foundry business is expected to see steady growth in 2018. The growth in semiconductor manufacturing will remain steady, but there will be challenges in the manufacturing capacity and expenses to move to the next nodes. For most applications, unless you must have highest levels of performance, there may not be as compelling a business case to focus on the bleeding-edge nodes. Over the last two years, the IC industry has experienced an acute shortage of 200mm fab capacity (legacy MCU, power, sensors, 6-micron to 65nm). In 2018, 200mm capacity will remain tight. An explosion in 200mm demand has set off a frenzied search for used semiconductor manufacturing equipment that can be used at older process nodes. The problem is there is not enough used equipment available. The profit margins in manufacturing are so thin in markets served by those fabs that it’s hard to justify paying current rising equipment prices, and newcomers may have a tough time making inroads. Foundries with fully depreciated 200mm equipment and capacity already are seeing increased revenues in their 200mm business.The specialty foundry business is undergoing a renaissance, thanks to the emergence of 5G and automotive.
300mm is expected to follow a similar path for lack of capacity because 300mm fabs already produce leading-edge chips and more mainstream 300mm demand is driven by MCUs, wireless communications and storage applications. Early predictions are for solid growth in 2018, fueled by demand for memory and logic at advanced 10/7nm.
In 2017, marking the first time that the semiconductor equipment market has exceeded the previous market high of US$47.7 billion set in 2000. Fab tool vendors found themselves in the midst of an unexpected boom cycle in 2017, thanks to enormous demand for equipment in 3D NAND and, to a lesser degree, DRAM. In 2018, equipment demand looks robust, although the industry will be hard-pressed to surpass the record growth figures in 2017. In 2018, 7.5 percent growth is expected to result in sales of US$60.1 billion for the global semiconductor equipment market – another record-breaking year. Demand looks solid across the three main growth drivers for fab tool vendors—DRAM, NAND and foundry/logic.
Rising demand for chips is hitting the IC packaging supply chain, causing shortages of select manufacturing capacity, various package types, leadframes and even some equipment. Spot shortages for some IC packages began showing up in 2017, but the problem has been growing and spreading since then, so packaging customers may encounter select shortages well into 2018. Apple Watch 3 shipment growth to benefit Taiwan IC packagers in 2018.
Market for advanced packaging begins to diverge based on performance and price. Advanced Packaging is now viewed as the best way to handle large amounts of data at blazing speeds.
Moore’s law
Many recent publications say Moore’s Law is dead. Though Moore’s Law is dead may be experiencing some health challenges, it’s not time to start digging the grave for the semiconductor and electronics market yet.
Even smaller nodes are still being taken to use in high end chips. The node names are confusing. Intel’s 10nm technology is roughly equivalent to the foundry 7nm node.In 2018, Intel is expected to finally ramp up 10nm finally in the first half of 2018. In addition, GlobalFoundries, Samsung and TSMC will begin to ship their respective 7nm finFET processes. On the leading edge, GlobalFoundries, Intel, Samsung and TSMC start migrating from the 16nm/14nm to the 10nm/7nm logic nodes. It is expected that some chip-makers face some challenges on the road. Time will tell if GlobalFoundries, Samsung and TSMC will struggle at 7nm. Early predictions are for solid growth in 2018, fueled by demand for memory and logic at advanced 10/7nm. 7nm is projected to generate sales from $2.5 billion to $3.0 billion in 2018. Over time 10nm/7nm is expected to be a big and long-running node. Suppliers of FPGAs and processors are expected to jump on 10nm/7nm.
South Korea’s Samsung Electronics said it has commenced production of the second generation of its 10nm-class 8-Gb DDR4 DRAM. Devices labeled 10nm-class have feature sizes as small as 10 to 19 nanometers. With the continued need for shrinking pattern dimensions, semiconductor manufacturers continue to implement more complex patterning techniques, such as advanced multi-patterning, for the 10nm design node and beyond. They also are investing significant development effort in readying EUV lithography for production at the 7/5nm design nodes. Samsung is planning to begin transitioning to EUV for logic chips next year at the 7nm node, although it is unclear when the technology will be put into production for DRAM.
There will be talk on even smaller nodes. FinFETs will get extended to at least to 5nm, and possibly 3nm in next 5 years. The path to 5nm loks pretty clear. FinFETs will get extended at least to 5nm. It’s possible they will get extended to 3nm. EUV will be used at new nodes, followed by High NA Lithography. New smaller nodes challenges the chip design as abstractions become more difficult at 7nm and beyond. Models are becoming more difficult to develop, integrate and utilize effectively at 10/7nm and beyond as design complexity, process variation and physical effects add to the number of variables that need to be taken into account. Materials and basic structures may diverge by supplier, at 7 nm and beyond. Engineering and scientific teams at 3nm and beyond will require completely different mixes of skills than today.
Silicon is still going strong, but the hard fact is that CMOS has been running out of steam for several nodes, and that becomes more obvious at each new node. To extend into new markets and new process nodes Chipmakers Look To New Materials. There are a number of compounds in use already (generally are being confined to specific niche applications), such as gallium arsenide, gallium nitride, and silicon carbide. Silicon will be supplemented by 2D materials to extend Moore’s Law. Transition metal dichalcogenides (TMDCs), a class of 2D materials derived from basic elements—principally tellurium, selenium, sulfur, and oxygen—are being widely explored by researchers. TMDCs are functioning as semiconductors in conjunction with graphene. Graphene, the wonder material rediscovered in 2004, and a host of other two-dimensional materials are gaining ground in manufacturing semiconductors as silicon’s usefulness begins to fade. Wide-bandgap semiconductor materials like gallium nitride (GaN) and silicon carbide (SiC) are anticipated to be used in many more applications in 2018. Future progress increasingly will require a mix of different materials and disciplines, but silicon will remain a key component.
Interconnect Materials need to to be improved. For decades, aluminum interconnects were the industry standard. In the late 1990s, chipmakers switched to copper. Over the years, transistors have decreased dramatically in size, so interconnects also have had to scale in size leading to roadblock known as the RC challenge. Industry is investing significant effort in developing new approaches to extend copper use and finding new metals. There’s also some investigation into improvements on the dielectric side. The era of all-silicon substrates and copper wires may be coming to an end.
Application markets
Wearables are a question mark. Demand for wearables slowed down in 2017 so much that smart speakers likely outsold wearable devices in 2017 holiday season. eMarketer is estimating that usage of wearable will grow just 11.9 percent in 2018, rising from 44.7 million adult wearable users in 2017 to 50.1 million in 2018. On the other hand market research firm IDC estimates that the shipments of wearable electronics devices are projected to more than double over the next five years as watches displace fitness trackers as the biggest sellers. IDC forecasts that wearables shipments will increase at a compound annual growth rate of 18.4 percent between 2017 and 2021, rising from 113.2 million this year to 222.3 million in 2021. At the same time fitness trackers are expected to become commodity product. Tomorrow’s wearables will become more fully featured and multi-functional.
The automotive market for semiconductors is shifting into high gear in 2018. Right now the average car has about $350 worth of semiconductor content, but that is projected to grow another 50% by 2023 as the overall automotive market for semiconductors grows from $35 billion to $54 billion. The explosion of drive-by-wire technology, combined with government mandates toward fully electric powertrains, has changed this paradigm—and it impacts more than just the automotive industry. Consider implications beyond the increasingly complex vehicle itself, including new demands on supporting infrastructure. The average car today contains up to 100 million lines of code. Self-driving car will have considerably more code in it. Software controls everything from safety critical systems like brakes and power steering, to basic vehicle controls like doors and windows. Meeting ISO 26262 Software Standards is needed but it will not make the code bug free. It’s quickly becoming common practice for embedded system developers to isolate both safety and security features on the same SoC. The shift to autonomous vehicles marks a major shift in the supply chain—and a major opportunity.
Many applications have need for a long service life — for example those deployed within industrial, scientific and military industries. In these applications, the service life may exceed that of component availability. Replacing an advanced, obsolete components in a design can be very costly, potentially requiring an entire redesign of the electronic hardware and software. The use of programmable devices helps designers not only to address component obsolescence, but also to reduce the cost and complexity of the solution. Programmable logic devices are provided in a range of devices of different types, capabilities and sizes, from FPGAs to System on Chips (SoC) and Complex Programmable Logic Devices (CPLD). The obsolete function can be emulated within the device, whether it is a logic function implemented in programmable logic in a CPLD, FPGA or SoC, or a processor system implemented in an FPGA or SoC.
Become familiar with USB type C connector. USB type C connector is becoming quickly more commonplace than any other earlier interface. In the end of 2016 there were 300 million devices using a USBC connection – a big part was smartphones, but the interface was also widespread on laptops. With growth, the USBC becomes soon the most common PC and peripheral interface. Thunderbolt™ 3 on USBC connector promises to fulfill the promise of USB-C for single-cable docking and so much more.
Power electronics
The power electronics market continues to grow and gain more presence across a variety of markets. 2017 was a good year for electric vehicles and the future of this market looks very promising. In 2017, we saw also how wireless charging technology has been adopted by many consumer electronic devices- including Apple smart phones. Today’s power supplies do more than deliver clean and stable dc power on daily basis—they provide advanced capabilities that can save you time and money.
Wide-bandgap semiconductor materials like gallium nitride (GaN) and silicon carbide (SiC) are anticipated to be used in many more applications in 2018. At the moment, the number of applications for those materials is steadily increasing in the automotive and military industry. Expect to see more adoption of SiC and GaN materials in automotive market.
According to Battery Market Goes Bigger and Better in 2018 article advances in battery technologies hold the keys to continuing progress in portable electronics, robotics, military, and telecommunication applications, as well as distributed power grids. It is difficult to see lithium-ion based batteries being replaced anytime soon, so the advances in battery technology are primarily through the application of lithium-ion battery chemistries. New battery protection for portable electronics cuts manufacturing steps and costs for Lithium-ion.
Transparency Market Research analysts predict that the global lithium-ion battery market is poised to rise from $29.67 billion in 2015 to $77.42 billion in 2024 with a compound annual growth rate of 11.6 %. That growth has already spread from the now ubiquitous consumer electronics segment to automotive, grid energy, and industrial applications. Dramatic increase is expected for battery power for the transportation, consumer electronic, and stationary segments. According to Bloomberg New Energy Finance (BNEF), the global energy-storage market will double six times between 2016 and 2030, rising to a total of 125 G/305 gigawatt-hours. In 2018, energy-storage systems will continue proliferating to provide backup power to the electric grid.
Memory
Memory business boomed in 2017 for both NAND and DRAM. The drivers for DRAM are smartphones and servers. Solid-state drives (SSDs) and smartphones are fueling the demand for NAND. Both the DRAM and NAND content in smartphones continues to grow, so memory business will do well in 2018.Fab tool vendors found themselves in the midst of an unexpected boom cycle in 2017, thanks to enormous demand for equipment in 3D NAND and, to a lesser degree, DRAM. In 2018, equipment demand looks robust, although the industry will be hard-pressed to surpass the record growth figures in 2017.
NAND Market Expected to Cool in Q1 from the crazy year 2017, but it is still growing well because there is increasing demand. The average NAND content in smartphones has been growing by roughly 50% recently, going from approximately 24 gigabytes in 2016 to approximately 38 gigabytes today.3D NAND will do the heavy memory lifting that smartphone users demand. Contract prices for NAND flash memory chips are expected to decline in during the first quarter of 2018 as a traditional lull in demand following the year-end quarter.
Lots of 3D NAND will go to solid state drives in 2018. IDC forecasts strong growth for the solid-state drive (SSD) industry as it transitions to 3D NAND. SSD industry revenue is expected to reach $33.6 billion in 2021, growing at a CAGR of 14.8%. Sizes of memory chips increase as number of layer in 3D NAND are added. We’ve already scaled up to 48 layers. Does this just keep scaling up, or are there physical limits here? Maybe we could see a path to 256 layers in few years.
Memory — particular DRAM — was largely considered a commodity business. Though that it’s really not true in 2017. DRAM memory marked had boomed in 2017 at the highest rate of expansion in 23 years, according to IC Insights. Skyrocketing prices drove the DRAM market to generate a record $72 billion in revenue, and it drove total revenue for the IC market up 22%. Though the outlook for the immediate future appears strong, a downturn in DRAM more than likely looms in the not-too-distant future. It will be seen when there are new players on the market. It is a largely unchallenged assertion that Chinese firms will in the not so distant future become a force in semiconductor memory market. Chinese government is committed to pumping more than $160 billion into the industry over a decade, with much of that ticketed for memory startups.
There is search for faster memory because modern computers, especially data-center servers that skew heavily toward in-memory databases, data-intensive analytics, and increasingly toward machine-learning and deep-neural-network training functions, depend on large amounts of high-speed, high capacity memory to keep the wheels turning. The memory speed has not increased as fast as the capacity. The access bandwidth of DRAM-based computer memory has improved by a factor of 20x over the past two decades. Capacity increased 128x during the same period. For year 2018 DRAM remains a near-universal choice when performance is the priority. There has been some attempts to very fast memory interfaces. Intel the company has introduced the market’s first FPGA chip with integrated high-speed EMBED (Embedded Multi-Die Interconnect Bridge): The Stratix 10 MX interfaces to HMB2 memory (High Memory Bandwidth) that offers about 10 times faster speed than standard DDR-type DIMM.
There is search going on for a viable replacement for DRAM. Whether it’s STT-RAM or phase-change memory or resistive RAM, none of them can match the speed or endurance of DRAM. Necessity is the mother of invention, and we see at least two more generations after 1x. XPoint is also coming up as another viable memory solution that could be inserted into the current memory architecture. It will be interesting to see how that plays out versus DRAM.
5G and IoT
5G something in it for everyone. 5G is big. 5G New Radio (NR) wireless technology will ultimately impact everyone in the electronics and telecommunications industries. Most estimates say 2020 is when we will ultimately see some real 5G deployments on a scale. In the meantime, companies are firming up their plans for whatever 5G products and services they will offer. Though test and measurement solutions will be key in the commercialization cycle. 5G is set to disrupt test processes. If 5G takes off, the technology will propel the development of new chips in both the infrastructure and the handset. Data centers require specialty semiconductors from power management to high-speed optical fiber front-ends. 5G systems will drive more complexity in RF front-ends .5G will offer increased capacity and decreased latency for some critical applications such as vehicle-to-vehicle (V2V) or vehicle-to-infrastructure (V2I) communications for advanced driver assistance systems (ADAS) and self-driving vehicles. The big question is whether 5G will disrupt the landscape or fall short of its promises.
Electronics manufacturers expect a lot from Internet of Thing. The evolution of intelligent electronic sensors is creating a revolution for IoT and Industrial IoT as companies bring new sensor-based, intelligent systems to market. The business promise is that the proliferation of smart and connected “things” in the Industrial Internet of Things (IIoT) provides tremendous opportunities for increased performance and lower costs. Industrial Internet of Things (IIoT) has a market forecast approaching $100 billion by 2020. Turning volumes of factory data into actionable information that has value is essential. Predictive maintenance and asset tracking are two big IoT markets to watch in 2018 because they will provide real efficiencies and improved safety. It will be about instrumenting our existing infrastructures with sensors that improve their reliability and help predict failures. It will be about tracking important assets through their lifecycles.
A new breed of designers has arrived that is leveraging inexpensive sensors to build the intelligent systems at the edge of the Internet of Things (IoT). They work in small teams, collaborate online, and they expect affordable design tools that are easy to use in order to quickly produce results. Their goal is to deliver a functioning device or a proof-of-concept to their stakeholders while spending as little money as possible to get there. We need to become multi-functional engineers who can comfortably work in the digital, RF, and system domains.
The Io edge sensor device usually needs to be cheap. Simple mathematical reasoning suggests that the average production cost per node must be small, otherwise the economics of the IoT simply are not viable. Most suppliers to the electronics industry are today working under the assumption that the bill-of-materials (BoM) cost of a node cannot exceed $5 on average. While the sensor market continues to garner billions of dollars, the average selling price of a MEMS sensor, for example, is only 60 cents.
Designing a well working and secure IoT system is still hard. IoT platforms are very complex distributed systems and managing these distributed systems is often an overlooked challenge. When designing for the IoT, security needs to be addressed from the Cloud down to each and every edge device. Protecting data is both a hardware and a software requirement, as more data is being stored and analyzed in edge devices and gateways.
The continued evolution of powerful embedded processors is enabling more functionality to be consolidated into single heterogeneous multicore devices. You will see more mixed criticality designs – those designs which contain both safety-critical and non-safety critical processes running on the same chip. It’s quickly becoming common practice for embedded system developers to isolate both safety and security features on the same SoC.
AI
There is clearly a lot of hype surrounding machine learning (ML) and artificial intelligence (AI) fields. Over the past few years, machine learning (ML) has evolved from an interesting new approach that allows computers to beat champions at chess and Go, into one that is touted as a panacea for almost everything. Machine learning already has delivered beneficial results in certain niches, but it has potential for a bigger and longer lasting impact because of the demand for broad insights and efficiencies across industries. Also EDA companies have been investing in this technology and some results are expected to be announced.
The Battle of AI Processors Begins in 2018. Machine learning applications have a voracious appetite for compute cycles, consuming as much compute power as they can possibly scrounge up. As a result, they are invariably run on parallel hardware – often parallel heterogeneous hardware—which creates development challenges of its own. 2018 will be the start of what could be a longstanding battle between chipmakers to determine who creates the hardware that artificial intelligence lives on. Main contenders on the field at the moment are CPUs, GPUs, TPUs (tensor processing units), and FPGAs. Analysts at both Research and Markets and TechNavio have predicted the global AI chip market to grow at a compound annual growth rate of about 54% between 2017 and 2021.
Sources:
Battery Market Goes Bigger and Better in 2018
Smart speakers to outsell wearables during U.S. holidays, as demand for wearables slows
Wearables Shipments Expected to Double by 2021
The Week In Review: Manufacturing #186
Five technology trends for 2018
NI Trend Watch 2018 explores trends driving the future faster
Creating Software Separation for Mixed Criticality Systems
Isolating Safety and Security Features on the Xilinx UltraScale+ MPSoC
Meeting ISO 26262 Software Standards
DRAM Growth Projected to be Highest Since ’94
NAND Market Expected to Cool in Q1
Memory Market Forecast 2018 … with Jim Handy
3D NAND Storage Fuels New Age of Smartphone Apps
$55.9 Billion Semiconductor Equipment Forecast – New Record with Korea at Top
Advanced Packaging Is Suddenly Very Cool
Apple Watch 3 shipment growth to benefit Taiwan IC packagers in 2018
Rapid SoC Proof-of-Concept for Zero Cost
EDA Challenges Machine Learning
What Can You Expect from the New Generation of Power Supplies?
Optimizing Machine Learning Applications for Parallel Hardware
FPGA-dataa 10 kertaa nopeammin
Chipmakers Look To New Materials
What the Experts Think: Delivering the next 5 years of semiconductor technology
Programmable Logic Holds the Key to Addressing Device Obsolescence
The Battle of AI Processors Begins in 2018
For China’s Memory Firms, Legal Tests May Loom
Predictions for the New Year in Analog & Power Electronics
Lithium-ion Overcomes Limitations
Will Fab Tool Boom Cycle Last?
The Next 5 Years Of Chip Technology
Chipmakers Look To New Materials
Process Window Discovery And Control
Sensors are Fundamental to New Intelligent Systems
Industrial IoT (IIoT) – Where is Silicon Valley
Internet of things (IoT) design considerations for embedded connected devices
How efficient memory solutions can help designers of IoT nodes meet tight BoM cost targets
1,325 Comments
Tomi Engdahl says:
Podcast Transcript: Artificial Intelligence Meets Verification Technology
https://www.eeweb.com/profile/max-maxfield/articles/podcast-transcript-artificial-intelligence-meets-verification-technology
Tomi Engdahl says:
5 Takeaways From ISS 2018
Fake nodes, fan-out and robocars were addressed at the event.
https://semiengineering.com/5-takeaways-from-2018-iss/
Ranging forecasts
What’s the outlook for the IC market in 2018? Right now, there is no consensus among the analysts. Some see zero growth, while one predicts a repeat of 2017. Most are in the middle.
At ISS, Daniel Niles, founder and portfolio manager at AlphaOne NexGen Technology Fund, was bearish. In 2017, semiconductor sales were on track for 21% growth and 15% unit growth, “but end markets are not that strong with inventory building at the customer level,” according to Niles’ slide presentation at ISS.
As a result, AlphaOne predicts that the IC industry will see 0% growth in terms of sales in 2018. IC unit growth is expected to grow by 6%, but average selling prices (ASPs) will fall by 6%, according to the firm. “Major semiconductor customers have very high inventory year-over-year and so does their supply chain,” according to AlphaOne.
Then, at a separate event, Bill McClean, president of IC Insights, was more upbeat with a forecast that reflects the consensus. In total, the IC market is expected to reach $393.9 billion in 2018, up 8.3% over 2017, according to IC Insights. IC unit growth is projected to increase 11%, but ASPs could fall by 2%, according to the firm.
Malcolm Penn, chief executive of Future Horizons, is the most bullish. In 2018, Penn sees the IC market reaching nearly $500 billion, up 21.1% over 2017. The analyst says the super-cycle will continue barring a major economic disaster.
Demystifying fan-out
The world of IC packaging is an important but confusing business. Over the years, the industry has developed a plethora of different package types with an assortment of acronyms.
Why so many? Packaging is somewhat of a custom business. Customers also want a package that optimizes the performance of the chip. And that’s why packaging is key. But there is no one package type that can meet all needs. Simple chips require commodity packages. The most complex chips require advanced packages. And then there are a bunch of packaging requirements in between.
Fake nodes
In a recent article, I addressed an ongoing trend in the IC business: Foundries are flooding the market with new nodes and different process options at existing nodes, spreading confusion and creating a variety of challenges for chipmakers.
At ISS, a panel addressed some of the same issues. One of the first issues the panel addressed is obvious—What are nodes? Today, there are full nodes, but some are pushing quarter and half nodes. Some nodes are more real than others, at least according to one expert. “The panel is going to talk about nodes and something I wrote earlier about the importance that we should not have fake nodes maybe,” said G. Dan Hutcheson, chief executive of VLSI Research, at ISS. “We have fake nodes and we have inter-nodes. It is really complex.”
Fudging the node names is not a new idea. In the 1970s, the industry began to measure nodes by “drawn gate length,” according to Hutcheson. But about that time, some started to use electrical gate length as a measurement, which created some confusion. “We actually had a fake node at that time. It’s what I call a marketing node,” he said.
Over time, the definition of the nodes changed. Then, Moore’s Law became one of the guiding principles. The axiom states that the transistor count doubles on a chip with each process generation. The transistor specs followed the same path.
“Historically, the industry has been following this law, and has named each successive process node approximately 0.7 times smaller than the previous one – a linear scaling that implies a doubling of density,”
Intel has proposed a standard metric for the nodes. So far, though, the proposal has followed on deaf ears.
So what is a real node? “Full nodes, at least from an Intel perspective, need to target close to a 2X transistor density improvement compared to the previous node,”
Tomi Engdahl says:
Nodes Vs. Nodelets
https://semiengineering.com/nodes-vs-node-lets/
Growing number of process options is creating confusion across the semiconductor industry.
There are full-node processes, such as 10nm and 7nm, with 5nm and 3nm in R&D. But there also is an increasing number of half-nodes or “node-lets” being introduced, including 12nm, 11nm, 8nm, 6nm and 4nm.
Node-lets are derivatives of full-node processes. For example, 12nm and 11nm are slightly more advanced versions of 16nm/14nm. And 8nm and 6nm fall under the same category as 7nm.
Tomi Engdahl says:
What EUV Brings To The Table
https://semiengineering.com/what-euv-brings-to-the-table/
Adoption of this technology will enable scaling for a few more nodes, but it won’t be easy.
Transistor Options Beyond 3nm
https://semiengineering.com/transistor-options-beyond-3nm/
Complicated and expensive technologies are being planned all the way to 2030, but it’s not clear how far the scaling roadmap will really go.
Tomi Engdahl says:
http://www.powerelectronics.com/power-management/defects-high-voltage-ceramic-capacitors-found-acoustically?NL=ED-003&Issue=ED-003_20180202_ED-003_957&sfvc4enews=42&cl=article_2_b&utm_rid=CPG05000002750211&utm_campaign=15203&utm_medium=email&elq2=cec9f5185a7840c1a96a3c1b2cb6b92f
Tomi Engdahl says:
Fan-Out Wars Begin
https://semiengineering.com/fan-out-wars-begin/
The number of low-density packaging options is increasing as the popularity of advanced packaging grows.
Tomi Engdahl says:
Testing Analog Chips
https://semiengineering.com/testing-analog-chips/
Increasing numbers of analog components could help perk up this market after years of steady but sleepy growth.
The world of analog components is broad and diverse, and while testing analog chips may not take as long as running tests on complex SoCs, there are different requirements for analog devices.
One type of chip that’s seeing more application these days is analog microelectromechanical system devices. Automotive electronics call for a number of analog chips, along with MEMS.
Mixed-signal ICs, which combine analog and digital elements, are a related field.
Risto Puhakka, president of VLSI Research, estimates the total analog tester market to be worth about $100 million a year, largely for testing linear chips and discrete devices. “This is kind of a quiet, sleepy segment,” he adds. “The testers live forever.”
Tomi Engdahl says:
ATE Tailwind For 2018?
Will test equipment have another big year?
https://semiengineering.com/ate-tailwind-for-2018/
The automatic test equipment market enjoyed a record sales year during 2017, and there are indications that the good times will continue this year.
Forecasters are predicting another robust year for sales of DRAMs and NAND flash memory devices, especially 3D NAND. That will drive demand for memory test equipment to keep up.
Frost & Sullivan predicts semiconductor test equipment will have a compound annual growth rate of 4.2% from 2015 to 2022, with worldwide revenue hitting $5.4 billion by 2022. The Asia-Pacific region will continue to dominate ATE sales; more than three-quarters of ATE revenue will come from the Asia-Pacific installed base, the market research firm says.
Advantest is one of the largest ATE suppliers. For its fiscal third quarter ended December 31, the company reported its net sales rose 29.5% from the same period a year earlier. Net income was up slightly.
For the Semiconductor and Component Test System segment, orders in the nine months ending December 31 were up 43.2% from a year ago.
The ATE vendor sees business conditions improving in this quarter, and the “favorable business environment” will likely continue in the next fiscal year, the company said in a statement.
Tomi Engdahl says:
NI Trend Watch 2018
https://semiengineering.com/ni-trend-watch-2018/
IIoT mandates, 5G disruption to test, breaking Moore’s Law, and the effects of electrification.
Tomi Engdahl says:
Round-the-clock power from smart bowties
https://discovery.kaust.edu.sa/en/article/471/round-the-clock-power-from-smart-bowties
Innovative diode design uses ultrafast quantum tunneling to harvest infrared energy from the environment.
Tomi Engdahl says:
Mass production of new class of semiconductors closer to reality
http://electroiq.com/blog/2018/02/mass-production-of-new-class-of-semiconductors-closer-to-reality/
Two Waterloo chemists have made it easier for manufacturers to produce a new class of faster and cheaper semiconductors.
The chemists have found a way to simultaneously control the orientation and select the size of single-walled carbon nanotubes deposited on a surface. That means the developers of semiconductors can use carbon as opposed to silicon, which will reduce the size and increase the speed of the devices while improving their battery life.
Tomi Engdahl says:
Understanding Your Chip’s Age
https://semiengineering.com/understanding-your-chips-age/
The effects and mechanisms of chip aging, plus how to predict a device’s lifetime.
Tomi Engdahl says:
Device provides years of power through temperature swings
https://www.engadget.com/2018/02/18/mit-thermal-resonator/
You wouldn’t need a battery to run gadgets around the clock.
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Device provides years of power through temperature swings
You wouldn’t need a battery to run gadgets around the clock.
Jon Fingas
02.18.18 in Gadgetry
Eventually, you might not need a battery or a conspicuous external power source to keep a device running for years on end. A team at MIT has created a device that produces energy by exploiting the temperature swings that occur between day and night. Known as a thermal resonator, it uses a hybrid of materials that produce both high heat conduction and capacity. A copper or nickel foam at its core is coated with graphene to boost its conductivity, and is infused with a phase-changing material (octadecane) that serves as storage.
The initial device was relatively tiny, and only produced 1.3 milliwatts of power. That’s enough for basic sensors or communication sensors
System draws power from daily temperature swings
http://news.mit.edu/2018/system-draws-power-daily-temperature-swings-0215
Technology developed at MIT can harness temperature fluctuations of many kinds to produce electricity
the new system takes advantage of the swings in ambient temperature that occur during the day-night cycle.
The new system, called a thermal resonator, could enable continuous, years-long operation of remote sensing systems, for example, without requiring other power sources or batteries, the researchers say.
The findings are being reported in the journal Nature Communications
Tomi Engdahl says:
Race Of Nations
https://semiengineering.com/race-of-nations/
Technology leadership is no longer just about companies. It is becoming a matter of national pride and survival, and semiconductors are at the epicenter.
Technology is the next arms race, and this is not just about national defense in the traditional sense. Countries collectively are pouring hundreds of billions of dollars into developing technology for the future, from education to outright grants and seed funding, and they are working with private industry to continue investing in their respective national futures.
Which technologies and nations will win is unknown at this point. Areas such as AI, machine learning and cloud computing are not new concepts, but they have ignited a frenzy of activity. And autonomous vehicles were somewhere on the road map of the next 30 years until Tesla uncorked its self-driving software, setting off one of the biggest technology scrambles in decades.
Tomi Engdahl says:
What EUV Brings To The Table
https://semiengineering.com/what-euv-brings-to-the-table/
Adoption of this technology will enable scaling for a few more nodes, but it won’t be easy.
After many years of hearing that EUV is almost ready for prime time, the tide is finally coming in. A decade of slow but steady progress has resulted in exposure tools that can expose on the order of 1,000 wafers a day on a regular basis. This may be shy of the requirements for high volume manufacturing (HVM), but it is certainly more than enough to support solid development programs and pilot line production. Almost all leading edge manufacturers have announced plans for early introduction in the 2018-19 timeframe, with HVM to follow within 1- 2 years if the economics and technology are proven to be viable
From a mask making perspective, the key technical issues have long been identified as mask blank and multi-layer defectivity, mask blank and patterned mask inspection, defect review and pellicles.
Detecting CD defects on a background pattern with 3-5 nm of LER will be challenging, to say the least. CD uniformity presents similar challenges.
EUV is coming. The successful adoption of this technology for HVM may drive Moore’s Law for another few nodes, but it will not be easy. The mask making community must play a key role in enabling viable EUV strategies for the entire process.
Tomi Engdahl says:
Dipping in the Hardware Emulation Archives
http://www.electronicdesign.com/test-measurement/dipping-hardware-emulation-archives?NL=ED-003&Issue=ED-003_20180219_ED-003_349&sfvc4enews=42&cl=article_2_b&utm_rid=CPG05000002750211&utm_campaign=15417&utm_medium=email&elq2=b808b8d0462c4b0eb6a5bb61c2bf28c6
From its FPGA-based beginnings to today’s advanced architectures used by a select group of companies, emulation has changed dramatically over the past three decades.
Every verification engineer today knows about hardware emulation and its capabilities. Some may know it’s a technology employed since the 1980s. However, not everyone knows the story of emulation’s winding path from a tool relegated to the dusty backrooms to widespread adoption, or the players involved.
In the second part of the 1980s, hardware emulation sprang from the invention of the field-programmable gate array (FPGA). By building an array of interconnected FPGAs configured to “emulate” the behavior of a design before silicon, it was possible to verify the design at speeds unapproachable by any software-based simulation algorithm. The high-speed led to testing the design-under-test (DUT) with real input-output traffic via a physical target system, where ultimately the chip would reside once released by the foundry. The DUT combined with the target system setup is called in-circuit emulation or ICE.
FPGA-based emulators were time-consuming to deploy and rather difficult to use. In fact, the industry devised the expression “time-to-emulation” (TTE) to measure the time required to bring up the DUT for emulation and start to emulate it. Measured in several months, the TTE often exceeded the time it took for the foundry to release first silicon.
By the middle of the 1990s, a few innovative startups proposed new technologies to overcome the drawbacks. They believed that only custom-made silicon designed for emulation held the promise to remove the pitfalls of the old class of emulators.
New Design Approaches
From the start, all of the initiatives were based on custom reprogrammable devices deployed in two rather different emulation architectures.
One made use of a custom FPGA designed to provide 100% native internal visibility of the DUT without compiling probes. The unique architecture also offered easier setup time and significantly faster compilation speed.
The other architecture took a radically different approach, achieving the same objectives: 100% native visibility into the DUT, easier setup time, and very fast compilation speed. It was called a custom-processor-based emulator.
Twenty years later, these design approaches are the architectures for today’s hardware emulation, though far, far superior to the early days
Tomi Engdahl says:
Entering 2018 on Solid Ground
http://www.semi.org/en/entering-2018-solid-ground
2017 finished on an upturn – both in the USA and globally. Based on consolidated fourth-quarter actual and estimated revenues of 213 large, global electronic manufacturers, sales rose in excess of 7 percent in 4Q’17 vs. 4Q’16
Total global electronic equipment sales increased more than 7 percent in the fourth quarter and SEMI equipment revenues rose 32 percent.
2017 was a strong year and 2018 is off to a good start! The 2017 lofty growth rates will temper, but this current expansion will likely continue.
Tomi Engdahl says:
FD-SOI Adoption Expands
https://semiengineering.com/fd-soi-adoption-expands/
Technology shifts direction after years of competing directly with CMOS at advanced nodes.
Fully depleted silicon-on-insulator (FD-SOI) is gaining ground across a number of new markets, ranging from IoT to automotive to machine learning, and diverging sharply from its original position as a less costly alternative to finFET-based designs.
For years, FD-SOI has been viewed as an either/or solution targeted at the same markets as bulk CMOS. Among the differences:
FD-SOI transistors are planar, so they are simpler and less expensive to design and manufacture than 3D finFETs. Manufacturing requires only minimal double patterning at 22nm and beyond, whereas 10/7nm finFETs require multiple patterning on multiple layers, as well as complex power management schemes to deal with dynamic power density and leakage current, which is a growing problem at 10/7nm and beyond.
FD-SOI supports body biasing, which can be utilized to significantly reduce energy consumption.
The technology has a built-in insulator layer to control leakage current and minimize capacitance and various types of noise.
FD-SOI also does not require channel doping, which is where the term “fully depleted” comes from. It is scalable at least to 10nm
And it can be sourced at both GlobalFoundries and Samsung
All of those factors have contributed to FD-SOI’s growth. But the momentum appears to be building almost independently of the aggressive advanced-node roadmaps for the mobile and server world, where EUV, taller finFETs, gate-all-around FETs, and increasingly smaller features remain the central focus.
Pros and cons
FD-SOI has a couple of well-understood advantages. One is that it is a planar technology, which makes it simpler to design, manufacture and test. The first layer consists of an ultra-thin buried oxide, which is added onto a silicon substrate. Because it is so thin, there is no reason to dope the channel.
Second, the insulator layer reduces the capacitance between the drain and the source, which in turn allows chipmakers to deploy body biasing, which is a way of optimizing a circuit’s power and performance by tuning the threshold voltage. In effect, the circuit is either powered on more quickly or slowly as needed by utilizing the difference between the source voltage and the body voltage.
So far, most of the body biasing has been uni-directional. That will change at future nodes, and there are workarounds even today.
New markets
That fits well with automotive and industrial IoT applications, where most chips need to be robust but not necessarily at the leading-edge processes.
“FD-SOI exhibits 100X to 1,000X lower radiation effects than other types of chips,” said Soitec’s Maleville. “That’s a big issue for automotive companies. So is low power. Car companies want to use chips in different areas without having to add cooling units. If you can have a lower operating temperature, you also improve the reliability of the devices.”
That has pushed some big-name companies into the FD-SOI world, including NXP and Intel. NXP is offering multiple platforms for different markets based upon FD-SOI. Intel, meanwhile, rejected FD-SOI in favor of bulk CMOS for its processors.
Tomi Engdahl says:
Qualcomm deals blow to Broadcom’s bid with sweetened NXP deal
https://www.reuters.com/article/us-nxp-semicondtrs-m-a-qualcomm/qualcomm-deals-blow-to-broadcoms-bid-with-sweetened-nxp-deal-idUSKCN1G41AE
U.S. semiconductor company Qualcomm Inc (QCOM.O) on Tuesday unveiled a sweetened $44 billion agreement to acquire NXP Semiconductors NV (NXPI.O)
The new deal puts pressure on Broadcom to decide if it will stick with a stipulation in its bid that Qualcomm does not raise its offer for NXP.
Broadcom said on Tuesday it was evaluating its options in response to Qualcomm’s move
The new NXP deal came less than a week after Broadcom and Qualcomm executives met face-to-face for the first time to discuss the differences between the two sides.
Tomi Engdahl says:
Transistor Options Beyond 3nm
https://semiengineering.com/transistor-options-beyond-3nm/
Complicated and expensive technologies are being planned all the way to 2030, but it’s not clear how far the scaling roadmap will really go.
Despite a slowdown in chip scaling amid soaring costs, the industry continues to search for a new transistor type 5 to 10 years out—particularly for the 2nm and 1nm nodes.
Specifically, the industry is pinpointing and narrowing down the transistor options for the next major nodes after 3nm. Those two nodes, called 2.5nm and 1.5nm, are slated to appear in 2027 and 2030, respectively, according to the International Technology Roadmap for Semiconductors (ITRS) version 2.0. Another organization, Imec, is more aggressive with the timetable, saying that 2.5nm or thereabouts will arrive by 2024.
Tomi Engdahl says:
Opinion: AMD goes after $15 billion ‘embedded’ market with two new chips
https://www.marketwatch.com/story/amd-goes-after-15-billion-embedded-market-with-two-new-chips-2018-02-21
Embedded markets tend to be consistent and stable, without the frequent changes required in the consumer PC market
Advanced Micro Devices, bringing modern processor and graphics designs to as many market segments as possible, announced two new families Wednesday that address the embedded processor space.
The Sunnyvale, Calif.-based company has already posted double-digital year-over-year sequential growth in revenue from embedded markets, but the release of the Epyc Embedded 3000 and Ryzen Embedded V1000 family create an additional opportunity.
$15 billion market
Research firm IDC estimates the market size that AMD can address with this pair of chip families exceeds $14 billion to $15 billion a year. The largest portion of that ($11 billion-$12 billion) includes storage and networking infrastructure systems that the Epyc 3000 line will target. The remaining amount includes internet of things (IoT) gateways, medical systems and casino gaming hardware, and is the purview of the Ryzen V1000.
Competitors in this space include Intel INTC, +4.21% (with its Xeon D-series and Core family of chips) and many Arm-based designs that focus on low power integration.
Both the Epyc 3000 and Ryzen V1000 chips represent the first time AMD has targeted embedded customers with specific features and capabilities at the hardware level.
Tomi Engdahl says:
Tech Talk: 5/3nm Parasitics
What to expect at future process nodes.
https://semiengineering.com/tech-talk-5-3nm-parasitics/
Ralph Iverson, principal R&D engineer at Synopsys, talks about parasitic extraction at 5/3nm and what to expect with new materials and gate structures such as gate-all-around FETs and vertical nanowire FETs.
Tomi Engdahl says:
Integrated Circuit Technology Advances Continue to Amaze
Despite increasing costs of development, IC manufacturers are still making great strides.
http://www.icinsights.com/news/bulletins/Integrated-Circuit-Technology-Advances-Continue-To-Amaze/
Tomi Engdahl says:
Semiconductor Industry 8-Point Policy Plan for 2018
https://www.eetimes.com/author.asp?section_id=36&doc_id=1332989
Tomi Engdahl says:
Engineering in the Twilight of Moore’s Law
It’s all about finding and riding the big waves
https://spectrum.ieee.org/at-work/innovation/engineering-in-the-twilight-of-moores-law
Tomi Engdahl says:
Why EDA Needs To Change
https://semiengineering.com/why-eda-needs-to-change/
EDA exists because it was too expensive for semiconductor companies to develop and maintain tools, but they must continue to be part of the innovation cycle.
Why is it taking so long for machine learning to have an impact within EDA? Most of the time when I talk to the experts within the field I hear about why designs are so different from other machine learning applications, and I know that is true.
Random is the key word there. I often have wondered when simulator data structures were built, if the memory could be organized more like the traffic flow in the design. But I am sure if it had been worth the effort, someone would have done it.
But not all data within EDA is so unstructured. Trace data, which is essential for functional verification and debug is very structured. It is time-based, and a lot of it is very regular.
EDA has been slow in finding ways to fully capture parallel processing. A lot of that goes back to the randomness, but I think a significant part of it is that EDA is being squeezed.
Parallelization is often difficult.
It is a cycle, but it has to start by giving users the ability to create new solutions by themselves. EDA has to open up the data and trust their customers. Semiconductor companies can, and should, be part of the EDA innovation cycle.
Tomi Engdahl says:
GE Lighting finds buyer for EMEA operations
http://www.ledsmagazine.com/articles/2018/02/ge-lighting-finds-buyer-for-emea-operations.html?eid=293591077&bid=2015907
GE has taken a big step in unloading its lighting businesses, reaching an agreement to sell GE Lighting’s Budapest-based European, Middle East, and Africa operations (GE calls it EMEAT for Europe, Middle East, Africa and Turkey), plus GE’s Global Automotive Lighting group, to a company controlled by the former president of GE Hungary.
The entire workforce of those units — over 4000 people in total — will transfer to the new entity
GE Lighting focuses on conventional lighting as well as on the home LED market, while Current is an energy consulting group that digitally links commercial users’ LED lights, solar panels, electric batteries, car chargers, and the like to help reduce energy costs and consumption.
Philips Lighting will be no more: It’s changing its name
http://www.ledsmagazine.com/articles/2018/02/philips-lighting-will-be-no-more-it-s-changing-its-name.html?eid=293591077&bid=2015907
After a solid fourth quarter reaffirmed the importance of services and Internet connectivity to the company’s future, CEO Eric Rondolat reveals that a new moniker is coming soon.
The world’s largest lighting company said that sales for the quarter ending Dec. 31 and for the year were €1.89 billion and €6.97 billion, respectively. A 3% increase in comparable sales for the quarter helped nudge yearly comparable sales growth to 0.5%, reversing a decline that Philips had suffered in 2016, when the quarter fell by 3.2% and the year dropped by 2.4%.
The biggest percentage growth came in the home sector — a young market where Philips sells smart systems based on its Hue line of LED bulbs that change brightness, color, and CCT prompted by many different Internet inputs — followed by the professional sector, in which Philips typically sells Internet-connected lighting to cities and commercial entities. Both considerably outgrew LED electronics — circuitry that Philips sells to lamp and luminaire makers, which was flat for the quarter — as well as conventional lamps, which shrunk.
Tomi Engdahl says:
Qualcomm Taps Samsung’s 7nm EUV for 5G
https://www.eetimes.com/document.asp?doc_id=1332996
Qualcomm said it will continue to work with longtime foundry supplier Samsung Electronics on Snapdragon 5G chipsets using Samsung’s 7nm Low Power Plus (LPP) process technology with extreme ultraviolet (EUV) lithography.
Samsung aims to take the lead in putting long-delayed EUV into production, with plans to use it in its 7nm LPP process starting in the second half of this year. Other leading-edge chip makers– including Intel, TSMC and Globalfoundries–are targeting EUV production sometime in 2019.
Tomi Engdahl says:
MediaTek Goes Back to ASIC
https://www.eetimes.com/document.asp?doc_id=1333004
MediaTek is going back into the ASIC business.
In a one-on-one interview with EE Times at the Mobile World Congress, Joe Chen, president of MediaTek, told us that the Taiwan consumer chip giant has big plans to provide “premier ASIC design services” to system vendors in consumer, communication and computing markets.
“MediaTek has been known as an ASSP company for a long time,” said Chen, “but we now see growth opportunities by becoming an ASIC company.”
Tomi Engdahl says:
Snapdragon Scores Embedded Wins
https://www.eetimes.com/author.asp?section_id=36&doc_id=1332993
Best known for its smartphone processors, Qualcomm is quietly gaining ground in the embedded market.
Best known for its smartphone processors, Qualcomm is quietly gaining ground in the embedded market. The company’s processors power many new designs, including sports glasses from Everysight, a smart thermostat from Johnson Controls (JCI), and intelligent digital signage from Nanolumens. They also appear in smart cameras and VR glasses, among other design wins. The company’s new Snapdragon 820E aims to extend this winning streak.
Smartphone technology is Qualcomm’s not-so-secret weapon. By adapting its mobile processors for embedded applications, the company can deliver a unique combination of powerful CPUs, a complete multimedia subsystem, and wireless connectivity — all at lower power than competing embedded processors. The new 820E processor, for example, provides four Kryo CPUs at up to 2.35GHz plus a high-performance GPU, 4K video engine, and image processor, yet it fits within a smartphone power budget.
Tomi Engdahl says:
Do We Need More Power Engineers?
http://www.powerelectronics.com/community/do-we-need-more-power-engineers?NL=ED-003&Issue=ED-003_20180220_ED-003_418&sfvc4enews=42&cl=article_1_b&utm_rid=CPG05000002750211&utm_campaign=15431&utm_medium=email&elq2=0dfd078ece604baa82eda456e9977214
“Do we need more power engineers?” is a short, simple question with a correspondingly short, simple answer: “it depends.” In this case it depends on many factors, among them how you define “power engineer,” how you assess the “right number,” and what a power engineer is worth.
On one side, companies say they can’t get enough engineers, a contention often supported by data plus anecdotes from economists and academics. On the other side, engineers say that their wages haven’t risen in real terms (which a true shortage would cause); there are often large-scale layoffs; professors just want to fill seats; and what companies really want is a large supply of engineers who are experienced, immediately able to support the project, and cheap, too.
The problem is that there isn’t an easy way to conclude what the “correct” number of engineers is; it’s analogous to asking “what’s the best op amp out there?” In the end, where you stand on the matter largely depends on where you sit, as the cliché goes.
What about power engineers, specifically? Although the situation is fluid, one trend is clear. Fewer engineers are designing power supplies from scratch, even at the moderate currents in the range of 2 to 10 A. Among the reasons: the available “buy” options very attractive and growing, while at the same time, the do-it-yourself “make” option is becoming more challenging.
While it is not that hard to design a good supply, a good one just isn’t good enough anymore. Today’s supplies must not only provide basic functions and performance (output accuracy, line/load regulation, and wide input range, to give a few examples), but they must also provide a menu of protection features (overcurrent, under/overvoltage, thermal) as starters—and those are the easier additional demands. If DC/DC isolation is needed, that brings new requirements to achieve certification (think “creep” and “clearance”).
However, the most-challenging supply demands related to meeting efficiency and EMI/RFI performance standards, along with their increasingly stringent regulatory mandates. Even an experienced supply designer knows that squeezing that extra one or two percentage points of efficiency from a design (and doing so across a wide range of loads and operating modes) is very difficult.
At the same time, the few who do understand the intricacies of supply architectures and algorithms (SEPIC, zero-voltage switching, hysteretic control, voltage-mode control, current-mode control, valley current-mode control) have distilled their knowledge into power regulator/controller ICs.
As a result, the dominant role of the power engineer is changing. Rather than designing supplies, their needed expertise is deploying them. After all, even with a very good supply which by itself meets all requirements, there are still issues of power-rail routing, IR drop, parasitics, packaging, using ferrites to suppress EMI, assessing and implementing cooling tactics…it’s a long list of what it takes to put that well-designed supply in its place without degrading its performance.
So, the answer to the first question is really dependent on why these power engineers are needed. If it is to design supplies (or converters or regulators), the answer is that there probably are enough practitioners of this elusive art
If it is to be able to effectively apply a qualified design
—the answer is that we don’t yet know.
The word is there is demand for more power engineers. Assuming that’s true—which is debatable—what sort of power engineering will they be doing?
Tomi Engdahl says:
Chapter 1: Power Supply Fundamentals
http://www.powerelectronics.com/power-electronics-systems/chapter-1-power-supply-fundamentals?NL=ED-003&Issue=ED-003_20180220_ED-003_418&sfvc4enews=42&cl=article_2_b&utm_rid=CPG05000002750211&utm_campaign=15431&utm_medium=email&elq2=0dfd078ece604baa82eda456e9977214
The key component of the dc power management system is the power supply that provides dc power for the associated system.
Tomi Engdahl says:
How Are RF Trends Impacting Connectors?
http://www.mwrf.com/components/how-are-rf-trends-impacting-connectors?NL=MWRF-001&Issue=MWRF-001_20180220_MWRF-001_239&sfvc4enews=42&cl=article_1_b&utm_rid=CPG05000002750211&utm_campaign=15435&utm_medium=email&elq2=99dc979739a04b0087e46caa5c3f578c
Cables and connectors may not always be the first aspect of a project that one considers, but they are nevertheless important—and increasingly so as they accommodate today’s demands, including smaller-size devices.
Devices are becoming smaller and more complex, whether it is a smartphone, medical imaging device, or a remote sensor accessing military satellite systems. At the same time, the devices still need to be rugged enough to withstand enormous amounts of wear and tear while offering unhindered data transmission and collection capabilities.
The new requirements of electronic product manufacturing mean that connector components need to be redesigned for these devices
many OEMs are searching for microwave assemblies that provide higher-speed interfaces up to 67 GHz that utilize 1.85-mm connectors capable of high mating cycles.
Device systems are now trending toward fiber-optic and microwave cables due to the tremendous amounts of data being transmitted and received. These complex systems are moving from traditional single-digit GHz performance levels to frequency requirements above 40 GHz.
Military system applications sometimes require RF cables that can disconnect on command. Due to this requirement, connectors can experience problems when disconnecting at the wrong times or from pin-mating issues.
Changing the number and position of pins can help to alleviate the issue of having a sure mating while allowing for the cable to disconnect when desired. However, operating systems have moved toward needing higher performance at frequencies of 28 GHz or more. Present keying schemes have only allowed for frequencies as high as 8 GHz.
Keyed coaxial connectors are being introduced for electronics that allow for 18-GHz performance while providing keyed position options. This setup minimizes mating issues while providing a more reliable connection to handle systems that experience high shock and vibration in varied environments.
RF connectors need to be designed in the correct configuration desired for the specific product or application
Tomi Engdahl says:
Smartphone slump has chipmakers pondering fate of ‘supercycle’
iPhone X production cut sends memory prices falling by 10%
https://asia.nikkei.com/Business/Trends/Smartphone-slump-has-chipmakers-pondering-fate-of-supercycle
Prices of memory chips have dropped around 10% in three months, triggering worries that the global semiconductor industry may be entering a correction phase.
The culprits behind the fall are Apple, which halved output of its flagship iPhone X in the January-March quarter, and Chinese smartphone makers such as Oppo and Vivo, whose remarkable growth has come to a halt. What happens to semiconductor prices affects a host of players, from materials suppliers to makers of semiconductor production equipment, and the industry has reached a critical juncture.
After all, chip demand is expected to grow, not only for smartphones but also household appliances in the age of the internet of things. And as investment in base stations for 5G mobile networks gets into full swing in the second half of 2018, demand for data center servers will grow in order to cope with a surge in volumes.
Tomi Engdahl says:
Nokia has, along with 12 partners, developed a concept where the production facility can be set up anywhere, anywhere within a few hours. The concept has a fun name: a factory in a box.
In fact, it is a container that can be driven to the desired location. With a container, startup can quickly start prefabrication, the old manufacturer can use it to showcase new products, and when production stops, it can be quickly restarted with a container.
Source: http://etn.fi/index.php?option=com_content&view=article&id=7613&via=n&datum=2018-02-23_15:57:15&mottagare=31202
Tomi Engdahl says:
DOCSIS 3.1 noise mitigation: Check your grounds
http://www.broadbandtechreport.com/articles/2018/01/docsis-3-1-noise-mitigation-check-your-grounds.html?cmpid=enl_btr_docsis_31_2018-02-22&pwhid=6b9badc08db25d04d04ee00b499089ffc280910702f8ef99951bdbdad3175f54dcae8b7ad9fa2c1f5697ffa19d05535df56b8dc1e6f75b7b6f6f8c7461ce0b24
Since the dawn of time, individuals have known that they need to protect themselves from lightning. In the beginning, humans were only concerned with protecting themselves. As time went on and infrastructures were constructed, it became evident that those things needed to be protected, too. Through trial and error, society figured out how to design and construct lightning rods that could take the energy generated from lightning and harmlessly return it to the earth.
A balancing act
With the advent of DOCSIS
3.1, companies not only have to be concerned that the grounds in hubs and headends are adequate in the sense that they meet the absolute ohm specification of the ground for safety of people and protection of property, but also that the various elements of that ground are balanced. That means that they must make sure that each of the various metallic “runs” that make up the ground have the same resistance.
Elements of the hub and headend ground
There are various elements that make up the hub and headend ground, including shelves that are bonded to racks with screws and wires, racks that are bonded together to make aisles, as well as aisles that are bonded to bus bars.
Why balance is important
Balancing the elements of a ground is always important because of the antennas that imbalances create for RF. But we had enough power difference between the signal and the noise to more-or-less harmlessly “absorb” the noise. What changed?
Because of potential energy coming into the plant, when we go from 64-QAM (quadrature amplitude modulation) to 256-QAM channels, we need to lower our noise floor by 3 dB just to stay even with MER (modulation error rate) and BER (bit error rate). Bonding up to 32 of these channels adds to the potential for interference, for noise.
By balancing the ground circuits, noise is reduced. Lab experiments and tests in actual hubs confirmed that if an unbalance of 0.8 ohms in the ground circuits can be reduced to 0.3 ohms, the noise floor in the 5 MHz to 50 MHz spectrum can be reduced by 8 dBmV.
How to determine if grounds are balanced
We cannot measure the resistance value of a ground at a shelf or similar place in a hub or headend. We can, however, easily measure and compare the continuity and balance of the various ground circuits of a hub or headend.
Fixing the balance
Daisy-chained ground circuits can be changed to home runs if the headend and hub grounds are not balanced.
Tomi Engdahl says:
Power Averaging to Save Weight, Cost, and Space
http://www.powerelectronics.com/dc-dc-converters/power-averaging-save-weight-cost-and-space?NL=ED-003&Issue=ED-003_20180222_ED-003_22&sfvc4enews=42&cl=article_2_b&utm_rid=CPG05000002750211&utm_campaign=15503&utm_medium=email&elq2=86779a468ad346b4a2235396b30a952e
Many dc power systems that are configured with dc-dc converters are designed to regulate voltage up to a maximum power level and have a maximum current and power rating. If the load tries to draw more than the rated current out of the supply, the supply will typically go into a current limiting mode that will either fold back the output voltage of the supply or the supply will shut down and restart. The current limit is typically set just above the maximum rated current so at the voltage set point of the converter, full power delivery can be achieved. A converter rated for 500 watts at 48 VDC will have a maximum continuous current rating of 500 watts/48VDC or 10.4A. The current limiting feature may start at 13A. The current limiting feature is typically designed for load faults only where the converter will see current limit only a few times in its life. If the converter isn’t designed to go into current limit as a normal mode of operation, you can stress components within the converter and shorten the life of the power system.
If the load draws more than the maximum current but below the current limit at the voltage set point, then you can overpower the supply and cause eventual power system failure. So a 500 watt converter at 48 VDC with a current limit set at 13A will be overpowered at up to 624 watts before current limiting starts. The typical configuration for a power averaging supply is shown in Fig. 1. The dc-dc converter is sized for the average power and the capacitor is sized to deliver the peak power while keeping the POL converters or load voltage within its specifications. U1 can be a simple circuit that switches in bulk capacitance during converter start up.
The large bulk capacitance can cause many complications for the dc power system. At turn-on the larger capacitor, which in many cases can be in the thousands of microfarads, can draw the dc supply into current limit.
When the dc supply successfully powers up by safely charging the capacitor the power system must be stable. With some dc-dc converters, the large capacitor can destabilize the voltage control loop, which can cause supply or system failure.
The circuitry around the module can become very complex if the power converter isn’t designed to handle a large capacitor at its output. There are dc converter modules (DCMs) that are designed to handle large amounts of capacitance at their outputs. DCMs are inherently designed to operate within their maximum current rating and power rating even when driving capacitance values as large as 10KuF and more if the additional capacitance is switched in during start up.
At startup the DCM will drive the capacitor up to voltage while staying within its safe operating area. Once the capacitor is charged, the control loop of the converter is design to be stable during normal operation. If the application is designed for power averaging, the initial power burst into the downstream POLs will be greater than the converter’s capability.
Power averaging configurations are very effective when the POL converter or load can tolerate a wide input voltage range.
Supplies configured for power averaging are very effective for reducing the size, weight, and cost of power systems where the load is on for a short periodic duration. The support circuitry can be minimized if the dc converter module is designed to operate safely within its current limit and power limit maximums.
Tomi Engdahl says:
Advanced DACs Bring RF Signal Generation to Light
http://www.mwrf.com/test-measurement/advanced-dacs-bring-rf-signal-generation-light?NL=MWRF-001&Issue=MWRF-001_20180222_MWRF-001_439&sfvc4enews=42&cl=article_1_b&utm_rid=CPG05000002750211&utm_campaign=15498&utm_medium=email&elq2=12aa2060d2764b949320278230c2b65c
This white paper explains how modern digital-to-analog converter (DAC) technology is enabling the direct generation of complex RF signals.
Tomi Engdahl says:
Gallium oxide for cheaper and smaller microcircuits
Silicon has long been a global material for microelectronics and semiconductor technology, but still has limitations, especially in power applications. Now scientists are introducing transparent semiconductive oxides. One of the most promising is gallium oxide.
- One of the biggest shortcomings in the world of microelectronics is always the good use of power. Designers always try to reduce extra power consumption and unnecessary heat production, says Gregg Jessen, electronics engineer at the US Air Force Research Laboratory.
- Usually this is done by scaling the devices. However, the technologies currently in use are already scaled almost to the limits of their access to many applications. They are limited in particular by their critical electric field strength.
Transparent conductive oxides are the most significant emerging material in semiconductor technology. They offer a combination of unlikely conductivity and transparency to the visual spectrum. One of the leading oxides has unique properties that can work as a powerful power switch: Ga2O3 or gallium oxide is a material with incredibly high bandwidth.
Scientists focus on FET
- The next application for gallium oxide is unipolar FET power switches.
Source: http://etn.fi/index.php?option=com_content&view=article&id=7582&via=n&datum=2018-02-19_14:48:02&mottagare=31202
Tomi Engdahl says:
Intel is spending more and more money on research
Intel’s processor manufacturer consumes more money than R & D for research and product development than the next four largest investors.
According to IC Insights, Intel spent $ 13.1 billion last year on research, or 21.2 percent of its net sales. The amount grew by three per cent on the previous year. In 2000, Intel’s R & D investments accounted for 16 percent of net sales, so the sum is growing in both relative and absolute terms.
Qualcomm is the second largest investor in research, as it has done since 2012. Last year, the sum was $ 3.45 billion, which is 4 percent less than in the previous year.
Samsung last year saw $ 3.41 billion, which is 19 percent more than in the previous year. Samsung’s research could be called “Efficiency” as it was the world’s largest semiconductor manufacturer last year.
Source: http://etn.fi/index.php?option=com_content&view=article&id=7581&via=n&datum=2018-02-19_14:48:02&mottagare=31202
Tomi Engdahl says:
Building a Better Battery
http://www.powerelectronics.com/batteries/building-better-battery?NL=ED-003&Issue=ED-003_20180219_ED-003_349&sfvc4enews=42&cl=article_1_b&utm_rid=CPG05000002750211&utm_campaign=15417&utm_medium=email&elq2=b808b8d0462c4b0eb6a5bb61c2bf28c6
The race to the world’s greatest battery is on, and scientists from APL may have just won first place with the world’s first near-destructible lithium-ion battery.
A cross-functional team of scientists from John Hopkins University Applied Physics Laboratory (APL), the University of Maryland, and the Army Research Laboratory (ARL) have invented a flexible, gel-based lithium-ion (Li-ion) battery that continues to power load even after being cut in half, submerged in water, and shot with an air cannon. The breakthrough technology is novel in its ability to withstand abuse and may redefine how the world thinks about power.
Lithium-Ion
Research on lithium-ion battery technology began in 1912. In 1970, the first Li-ion battery hit the market, and the technology has rapidly increased in popularity since. Li-ion production capacity was 29 gigawatt-hours in 2016. The demand for mobile power solutions for consumer electronics only continues to rise, and to date, there has not been a better rechargeable power solution than Li-ion. Li-ion technology, however, is not without issues.
The Problem with Existing Li-ion Batteries
Lithium-ion technology poses a serious problem: Li-ion batteries can explode and burst into flames.
The electrolyte used in Li-ion batteries, however, is highly flammable and bursts into flames when punctured or if conditions of extremely high heat are present (say, the kind of high heat present in a flammable Samsung Galaxy smartphone).
The new gel-based battery invented by APL researchers, however, may have solved the known issues with using Li-ion technology.
The flexible battery developed by the team of scientists at APL, UMD, and ARL is based on a novel electrolyte that APL and UMD researchers discovered in 2015, called “water-in-salt.” The team embedded the water-in-salt electrolyte in a polyvinyl alcohol (PVA) polymer matrix. The result is a gel polymer electrolyte (GPE) that is more stable than a liquid, but also boasts flexibility and the high-energy capabilities of its commercial counterparts.
In an experiment, the research team built a prototype using the GPE substrate, enclosed between pieces of electronically insulating heat-resistant tape. The team used the battery to power a hefty motor. Then, the researchers cut the battery, submerged it in a tank of synthetic salt water, and shot it with an air cannon. The battery continued to power load despite the extreme, abusive conditions.
The flexible GPE-based battery seems to be about 4 inches high x 1 inch wide.
Though similar in output to traditional Li-ion batteries, the versatility of the GPE-based technology is unparalleled by both Li-ion technology and other emerging battery technologies like Al-O batteries, solid-state batteries, and micro-batteries
Tomi Engdahl says:
Unique Driver Architecture Enhances GaN-Based Isolated Power-Supply Designs
http://www.powerelectronics.com/gan-transistors/unique-driver-architecture-enhances-gan-based-isolated-power-supply-designs?NL=ED-003&Issue=ED-003_20180223_ED-003_530&sfvc4enews=42&cl=article_1_b&utm_rid=CPG05000002750211&utm_campaign=15529&utm_medium=email&elq2=5adf716468064a6b8476b43c654281b9
GaN-on-silicon E-HEMT transistors are the choice for maximum performance, efficiency and cost-effective power supplies. Cost-effective driver technology enhances supply performance by simplifying layout, reducing component count, and improving reliability.
GaN (gallium nitride) E-HEMTs (High Electron Mobility Transistors) have altered the dynamics of power electronics in consumer electronics, datacenters, industrial motors, appliances, and transportation. In the past, the transistor (formerly the Superjunction MOSFET) was the limiting factor in most switching power supplies. For years, 100 kHz-300 kHz was state-of-the-art.
Over the last 10 years or so, the only improvements have been confined to efficiency as MOSFETs have become incrementally better from one generation to the next. With the advent of GaN transistors that look and act like much faster Superjunction MOSFETs, suddenly magnetics, layout techniques, and performance drivers have leapt into the limelight of areas that need to be improved.
Driver requirements don’t change much with E-HEMT GaN transistors. But to take full advantage of GaN’s benefits, the few parameters that do change are very important.
Minimum Requirements for Non-Isolated Single Gate Driver
Most operate at 5 to 6.5V gate drive
Integrated LDO for regulated 5 to 6V gate drive
ROL≤ 2Ω pull-down output impedance
2A peak drive current
Low-inductance SMT package
1MHz switching capability
Tomi Engdahl says:
Component Shortages Will Ease as Wafer Capacity Grows
https://epsnews.com/2018/02/22/component-shortages-will-ease-wafer-capacity-grows/
Silicon wafer production capacity last year wasn’t enough to meet supply and demand across several IC segments, particularly memory components and discrete semiconductors, which resulted in component shortages and extended lead times. Wafer capacity is now forecast to increase over the next two years, which will lessen supply constraints and stabilize pricing as more capacity is brought online.
But buyers shouldn’t expect to see any relief from tight supply for either memory components or discrete semiconductors until the second half of 2018. Market research firm TrendForce doesn’t expect new DRAM production capacity to be available until the second half of 2018.
Several memory device manufacturers have announced plans to ramp up production capacity over the next few years, which should stem the steep price hikes experienced over the past 18 months and stabilize pricing by 2019. Samsung, SK Hynix, Micron, Intel, Toshiba/WD, and XMC/Yangtze River Storage Technology all have reported plans to ramp up 3D NAND flash production, while Samsung and SK Hynix also are increasing DRAM capacity over the next two years.
Tomi Engdahl says:
Chipmakers Test Ferroelectrics as a Route to Ultralow-Power Chips
https://spectrum.ieee.org/computing/hardware/chipmakers-test-ferroelectrics-as-a-route-to-ultralowpower-chips
Academics have high hopes for ferroelectric materials. Adding a single layer of these materials, which have unusual electrical properties, to today’s transistors could radically decrease the power consumption of chips.
Many in industry are skeptical about the benefits of ferroelectrics. Still, the IEDM meeting made it clear that semiconductor companies are now paying attention. Researchers from GlobalFoundries presented data on the performance of ferroelectric-frosted transistors made using their 14-nanometer manufacturing technology.
The magic of ferroelectrics is their potential to free engineers from the “Boltzmann tyranny,”
Operating at lower voltages will be necessary for engineers to further shrink transistors. As they get smaller, they do a worse job of shedding heat. Shrink them too much and the overheating transistors will melt. Running transistors at lower voltages keeps temperatures in check.
Ferroelectric materials are defined by their tendency to experience profound electrical polarization in response to relatively puny electrical fields. Put a voltage across a ferroelectric film and charges—sometimes charged atoms—within it will quickly move from one side to the other. “You put half a volt on it, and because of the polarization it’s like applying a whole volt,” says Franklin.
Tomi Engdahl says:
Generating Electricity is a Snap
A collaborative research project is making use of temperature fluctuations to produce electricity.
http://www.powerelectronics.com/alternative-energy/generating-electricity-snap?NL=ED-003&Issue=ED-003_20180228_ED-003_787&sfvc4enews=42&cl=article_1_b&utm_rid=CPG05000002750211&utm_campaign=15646&utm_medium=email&elq2=1fabf038ff6447bdb785a26b49c511be
Tomi Engdahl says:
Microchip Technology in talks to buy Microsemi: source
https://www.reuters.com/article/us-microsemi-m-a-microchip-tech/microchip-technology-in-talks-to-buy-microsemi-source-idUSKCN1GB0K3
Tomi Engdahl says:
Bye Bye, Maplin
https://hackaday.com/2018/03/01/bye-bye-maplin/
Well, that was quick. Four days ago we mentioned that the British electronics retail chain Maplin was being offered for sale, and today it has been announced that no buyer has been found and the company is going into administration.
We dealt with all the nostalgia for what was roughly a British equivalent to Radio Shack in our previous post. Perhaps now it’s time to look beyond the jumpers-for-goalposts reminiscences about spaceships on the catalogues for a moment, and consider what this means for us in 2018.
https://hackaday.com/2018/02/24/maplin-for-sale/
Tomi Engdahl says:
The world’s first 3 nanometer circuit
The Belgian Microelectronics Research Center IMEC, together with the EDA House with Cadence Design Systems, has made a real breakthrough in circuit manufacturing technology. EUV lithography and traditional 193 nanometers immersolithography and Cadence’s tools gave the world’s first 3 nanometer test circuit to be the world’s first.
The test circuit was a common 64-bit processor circuit, which was made with standard cell libraries. With the TRIM process, the gap between the routing of the circuit was shrunk to 21 nanometers.
IMEC and Cadence reached the previous milestone in 2015 by launching the first 5 nanometer circuit. According to the researchers, the implementation of a 3 nanometer test circuit indicates that mobile circles can expect significant upheaval in the next few years.
Source: http://etn.fi/index.php?option=com_content&view=article&id=7637&via=n&datum=2018-03-01_14:57:06&mottagare=31202
Tomi Engdahl says:
Microchip Technology Agrees to buy Microsemi
https://www.wsj.com/articles/microchip-technology-agrees-to-buy-microsemi-1519938593
Microchip to pay $68.78 a share for Microsemi, or $8.3 billion
Tomi Engdahl says:
DIY Monolithic Power Management ICs
http://www.powerelectronics.com/power-management/diy-monolithic-power-management-ics?NL=ED-003&Issue=ED-003_20180301_ED-003_736&sfvc4enews=42&cl=article_2_b&utm_rid=CPG05000002750211&utm_campaign=15659&utm_medium=email&elq2=4773c928436344a9a6ae571487912574
A library of selectable standard analog building blocks and unique software enables the in-house design and production of a monolithic power management IC.
You may not be able to find a commercially-available power management IC (PMIC) that meets your application’s requirements, but there is a way to get the device you need. You can use a new “do-it-yourself” (DIY) design technique, developed by AnDAPT (www.andapt.com), that employs a library of selectable power component building blocks, which in turn are built using analog elementary blocks that can interface with each other. They are offered on an Adaptive Multi-Rail Power (AmP) platform IC. After you select all the desired power component building blocks, software interconnects the analog elementary blocks (called µAnalog by AnDAPT) and creates a ready-to-use monolithic IC tailored to the requirements of the particular application.