Here are some of my collection of newest trends and predictions for year 2018. I have not invented those ideas what will happen next year completely myself. I have gone through many articles that have given predictions for year 2018. Then I have picked and mixed here the best part from those articles (sources listed on the end of posting) with some of my own additions to make this posting.This article contains very many quotations from those source articles (hopefully all acknowledged with link to source).
The general trend in electronics industry is that the industry growth have been driven by mobile industry. Silicon content in smartphones and other mobile devices is increasing as vendors add greater functionality. Layering on top of that are several emerging trends such as IoT, big data, AI and smart vehicles that are creating demand for greater computing power and expanding storage capacity.
Manufacturing trends
According to Foundry Challenges in 2018 article the silicon foundry business is expected to see steady growth in 2018. The growth in semiconductor manufacturing will remain steady, but there will be challenges in the manufacturing capacity and expenses to move to the next nodes. For most applications, unless you must have highest levels of performance, there may not be as compelling a business case to focus on the bleeding-edge nodes. Over the last two years, the IC industry has experienced an acute shortage of 200mm fab capacity (legacy MCU, power, sensors, 6-micron to 65nm). In 2018, 200mm capacity will remain tight. An explosion in 200mm demand has set off a frenzied search for used semiconductor manufacturing equipment that can be used at older process nodes. The problem is there is not enough used equipment available. The profit margins in manufacturing are so thin in markets served by those fabs that it’s hard to justify paying current rising equipment prices, and newcomers may have a tough time making inroads. Foundries with fully depreciated 200mm equipment and capacity already are seeing increased revenues in their 200mm business.The specialty foundry business is undergoing a renaissance, thanks to the emergence of 5G and automotive.
300mm is expected to follow a similar path for lack of capacity because 300mm fabs already produce leading-edge chips and more mainstream 300mm demand is driven by MCUs, wireless communications and storage applications. Early predictions are for solid growth in 2018, fueled by demand for memory and logic at advanced 10/7nm.
In 2017, marking the first time that the semiconductor equipment market has exceeded the previous market high of US$47.7 billion set in 2000. Fab tool vendors found themselves in the midst of an unexpected boom cycle in 2017, thanks to enormous demand for equipment in 3D NAND and, to a lesser degree, DRAM. In 2018, equipment demand looks robust, although the industry will be hard-pressed to surpass the record growth figures in 2017. In 2018, 7.5 percent growth is expected to result in sales of US$60.1 billion for the global semiconductor equipment market – another record-breaking year. Demand looks solid across the three main growth drivers for fab tool vendors—DRAM, NAND and foundry/logic.
Rising demand for chips is hitting the IC packaging supply chain, causing shortages of select manufacturing capacity, various package types, leadframes and even some equipment. Spot shortages for some IC packages began showing up in 2017, but the problem has been growing and spreading since then, so packaging customers may encounter select shortages well into 2018. Apple Watch 3 shipment growth to benefit Taiwan IC packagers in 2018.
Market for advanced packaging begins to diverge based on performance and price. Advanced Packaging is now viewed as the best way to handle large amounts of data at blazing speeds.
Moore’s law
Many recent publications say Moore’s Law is dead. Though Moore’s Law is dead may be experiencing some health challenges, it’s not time to start digging the grave for the semiconductor and electronics market yet.
Even smaller nodes are still being taken to use in high end chips. The node names are confusing. Intel’s 10nm technology is roughly equivalent to the foundry 7nm node.In 2018, Intel is expected to finally ramp up 10nm finally in the first half of 2018. In addition, GlobalFoundries, Samsung and TSMC will begin to ship their respective 7nm finFET processes. On the leading edge, GlobalFoundries, Intel, Samsung and TSMC start migrating from the 16nm/14nm to the 10nm/7nm logic nodes. It is expected that some chip-makers face some challenges on the road. Time will tell if GlobalFoundries, Samsung and TSMC will struggle at 7nm. Early predictions are for solid growth in 2018, fueled by demand for memory and logic at advanced 10/7nm. 7nm is projected to generate sales from $2.5 billion to $3.0 billion in 2018. Over time 10nm/7nm is expected to be a big and long-running node. Suppliers of FPGAs and processors are expected to jump on 10nm/7nm.
South Korea’s Samsung Electronics said it has commenced production of the second generation of its 10nm-class 8-Gb DDR4 DRAM. Devices labeled 10nm-class have feature sizes as small as 10 to 19 nanometers. With the continued need for shrinking pattern dimensions, semiconductor manufacturers continue to implement more complex patterning techniques, such as advanced multi-patterning, for the 10nm design node and beyond. They also are investing significant development effort in readying EUV lithography for production at the 7/5nm design nodes. Samsung is planning to begin transitioning to EUV for logic chips next year at the 7nm node, although it is unclear when the technology will be put into production for DRAM.
There will be talk on even smaller nodes. FinFETs will get extended to at least to 5nm, and possibly 3nm in next 5 years. The path to 5nm loks pretty clear. FinFETs will get extended at least to 5nm. It’s possible they will get extended to 3nm. EUV will be used at new nodes, followed by High NA Lithography. New smaller nodes challenges the chip design as abstractions become more difficult at 7nm and beyond. Models are becoming more difficult to develop, integrate and utilize effectively at 10/7nm and beyond as design complexity, process variation and physical effects add to the number of variables that need to be taken into account. Materials and basic structures may diverge by supplier, at 7 nm and beyond. Engineering and scientific teams at 3nm and beyond will require completely different mixes of skills than today.
Silicon is still going strong, but the hard fact is that CMOS has been running out of steam for several nodes, and that becomes more obvious at each new node. To extend into new markets and new process nodes Chipmakers Look To New Materials. There are a number of compounds in use already (generally are being confined to specific niche applications), such as gallium arsenide, gallium nitride, and silicon carbide. Silicon will be supplemented by 2D materials to extend Moore’s Law. Transition metal dichalcogenides (TMDCs), a class of 2D materials derived from basic elements—principally tellurium, selenium, sulfur, and oxygen—are being widely explored by researchers. TMDCs are functioning as semiconductors in conjunction with graphene. Graphene, the wonder material rediscovered in 2004, and a host of other two-dimensional materials are gaining ground in manufacturing semiconductors as silicon’s usefulness begins to fade. Wide-bandgap semiconductor materials like gallium nitride (GaN) and silicon carbide (SiC) are anticipated to be used in many more applications in 2018. Future progress increasingly will require a mix of different materials and disciplines, but silicon will remain a key component.
Interconnect Materials need to to be improved. For decades, aluminum interconnects were the industry standard. In the late 1990s, chipmakers switched to copper. Over the years, transistors have decreased dramatically in size, so interconnects also have had to scale in size leading to roadblock known as the RC challenge. Industry is investing significant effort in developing new approaches to extend copper use and finding new metals. There’s also some investigation into improvements on the dielectric side. The era of all-silicon substrates and copper wires may be coming to an end.
Application markets
Wearables are a question mark. Demand for wearables slowed down in 2017 so much that smart speakers likely outsold wearable devices in 2017 holiday season. eMarketer is estimating that usage of wearable will grow just 11.9 percent in 2018, rising from 44.7 million adult wearable users in 2017 to 50.1 million in 2018. On the other hand market research firm IDC estimates that the shipments of wearable electronics devices are projected to more than double over the next five years as watches displace fitness trackers as the biggest sellers. IDC forecasts that wearables shipments will increase at a compound annual growth rate of 18.4 percent between 2017 and 2021, rising from 113.2 million this year to 222.3 million in 2021. At the same time fitness trackers are expected to become commodity product. Tomorrow’s wearables will become more fully featured and multi-functional.
The automotive market for semiconductors is shifting into high gear in 2018. Right now the average car has about $350 worth of semiconductor content, but that is projected to grow another 50% by 2023 as the overall automotive market for semiconductors grows from $35 billion to $54 billion. The explosion of drive-by-wire technology, combined with government mandates toward fully electric powertrains, has changed this paradigm—and it impacts more than just the automotive industry. Consider implications beyond the increasingly complex vehicle itself, including new demands on supporting infrastructure. The average car today contains up to 100 million lines of code. Self-driving car will have considerably more code in it. Software controls everything from safety critical systems like brakes and power steering, to basic vehicle controls like doors and windows. Meeting ISO 26262 Software Standards is needed but it will not make the code bug free. It’s quickly becoming common practice for embedded system developers to isolate both safety and security features on the same SoC. The shift to autonomous vehicles marks a major shift in the supply chain—and a major opportunity.
Many applications have need for a long service life — for example those deployed within industrial, scientific and military industries. In these applications, the service life may exceed that of component availability. Replacing an advanced, obsolete components in a design can be very costly, potentially requiring an entire redesign of the electronic hardware and software. The use of programmable devices helps designers not only to address component obsolescence, but also to reduce the cost and complexity of the solution. Programmable logic devices are provided in a range of devices of different types, capabilities and sizes, from FPGAs to System on Chips (SoC) and Complex Programmable Logic Devices (CPLD). The obsolete function can be emulated within the device, whether it is a logic function implemented in programmable logic in a CPLD, FPGA or SoC, or a processor system implemented in an FPGA or SoC.
Become familiar with USB type C connector. USB type C connector is becoming quickly more commonplace than any other earlier interface. In the end of 2016 there were 300 million devices using a USBC connection – a big part was smartphones, but the interface was also widespread on laptops. With growth, the USBC becomes soon the most common PC and peripheral interface. Thunderbolt™ 3 on USBC connector promises to fulfill the promise of USB-C for single-cable docking and so much more.
Power electronics
The power electronics market continues to grow and gain more presence across a variety of markets. 2017 was a good year for electric vehicles and the future of this market looks very promising. In 2017, we saw also how wireless charging technology has been adopted by many consumer electronic devices- including Apple smart phones. Today’s power supplies do more than deliver clean and stable dc power on daily basis—they provide advanced capabilities that can save you time and money.
Wide-bandgap semiconductor materials like gallium nitride (GaN) and silicon carbide (SiC) are anticipated to be used in many more applications in 2018. At the moment, the number of applications for those materials is steadily increasing in the automotive and military industry. Expect to see more adoption of SiC and GaN materials in automotive market.
According to Battery Market Goes Bigger and Better in 2018 article advances in battery technologies hold the keys to continuing progress in portable electronics, robotics, military, and telecommunication applications, as well as distributed power grids. It is difficult to see lithium-ion based batteries being replaced anytime soon, so the advances in battery technology are primarily through the application of lithium-ion battery chemistries. New battery protection for portable electronics cuts manufacturing steps and costs for Lithium-ion.
Transparency Market Research analysts predict that the global lithium-ion battery market is poised to rise from $29.67 billion in 2015 to $77.42 billion in 2024 with a compound annual growth rate of 11.6 %. That growth has already spread from the now ubiquitous consumer electronics segment to automotive, grid energy, and industrial applications. Dramatic increase is expected for battery power for the transportation, consumer electronic, and stationary segments. According to Bloomberg New Energy Finance (BNEF), the global energy-storage market will double six times between 2016 and 2030, rising to a total of 125 G/305 gigawatt-hours. In 2018, energy-storage systems will continue proliferating to provide backup power to the electric grid.
Memory
Memory business boomed in 2017 for both NAND and DRAM. The drivers for DRAM are smartphones and servers. Solid-state drives (SSDs) and smartphones are fueling the demand for NAND. Both the DRAM and NAND content in smartphones continues to grow, so memory business will do well in 2018.Fab tool vendors found themselves in the midst of an unexpected boom cycle in 2017, thanks to enormous demand for equipment in 3D NAND and, to a lesser degree, DRAM. In 2018, equipment demand looks robust, although the industry will be hard-pressed to surpass the record growth figures in 2017.
NAND Market Expected to Cool in Q1 from the crazy year 2017, but it is still growing well because there is increasing demand. The average NAND content in smartphones has been growing by roughly 50% recently, going from approximately 24 gigabytes in 2016 to approximately 38 gigabytes today.3D NAND will do the heavy memory lifting that smartphone users demand. Contract prices for NAND flash memory chips are expected to decline in during the first quarter of 2018 as a traditional lull in demand following the year-end quarter.
Lots of 3D NAND will go to solid state drives in 2018. IDC forecasts strong growth for the solid-state drive (SSD) industry as it transitions to 3D NAND. SSD industry revenue is expected to reach $33.6 billion in 2021, growing at a CAGR of 14.8%. Sizes of memory chips increase as number of layer in 3D NAND are added. We’ve already scaled up to 48 layers. Does this just keep scaling up, or are there physical limits here? Maybe we could see a path to 256 layers in few years.
Memory — particular DRAM — was largely considered a commodity business. Though that it’s really not true in 2017. DRAM memory marked had boomed in 2017 at the highest rate of expansion in 23 years, according to IC Insights. Skyrocketing prices drove the DRAM market to generate a record $72 billion in revenue, and it drove total revenue for the IC market up 22%. Though the outlook for the immediate future appears strong, a downturn in DRAM more than likely looms in the not-too-distant future. It will be seen when there are new players on the market. It is a largely unchallenged assertion that Chinese firms will in the not so distant future become a force in semiconductor memory market. Chinese government is committed to pumping more than $160 billion into the industry over a decade, with much of that ticketed for memory startups.
There is search for faster memory because modern computers, especially data-center servers that skew heavily toward in-memory databases, data-intensive analytics, and increasingly toward machine-learning and deep-neural-network training functions, depend on large amounts of high-speed, high capacity memory to keep the wheels turning. The memory speed has not increased as fast as the capacity. The access bandwidth of DRAM-based computer memory has improved by a factor of 20x over the past two decades. Capacity increased 128x during the same period. For year 2018 DRAM remains a near-universal choice when performance is the priority. There has been some attempts to very fast memory interfaces. Intel the company has introduced the market’s first FPGA chip with integrated high-speed EMBED (Embedded Multi-Die Interconnect Bridge): The Stratix 10 MX interfaces to HMB2 memory (High Memory Bandwidth) that offers about 10 times faster speed than standard DDR-type DIMM.
There is search going on for a viable replacement for DRAM. Whether it’s STT-RAM or phase-change memory or resistive RAM, none of them can match the speed or endurance of DRAM. Necessity is the mother of invention, and we see at least two more generations after 1x. XPoint is also coming up as another viable memory solution that could be inserted into the current memory architecture. It will be interesting to see how that plays out versus DRAM.
5G and IoT
5G something in it for everyone. 5G is big. 5G New Radio (NR) wireless technology will ultimately impact everyone in the electronics and telecommunications industries. Most estimates say 2020 is when we will ultimately see some real 5G deployments on a scale. In the meantime, companies are firming up their plans for whatever 5G products and services they will offer. Though test and measurement solutions will be key in the commercialization cycle. 5G is set to disrupt test processes. If 5G takes off, the technology will propel the development of new chips in both the infrastructure and the handset. Data centers require specialty semiconductors from power management to high-speed optical fiber front-ends. 5G systems will drive more complexity in RF front-ends .5G will offer increased capacity and decreased latency for some critical applications such as vehicle-to-vehicle (V2V) or vehicle-to-infrastructure (V2I) communications for advanced driver assistance systems (ADAS) and self-driving vehicles. The big question is whether 5G will disrupt the landscape or fall short of its promises.
Electronics manufacturers expect a lot from Internet of Thing. The evolution of intelligent electronic sensors is creating a revolution for IoT and Industrial IoT as companies bring new sensor-based, intelligent systems to market. The business promise is that the proliferation of smart and connected “things” in the Industrial Internet of Things (IIoT) provides tremendous opportunities for increased performance and lower costs. Industrial Internet of Things (IIoT) has a market forecast approaching $100 billion by 2020. Turning volumes of factory data into actionable information that has value is essential. Predictive maintenance and asset tracking are two big IoT markets to watch in 2018 because they will provide real efficiencies and improved safety. It will be about instrumenting our existing infrastructures with sensors that improve their reliability and help predict failures. It will be about tracking important assets through their lifecycles.
A new breed of designers has arrived that is leveraging inexpensive sensors to build the intelligent systems at the edge of the Internet of Things (IoT). They work in small teams, collaborate online, and they expect affordable design tools that are easy to use in order to quickly produce results. Their goal is to deliver a functioning device or a proof-of-concept to their stakeholders while spending as little money as possible to get there. We need to become multi-functional engineers who can comfortably work in the digital, RF, and system domains.
The Io edge sensor device usually needs to be cheap. Simple mathematical reasoning suggests that the average production cost per node must be small, otherwise the economics of the IoT simply are not viable. Most suppliers to the electronics industry are today working under the assumption that the bill-of-materials (BoM) cost of a node cannot exceed $5 on average. While the sensor market continues to garner billions of dollars, the average selling price of a MEMS sensor, for example, is only 60 cents.
Designing a well working and secure IoT system is still hard. IoT platforms are very complex distributed systems and managing these distributed systems is often an overlooked challenge. When designing for the IoT, security needs to be addressed from the Cloud down to each and every edge device. Protecting data is both a hardware and a software requirement, as more data is being stored and analyzed in edge devices and gateways.
The continued evolution of powerful embedded processors is enabling more functionality to be consolidated into single heterogeneous multicore devices. You will see more mixed criticality designs – those designs which contain both safety-critical and non-safety critical processes running on the same chip. It’s quickly becoming common practice for embedded system developers to isolate both safety and security features on the same SoC.
AI
There is clearly a lot of hype surrounding machine learning (ML) and artificial intelligence (AI) fields. Over the past few years, machine learning (ML) has evolved from an interesting new approach that allows computers to beat champions at chess and Go, into one that is touted as a panacea for almost everything. Machine learning already has delivered beneficial results in certain niches, but it has potential for a bigger and longer lasting impact because of the demand for broad insights and efficiencies across industries. Also EDA companies have been investing in this technology and some results are expected to be announced.
The Battle of AI Processors Begins in 2018. Machine learning applications have a voracious appetite for compute cycles, consuming as much compute power as they can possibly scrounge up. As a result, they are invariably run on parallel hardware – often parallel heterogeneous hardware—which creates development challenges of its own. 2018 will be the start of what could be a longstanding battle between chipmakers to determine who creates the hardware that artificial intelligence lives on. Main contenders on the field at the moment are CPUs, GPUs, TPUs (tensor processing units), and FPGAs. Analysts at both Research and Markets and TechNavio have predicted the global AI chip market to grow at a compound annual growth rate of about 54% between 2017 and 2021.
Sources:
Battery Market Goes Bigger and Better in 2018
Smart speakers to outsell wearables during U.S. holidays, as demand for wearables slows
Wearables Shipments Expected to Double by 2021
The Week In Review: Manufacturing #186
Five technology trends for 2018
NI Trend Watch 2018 explores trends driving the future faster
Creating Software Separation for Mixed Criticality Systems
Isolating Safety and Security Features on the Xilinx UltraScale+ MPSoC
Meeting ISO 26262 Software Standards
DRAM Growth Projected to be Highest Since ’94
NAND Market Expected to Cool in Q1
Memory Market Forecast 2018 … with Jim Handy
3D NAND Storage Fuels New Age of Smartphone Apps
$55.9 Billion Semiconductor Equipment Forecast – New Record with Korea at Top
Advanced Packaging Is Suddenly Very Cool
Apple Watch 3 shipment growth to benefit Taiwan IC packagers in 2018
Rapid SoC Proof-of-Concept for Zero Cost
EDA Challenges Machine Learning
What Can You Expect from the New Generation of Power Supplies?
Optimizing Machine Learning Applications for Parallel Hardware
FPGA-dataa 10 kertaa nopeammin
Chipmakers Look To New Materials
What the Experts Think: Delivering the next 5 years of semiconductor technology
Programmable Logic Holds the Key to Addressing Device Obsolescence
The Battle of AI Processors Begins in 2018
For China’s Memory Firms, Legal Tests May Loom
Predictions for the New Year in Analog & Power Electronics
Lithium-ion Overcomes Limitations
Will Fab Tool Boom Cycle Last?
The Next 5 Years Of Chip Technology
Chipmakers Look To New Materials
Process Window Discovery And Control
Sensors are Fundamental to New Intelligent Systems
Industrial IoT (IIoT) – Where is Silicon Valley
Internet of things (IoT) design considerations for embedded connected devices
How efficient memory solutions can help designers of IoT nodes meet tight BoM cost targets
1,325 Comments
Tomi Engdahl says:
As Toshiba’s $18 billion chip unit sale faces tight deadline, IPO looms
https://www.reuters.com/article/us-toshiba-chips/as-toshibas-18-billion-chip-unit-sale-faces-tight-deadline-ipo-looms-idUSKBN1GZ0LU
Japan’s Toshiba Corp faces a Friday deadline to win Chinese antitrust approval to sell its prized $18 billion memory-chip business by end-March, raising the possibility the deadline may be missed and that it will seek alternatives such as an IPO.
Tomi Engdahl says:
Mixed-Signal PCB Design: Schematic-Level Design Considerations
https://www.eeweb.com/profile/e3-designers-llc/articles/mixed-signal-pcb-design-schematic-level-design-considerations?utm_source=Aspencore&utm_medium=EDN
Convey unique information or special design-specific information: What we mean here is that you must convey design-specific details in the schematic. A great example of this with which we are all probably familiar is the multiple functions on a microprocessor.
Mixed-signal schematic information…
OK, but what does all this mean for mixed-signal PCB designs? What kind of information is important to convey, especially in a mixed-signal design? We’re glad you asked…
Multiple GND/return nets: Sometimes as a designer you will use multiple GND/Return nets in your design. Maybe you have isolated circuitry, sensitive thermocouple conditioning circuitry, high power switch mode power supply returns, or localized PLL power and return nets.
If this is something you find yourself doing in your designs, then make it easy for yourself (and the rest of us!) and name those return nets appropriately! Is it clearer to use a different symbol? Maybe. Is it even more clear to use a different symbol and a unique name like ‘PLL-RTN’, ‘PGND’, ‘AGND’ or ‘ISO-GND’? Absolutely!
What’s the point, though? All that extra work typing, naming the nets… who has the time? The thing is that most seasoned engineers will appreciate this — it informs them that the return plane was isolated or cut for a reason, and for a good reason at that. It tells the engineers who will use this schematic that you were paying attention to the details. And, it will convey the fact that the multiple return nets were used for a reason, not just because you did so on a whim. It communicates that those nets are intended to serve specific functions, and to help separate circuit return paths, which can be very important in mixed signal designs.
Multiple branches from a power net: As you may often use multiple power return paths in your design, you may also have to use multiple power supply paths. Sometimes, these paths are not at different voltage levels, but may simply be high-frequency isolated from a bulk supply on your circuit. A great example of this would be on a highly integrated DSP, which has internal ADC and DAC devices.
You may want to save board space and cost by using the same VCC supply as a reference voltage for these converters — and this is something that designers often do — but it can get confusing if you don’t name those VCC nets clearly.
As an example, consider the following:
2V5
2V5-1
2V5-2
2V5-3
Sure, when you are initially capturing your schematic, you might be able to keep track of things this way, but it can get out of hand very quickly. And later, when you get to the PCB layout, forget about it — you’ll be spinning in circles trying to keep track of that naming “convention.”
Now contrast the preceding example with the following:
2V5
2V5-ADC-VREF
2V5-DAC-VREF
2V5-PLL
We’ll leave it to you to decide which one is the clearer and conveys the design intent more effectively.
Decoupling capacitors: Sometimes on a schematic sheet, it can be difficult to place capacitors at each pin, even though that is what you want done on the layout. This is where the use of some simple text notes can make a big difference and be a big help to whoever is doing the PCB layout. It can be as simple as saying:
Place (1) 10uF and (1) 0.1uF near each VCC pin
…near a group of 40 capacitors intended for 20 pins of an FPGA.
Decoupling in a mixed signal design can be tricky, and the clearer you can convey the design intent you have worked so hard to arrive at, the better will be the end-product. Combining notes on the schematic with unique net names and return paths can go a long-way to keeping all the circuits in your design happy and working as you want them to.
Analog circuit notes: This one is reasonably easy to do and can add a lot to the schematic level. If you have spent hours fine-tuning an op-amp filter, for example, then add a couple of notes at an appropriate location on the schematic to make it easier to understand the function without being obliged to power up a SPICE simulator. Some analog filter topologies are complex and, unless you live in that world, this isn’t something most engineers keep at the forefront of their brains.
Simply writing something like…
’3rd order butterworth LPF, 500kHz -3dB’
…means that junior engineers and others who may not be analog gurus can look at the block and say: “OK, I may not know how to design one of those, but at least I know what it is supposed to do.” Having just this level of information available is more important than many of us realize and something we often take for granted.
Even just writing the gain of a circuit and the expected output range can be invaluable for bench debugging performed by software engineers or technicians who may not have a lot of design experience. We find it useful for us on our own designs. Sometimes there is so much going on that you forget some of the details; that’s OK, but if you write things down you will save yourself a lot of pain in the future.
Tomi Engdahl says:
A brief guide to choosing PCB connectors
https://www.electronicproducts.com/Interconnections/Connectors/A_brief_guide_to_choosing_PCB_connectors.aspx?utm_source=Aspencore&utm_medium=EDN
Find out the key design considerations related to the electrical and mechanical merits of PCB connectors
Tomi Engdahl says:
The case for rigid-flex PCB technology
https://www.edn.com/design/pc-board/4429893/The-case-for-rigid-flex-PCB-technology
When to use flex
It’s getting harder to fit everything in the box; it’s also getting more costly. One solution promising to help designers meet the size constraint head on is rigid-flex PCB technology, but most design teams try to avoid using rigid-flex PCBs when product cost is an issue. But is it really as expensive as we think?
To begin with, consider the cost of the traditional rigid-cable-rigid PCB assembly to one based on rigid-flex technology. The former construction works well for short-run designs; however, it requires connectors on each board and the interconect, all of which drive up BoM cost. Additionally, the rigid-cable-rigid design is prone to ‘cold joints’, and reduced service life. In contrast, rigid-flex circuits eliminate these joints, making them much more reliable and able to deliver overall higher product quality and longevity. So while rigid-flex PCB technology is certainly not new, various considerations now make it much more viable – not the least of which is cost.
Simulate the cost
In some designs, rigid-flex will not be a viable alternative, and you must do your due diligence in determining the break-even point where the costs are about equal. This kind of price simulation can be done by considering the total quoted costs for fabrication and assembly. The PCBs can be quoted before design, as long as the parameters of design are well understood (for example, the layer stack, estimated via count, track and space ratios, etc.).
Tomi Engdahl says:
The collaboration between scientists at Bristol University and Southampton with American Microsem has proved that the operation of microelectromechanical MEMS relays is reliable when contact is coated with nanocrystalline graphite. With technology, it is possible to easily develop very low power electronics in tough environments.
Micro and nano-electromechanical relays are effective zero-loop current generators. They can operate at much higher temperatures and radiation levels than transistors.
Such small size relays have good potential to implement intelligent electronic components with integrated identification, processing and operation that are highly energy efficient.
The study shows how nanocell graphite films protect the tip of the relay against degradation over millions of cycles and provides reliable electrical contact. The thickness of the film is only tens of nanometers.
- Relays with temperatures above 225 ° C and can easily absorb radiation doses of two magnitudes higher than those of the transistors. The challenge is to have them reliably operational. Nanocrystalline graphite thin films function effectively as a leading solid lubricant, which physically protects relay electrodes and breaks contacts millions of times, explains Pamunuwa.
Source: http://www.etn.fi/index.php/13-news/7760-nanokiteisella-grafiitilla-luotettavia-mikro-ja-nanoreleita
Tomi Engdahl says:
Trump Presses China to Buy More U.S. Chips
https://www.eetimes.com/document.asp?doc_id=1333125
China is considering buying more semiconductors from U.S. firms as part of behind-the-scenes negotiations to reduce the U.S. trade deficit with China and avert a trade war, according to reports.
The Wall Street Journal reported on Monday that the Trump administration wants to increase sales of U.S. cars and semiconductors in China as part of a plan to cut the bilateral trade deficit with China — estimated to be about $375 billion — by $100 billion. The Wall Street Journal report cites anonymous sources said to have knowledge of the negotiations between the two nations.
According to a Financial Times report, also citing anonymous sources, China has expressed willingness to divert some of its chip purchases away from Japanese and South Korean companies in favor of U.S. semiconductor firms. China imported $2.6 billion worth of chips from the U.S. last year, according to a separate report by the Reuters news service.
Tomi Engdahl says:
Stock Relisting Could Be a Boon for Arm
https://www.eetimes.com/author.asp?section_id=36&doc_id=1333126
Arm Holdings would gain much-needed visibility under a plan being floated by Softbank to re-list the processor IP firm on the stock market.
A potential relisting of Arm by SoftBank, as highlighted last week in the UK’s Financial Times newspaper, could be a boon for the company, says one former senior electronics industry executive from Imagination Technologies.
Yoshimitsu Goto, a senior corporate officer at SoftBank, is said to have suggested to investors that an initial public offering could be a potential exit strategy for an investment fund that SoftBank launched last year. The report adds that the $93 billion Vision Fund, backed by Saudi Arabia’s main sovereign wealth fund and companies including Apple and Qualcomm, is set to acquire a 25 percent stake in Arm.
Tomi Engdahl says:
The European Commission has fined eight Japanese capacitor manufacturers for a cartel that has been in the industry in 1998-2012. Elna, Hitachi Chemical, Holy Stone, Matsuo, NEC Tokin, Nichicon, Nippon Chemi-Con and Rubycon were sentenced to a fine of EUR 254 million.
The cartel also featured Sanyo, who revealed the whole pattern.
The agreement on prices has had a very large impact on electronic devices. Capacitors are practically used in all devices from smart phones to car systems and wind turbines.
The maximum amount of fines is set at 10% of annual turnover in 2006. For three companies, the fine reached this upper limit.
By disclosing the cartel to the Commission, Sanyo avoided about EUR 32.4 million in fines.
Source: http://etn.fi/index.php?option=com_content&view=article&id=7767&via=n&datum=2018-03-27_15:36:46&mottagare=31202
Tomi Engdahl says:
Microprocessors will soon be 100 times faster
At this time, microprocessors are super-fast. Their clock speed can reach up to 8-16 gigahertz. If the research of Israeli researchers is correct, processors will soon be up to 100 times faster.
The article published in Laser and Photonics Review shows that Professor Levy has developed technology for optical circuits that are as reliable and easy to manufacture as modern electronics. But when data moves instead of electricity in the form of light, the processors are inexplicably fast.
The concept built by the researchers is based on the MONOS (Metal-Oxide-Nitride-Oxide-Silicon) structure. Basically, the structure is very close to the structure of existing flash memory.
Source: http://etn.fi/index.php?option=com_content&view=article&id=7769&via=n&datum=2018-03-27_15:36:46&mottagare=31202
Tomi Engdahl says:
CMOS Optoelectronics: Avalanche-mode silicon LEDs improve optical coupling in CMOS integrated circuits
https://www.laserfocusworld.com/articles/print/volume-54/issue-01/world-news/cmos-optoelectronics-avalanche-mode-silicon-leds-improve-optical-coupling-in-cmos-integrated-circuits.html?cmpid=enl_lfw_lfw_detectors_and_imaging_newsletter_2018-03-27&pwhid=6b9badc08db25d04d04ee00b499089ffc280910702f8ef99951bdbdad3175f54dcae8b7ad9fa2c1f5697ffa19d05535df56b8dc1e6f75b7b6f6f8c7461ce0b24&eid=289644432&bid=2048233
In the world of silicon photonics, researchers aim to develop compact, monolithic optical platforms with integrated light sources and photodetectors to perform electronic-to-optical-to-electronic conversion at the speed of light. As with any other optoelectronic integrated circuit (IC), the goal is efficient and high-speed routing and processing of information signals on and off the chip. The same is true for complementary metal-oxide semiconductor (CMOS) platforms—however, the optical interconnect or optocoupler technology has, until now, been limited to bulky infrared (IR) sources that operate at relatively low (kilohertz) speeds.
To advance optocoupling in CMOS ICs, Ph.D. student Satadal Dutta from the University of Twente (Enschede, Netherlands) has proposed using silicon (Si) light-emitting diodes (LEDs) biased in “avalanche breakdown” mode to generate visible light that is easily detected by standard Si photodiodes in a high-quantum-efficiency process.1 In addition, Dutta and PhD student Vishal Agarwal have modeled and designed a CMOS IC using avalanche-mode LEDs, waveguides, and single-photon avalanche diode (SPAD) detectors that can theoretically operate at gigahertz speeds and single-photon detection sensitivities. Essentially, the all-silicon platform avoids many of the roadblocks presented by hybrid materials systems.
Tomi Engdahl says:
Could Semiconductors be the Linchpin to Avert a China-U.S. Trade War?
http://www.electronicdesign.com/embedded-revolution/could-semiconductors-be-linchpin-avert-china-us-trade-war
China’s offer may be a good first step, but it will likely need to be modified to realize the intended objective.
Citing concerns about record-setting trade deficits between the U.S. and China, and following through on campaign promises, President Trump signed an executive memorandum on March 22 imposing $50 billion in annual tariffs and other penalties on a wide range of Chinese imports. This action follows on President Trump’s imposition of tariffs on steel and aluminum, which will also impact China. China’s response to the earlier tariffs has been to threaten to impose tariffs on $3 billion of U.S. imports.
Tomi Engdahl says:
Going Deep Or Broad With Formal?
Why formal verification is being used in more ways across more designs.
https://semiengineering.com/going-deep-or-broad-with-formal/
Do you want to identify hard to find bugs, and get a certain level of confidence about a block? Where should the effort be placed? Is it by going deep, meaning a team of specialists or experts must be built who can use advanced formal techniques, and do things that not everybody can do, but they can find bugs that other tools or techniques cannot find? Or is the right approach a broad one, where different applications are used that the average verification engineer or designer can get real value out of it when it comes to finding bugs?
The truth is that both deep and broad have areas of high ROI, according to. “The question could come down to how much time and investment one is willing to make,” said Sean Safarpour, CAE director for formal solutions at Synopsys. “If time is scarce, then going broad with some formal apps is a quick solution that provides a lot of value. Apps such as connectivity checking or formal register verification can be deployed within days, but can save weeks of simulation effort, as well as find bugs very quickly. They do this all without the need train anyone on ‘advanced’ formal techniques.”
Tomi Engdahl says:
EU Project Delivers Open-Source Simulator for Cyber-Physical Systems
https://www.eetimes.com/document.asp?doc_id=1333137
A European funded project has released an open-source framework which seamlessly simulates, in an integrated way, both the networking and the processing parts of cyber-physical systems (CPS), as well as cloud and high-performance computing systems.
Cyber-physical systems are supersets of embedded systems, integrating sensing, computation, control, and networking into physical objects and infrastructure. While IoT refers mainly to uniquely identifiable internet-connected devices and embedded systems, CPS refers to the combination of the multiple hardware devices and software (including computational) aspects of a system, together with its relationship with the physical world.
The European project, a three-year program which began in February 2015 and received 2.88 million euros (about $3.5 million) in funding from the European Commission under the Horizon 2020 program, addresses the lack of simulation tools and models for full system design and analysis. This is mainly because most existing simulation tools for complex CPS only efficiently handle parts of a system while mainly focusing on performance.
Tomi Engdahl says:
MRAM Uptake Spurs MCU Design
https://www.eetimes.com/document.asp?doc_id=1333133
As magnetoresistive random access memory (MRAM) gathers steam as an emerging option with increasingly more cost-effective applications, the ecosystem is also emerging to support it.
eVaderis recently announced co-development efforts on an ultra-low-power microcontroller (MCU) reference design using GlobalFoundries’s embedded MRAM technology on the 22-nm FD-SOI (22FDX) platform. Together, the companies are looking to support a wide range of low-power applications such as battery-powered Internet of Things (IoT) products, consumer and industrial microcontrollers, and automotive controllers.
Tomi Engdahl says:
Chip Equipment Sales Remain Strong
https://www.eetimes.com/document.asp?doc_id=1333131
The semiconductor capital equipment market continues to hum along with sales remaining on an upward trajectory in February, with market watchers continuing to anticipate a fourth consecutive year of fab tool spending growth.
The three-month moving average of fab tool sales for North American and Japanese semiconductor gear makers increased on both a sequential and annual basis, according to industry trade groups.
SEMI, the trade association that represents North American semiconductor equipment vendors, reported that North American equipment firms posted $2.41 billion in worldwide bookings in February, up 2 percent from January and up 22 percent compared to February 2017.
Tomi Engdahl says:
What Happened To Nanoimprint Litho?
Next-gen lithography technology resurfaces for a variety of tasks.
https://semiengineering.com/what-happened-to-nanoimprint-litho/
Nanoimprint lithography (NIL) is re-emerging amid an explosion of new applications in the market.
Canon, EV Group, Nanonex, Suss and others continue to develop and ship NIL systems for a range of markets. NIL is different than conventional lithography and resembles a stamping process. Initially, a lithographic system forms a pattern on a template based on a pre-defined design. Then, a separate substrate is coated with a resist. Like a stamping process, the patterned template is pressed against the substrate, forming a pattern on the substrate at feature sizes down to 5nm and beyond.
Nanoimprint is a cost-effective, single-exposure technique that doesn’t require expensive optics and multiple patterning. But the technology has some issues in terms of defectivity, overlay and throughput, preventing it from becoming a more mainstream lithographic technology. Today, NIL is mainly used for non-semiconductor applications.
Tomi Engdahl says:
Improving Patterning Yield At The 5nm Semiconductor Node
https://semiengineering.com/improving-patterning-yield-at-the-5nm-semiconductor-node/
Assessing new process integration options for Imec’s 5nm node with virtual fabrication.
Tomi Engdahl says:
Could Semiconductors be the Linchpin to Avert a China-U.S. Trade War?
http://www.electronicdesign.com/embedded-revolution/could-semiconductors-be-linchpin-avert-china-us-trade-war
China’s offer may be a good first step, but it will likely need to be modified to realize the intended objective.
Citing concerns about record-setting trade deficits between the U.S. and China, and following through on campaign promises, President Trump signed an executive memorandum on March 22 imposing $50 billion in annual tariffs and other penalties on a wide range of Chinese imports. This action follows on President Trump’s imposition of tariffs on steel and aluminum, which will also impact China. China’s response to the earlier tariffs has been to threaten to impose tariffs on $3 billion of U.S. imports.
The announcement of the latest tariffs on Chinese products follows news of record-setting trade deficits between the U.S and China of $375 billion in 2017. The logic behind these new penalties was also framed as a protest against Chinese firms stealing the intellectual property of U.S. firms and rules that force U.S. firms to form joint ventures with Chinese companies in order to access the China market.
Tomi Engdahl says:
How To Choose The Right Memory
https://semiengineering.com/how-to-choose-the-right-memory/
Different types and approaches can have a big impact on cost, power, bandwidth and latency.
When it comes to designing memory, there is no such thing as one size fits all. And given the long list of memory types and usage scenarios, system architects must be absolutely clear on the system requirements for their application.
A first decision is whether or not to put the memory on the logic die as part of the SoC, or keep it as off-chip memory.
“The tradeoff between latency and throughput is critical, and the cost of power is monstrous,”,” said Patrick Soheili, vice president of business and corporate development at eSilicon. “Every time you move from one plane to another, it’s a factor of 100X. That applies to on-chip versus off-chip memory, as well. If you can connect it all together one one chip, that’s always the best.”
For that reason and others, the first choice of chipmakers is to put as much RAM or flash on the logic die. But in most cases, it’s not enough.
“When the size of memory on the logic die exceeds what can be produced economically, then off-chip memory is the obvious choice,”
“There’s a vibrant array of low-cost, low-power memories based on the SPI (Serial Peripheral Interface) bus of several types from several manufacturers, including memories with automotive speed grades. The SPI bus is speeding up and adding width.”
In fact, Cadence is seeing a lot of demand for 200MHz Octal-SPI IP interfaces — both controllers and PHYs.
The critical tradeoffs in memory are bandwidth, latency, power consumption, capacity and cost. Engineers sometimes forget about the cost part, but it drives a lot of decision points of implementation, Nandra said.
Embedded memory
If the memory is embedded as part of an SoC, there are a number of architectural considerations.
Tomi Engdahl says:
More than Moore’s overall wafer demand is driven by the megatrends
http://electroiq.com/blog/2018/03/more-than-moores-overall-wafer-demand-is-driven-by-the-megatrends/
More than Moore (MtM) wafer demand reached almost 45 million 8-inch eq wafers in 2017. The wafer demand is expected to reach more than 66 million 8-inch eq. wafers by 2023, with an almost 10% CAGR between 2017 and 2023. According to Yole Développement (Yole)’s definition, the MtM applications include MEMS & sensors, CIS , and power, along with RF devices.
For the first time, the market research and strategy consulting company Yole announces a global technology & market analysis dedicated to the MtM industry. The Wafer Starts for More Than Moore Applications report is the first part of a valuable series that will be released all year long.
Driven by the increasing deployment of renewable energy sources , and industrial motor drives, as well as the growing EV/HEVs industry, power devices’ wafer market size will grow at an almost 13% CAGR from 2017 to 2023. In 2017, it accounted for more than 60% of overall MtM wafer starts. According to Yole’s analysts, it will continue dominating the MtM industry.
In parallel, 5G, a hot topic today, will likely be a huge part of the MtM evolution, bringing any service to any user anywhere, but also requiring new antennas, along with filtering functionality. These stringent requirements will lead to increasing demand for RF components like RF filters, PAs , and LNAs to ensure access to tomorrow’s radio network.
Tomi Engdahl says:
The Week In Review: Design
Nvidia deep learning architecture for Arm; fabless growth in China; learn marketing.
https://semiengineering.com/the-week-in-review-design-123/
Market research firm IC Insights says fabless IC suppliers accounted for 27% of the world’s IC sales in 2017—an increase from 18% ten years earlier in 2007. U.S. companies accounted for the greatest share of fabless IC sales last year at 53% (down, however, from 2010’s share of 69%). Since 2010, the largest fabless IC marketshare increase has come from the Chinese suppliers, which captured 5% share in 2010 but represented 11% of total fabless IC sales in 2017.
Nvidia will integrate its open-source NVIDIA Deep Learning Accelerator (NVDLA) architecture into Arm’s Project Trillium platform for machine learning. The NVDLA hardware supports a wide range of IoT devices and is supported by Nvidia’s suite of developer tools.
Tomi Engdahl says:
Natural biodynamic systems to solve health and environmental problems
https://www.edn.com/design/medical/4460469/Natural-biodynamic-systems-to-solve-health-and-environmental-problems?utm_source=Aspencore&utm_medium=EDN&utm_campaign=social
Transducer devices are driving advancements in personalized medicine and stem cell technology. Devices such as personal fitness monitors indicate the viability of near infrared optical transducers and the role of light in medical diagnosis. Present day research also suggest not only light, but sound, electromagnetic waves [23], magnetic and electric fields [18, 21], temperature [3], and pH gradients will all play a central role in the development of ultra-portable therapeutic medical systems. The use of electric magnetic and optic (optogenetic) fields in cell differentiation [32, 33, 34] suggest that these systems, natural biodynamic systems, or what some term as holistic medical systems, will be a catalyst for new advances in stem cell research and result in low-cost alternatives to personalized stem cell and generalized medical fitness therapy.
Tomi Engdahl says:
David J. Lynch / Washington Post:
Trump administration targets ~$50B in Chinese electronics, aerospace, and machinery goods with tariffs amid a deepening US-China trade conflict
Trump administration targets $50 billion in Chinese electronics, aerospace and machinery goods with tariffs
https://www.washingtonpost.com/business/economy/trump-administration-targets-chinese-electronics-aerospace-and-machinery-goods-with-50-billion-in-tariffs/2018/04/03/9be42e5e-3786-11e8-9c0a-85d477d9a226_story.html
Tomi Engdahl says:
Global Semiconductor Sales Up 21 Percent Year-to-Year in February
https://www.semiconductors.org/news/2018/04/02/global_sales_report_2017/global_semiconductor_sales_up_21_percent_year_to_year_in_february/
Americas market grows by nearly 40 percent compared to last year; global sales decrease slightly month-to-month
Tomi Engdahl says:
Intel Could Lose Apple Business on Two Fronts
https://www.eetimes.com/document.asp?doc_id=1333150
A report that Apple’s long-rumored transition away from Intel chips to its own Arm-based processor for Mac computers could happen as soon as 2020 sent the largest U.S. chip company’s stock price down more than 6 percent Monday (April 2). According to at least one industry analyst, the potential loss of the processor socket in Macs is only one of two threats facing Intel’s business from Apple.
“I think there is a double threat to Intel. Intel will also likely lose Apple’s modem business once Apple integrates a modem into its mobile SoCs, which will likely be in the same time frame,” said Jim McGregor, principal analyst at Tirias Research, in an email exchange with EE Times.
The Bloomberg news service first reported Monday plans to move Macs to custom, Arm-based Apple processors. Such a move would be consistent with Apple’s moves in recent years to become more vertically integrated. It would also mimic what Apple did in the smartphone market and tablet, moving from Samsung branded processors to its own internally designed A Series processors beginning in 2010.
Tomi Engdahl says:
Trump’s Tariff List to Impact Supply Chain
https://www.eetimes.com/document.asp?doc_id=1333153
Electronics industry executives and trade groups are working to analyze the potential impact of the Trump administration’s list of $50 billion worth of Chinese imports that could be subject to 25 percent tariffs in protest of Chinese policies around technology and intellectual property deemed unfair. The list contains scores of products used in the electronics manufacturing supply chain, but is largely devoid of the finished consumer electronics goods that many feared it could contain.
The list is wide ranging, including products in industries from technology to manufacturing, medical and transportation. It includes a handful of consumer appliances such as some televisions and VCRs, and a host of electronic components such as printed circuit boards, caps and wires.
“The lack of a lot of consumer products indicate the administration doesn’t want to hurt consumers, at least not directly,” said Kevin Krewell, a principal analyst with Tirias Research, told EE Times. “But tariffs often do lead to higher prices for finished goods.”
Tomi Engdahl says:
Mesh Networking Grows For ICs
https://semiengineering.com/mesh-networking-grows-for-ics/
Approach is yet another way to scale SoCs and systems, but it also adds new level of complexity.
Mesh networks were invented to create rich interaction among groups of almost-unrelated peers, but now they are showing up in everything from advanced chip packages to IoT networks.
The flexibility of a many-to-many peer-connection model made the mesh approach a favorite for two-dimensional network-on-a-chip topologies, to the point where they began to supplant data-bus connections during the mid-2000s. That flexibility kept mesh on designers’ short list as 2-D topologies gave way to 3-D, which scale and handle advanced packaging more efficiently
Lessons learned from reaching that balance in chips designed for IoT devices with low power requirements may be useful in designing networks of those devices connected using a mesh-capable extension for Bluetooth Low Energy. The technology can be used to connect as many as 32,000 devices peerlessly, with enough structure to minimize both contention and power use.
Structured mesh topologies already are being applied inside advanced packages, for complex systems such as cars and industrial operations, and across many devices that need to communicate without the formalities of defined hub-and-spoke network structure and role definition. The idea is that chips can be developed independently, function independently, but organize dynamically and non-hierarchically to share information and work together efficiently.
“This is already being implemented on-chip,”
“Rather than going to 7nm and beyond, where you have to deal with yield and cost issues, the goal is not to spin an entire SoC every time you want to go after a new market opportunity,” said Sundari Mitra, CEO of NetSpeed Systems. “The way to do that is to take core IP blocks like accelerators, and combine them with base die such as I/Os and PHYs, which can remain at bigger geometries. But the connection has to be correct so that you don’t end up with deadlocks, and you need an extensible network that allows you to do that. Whether that is purely mesh isn’t essential. You don’t necessarily have to be rigid on the topology. But you do want to connect this all together at the architectural level because verifying it is difficult.”
Tomi Engdahl says:
Power Management, Chapter 5: Regulatory Standards
http://www.powerelectronics.com/power-management/power-management-chapter-5-regulatory-standards?NL=ED-003&Issue=ED-003_20180405_ED-003_581&sfvc4enews=42&cl=article_2_b&utm_rid=CPG05000002750211&utm_campaign=16374&utm_medium=email&elq2=9f97506f6b2e45dc8517c012859206ac
Regulatory standards must be met because international and domestic standards are required for the power-management section of the end-item equipment. These standards vary from one country to another, so the power subsystem manufacturer and the end-item system manufacturer must adhere to these standards where the system will be sold. Design engineers must understand these standards even though they may not perform standards certification. Understanding these regulatory standards usually poses problems for power-management subsystem designers.
Power-Line Standards for Power Supplies
EN61000-3: Limits voltage changes the power supply under test can impose on the input power source (flicker test).
EN61000-4: Tests the effects of transients and determines the ability of the power supply to survive without damage or operate through temporary variations in main voltage. These transients can be in either direction (undervoltage or overvoltage).
EN61000-3-2: Limits the harmonic currents that the power supply generates onto the power line. The standard applies to power supplies rated at 75 W with an input line current up to 16A/phase.
EN61000-4-11: Checks the effect of input voltage dips on the ac input power supplies.
EMC Standards for Power Supplies
The most commonly used international standard for emissions is C.I.S.P.R. 22 “Limits and Methods for Measurement of Emissions from ITE.” Most of the immunity standards are contained in various sections of EN61000. As of January1996, EC Directive 89/336/ EEC on EMC requires the manufacturer to make a declaration of conformity if the product is sold in the European Community.
Sections of EN61000 for EMC include:
EN61204-3: This covers the EMC requirements for power supplies with a dc output up to 200V at power levels up to 30kW, and operating from ac or dc sources up to 600 V.
EN61000-2-12: Compatibility levels for low-frequency conducted disturbances and signaling in public medium-voltage power supply systems
EN61000-3-12: Limits for harmonic currents produced by equipment connected to public low-voltage systems with input current >16A and < 75A per phase
EN61000-3-2: Limits harmonic currents injected into the public supply system. It specifies limits of harmonic components of the input current, which may be produced by equipment tested under specified conditions
EN61000-4-1: Test and measurement techniques for electric and electronic equipment (apparatus and systems) in its electromagnetic environment.
EN61000-4-11: Measurement techniques for voltage dips, short interruptions, and voltage variations immunity tests.
EN61000-4-12: Testing for non-repetitive damped oscillatory transients (ring waves) occurring in low-voltage power, control, and signal lines supplied by public and non-public networks.
EN61000-4-3: Testing and measurement techniques for immunity requirements of electrical and electronic equipment to radiated electromagnetic energy. It establishes test levels and the required test procedures.
EN61000-4-4: Testing and measurement techniques for electrical fast transient/burst immunity test.
EN61000-4-5: Recommended test levels for equipment to unidirectional surges caused by overvoltage from switching and lightning transients. Several test levels are defined that relate to different environment and installation conditions.
EN61000-6-1: Electromagnetic compatibility (EMC) immunity for residential, commercial, and light-industrial environments
EN61000-6-2: Generic standards for EMC immunity in industrial environments
EN61000-6-3: Electromagnetic compatibility (EMC) emission requirements for electrical and electronic apparatus intended for use in residential, commercial, and light-industrial environments.
EN61000-6-4: Generic EMC standards for industrial environments intended for use by test laboratories, industrial/medical product designers, system designers, and system installers.
Restriction of Hazardous Substances (RoHS) Affects Power Supplies
RoHS is a directive that restricts use of hazardous substances in electrical and electronic equipment. Designated 2002/95/EC, it is commonly referred to as the Restriction of Hazardous Substances Directive. This RoHS directive took effect in July 2006, and includes power supplies. Often referred to as the lead-free directive, RoHS restricts the use of: lead; mercury; cadmium; hexavalent chromium (Cr6+); polybrominated biphenyls (PBB) (flame retardant); and polybrominated diphenyl ether (PBDE) (flame retardant).
Electronic Waste Directives
RoHS is closely linked to the Waste and Electronic Equipment Directive (WEEE). Designated 2002/96/EC, it makes power-supply manufacturers responsible for the disposal of their waste electrical and electronic equipment
Directives for Disposal of Batteries
Batteries are not included within the scope of RoHS. However, in Europe, batteries are under the European Commission’s 1991 Battery Directive (91/157/EEC), which was recently increased in scope and approved in the form of the new battery directive, version 2003/0282 COD
Tomi Engdahl says:
Firms Need Engineers, But Resist Paying More to Get Them
http://www.electronicdesign.com/analog/firms-need-engineers-resist-paying-more-get-them?NL=ED-003&Issue=ED-003_20180406_ED-003_111&sfvc4enews=42&cl=article_2_b&utm_rid=CPG05000002750211&utm_campaign=16376&utm_medium=email&elq2=560f2407d3014efc9c6b4de599609e6e
The engineering job market is tight. But many companies are somewhat unrealistic about the importance of offering a competitive salary, which isn’t going to get them top talent.
Angie Keller | Mar 07, 2018
It’s probably no surprise that the job outlook for engineers is positive. In a January Bureau of Labor Statistics report, employment in the electrical and electronics space is expected to grow seven percent by the year 2026.
To capitalize on the country’s economic growth, organizations are expanding and looking for more workers to fill traditional roles in addition to new and emerging positions. As such, the engineering market is experiencing a lower unemployment rate compared to the national average, with tens of thousands of jobs expected to be added in the next five years.
At Randstad, we see demand rising for a diversity of engineering skill sets, where competition for candidates is getting fierce:
● Validation Engineers: While the overall job outlook for validation engineers has struggled in past years, demand for them is growing. In fact, the projected total employment for validation engineers is expected to top 194,000 in 2018.
● Controls Engineers: As automation gains traction in manufacturing and beyond, controls engineers are increasingly in demand.
● Robotics Engineers: In a recent poll, 81 percent of senior executives surveyed cited robotics as one of the top five industrial sectors that will hire new workers through the end of this decade.
● Embedded Engineers: Increased demand by consumers and businesses for more connectivity and smarter, more power-efficient electronic technology is driving the demand for embedded systems engineers. Especially sought out are embedded developers with not only the required coding expertise, but also a deep understanding of how software and hardware interact and communicate.
Almost across the board, it is proving extremely difficult for companies to fill open engineering positions today. HR decision makers report the average time to fill a non-executive position is 2.6 months and five months or more to find leadership and executive talent
A key challenge: Many companies are somewhat unrealistic about the importance of offering a competitive salary
Tomi Engdahl says:
Intel invests in next-gen 3D nanowire LEDs from Aledia
https://www.laserfocusworld.com/articles/2018/02/intel-invests-in-next-gen-3d-nanowire-leds-from-aledia.html?cmpid=enl_lfw_lfw_laser_sources_newsletter_2018-04-05&pwhid=6b9badc08db25d04d04ee00b499089ffc280910702f8ef99951bdbdad3175f54dcae8b7ad9fa2c1f5697ffa19d05535df56b8dc1e6f75b7b6f6f8c7461ce0b24&eid=289644432&bid=2058250
Next-generation 3D LED manufacturer Aledia (Grenoble, France) closed a Series C financing round with Intel Capital as a new investor. In addition to Intel Capital, the majority of existing Aledia investors participated in the $37.3 million dollar (30 million euro) round, including Braemar Energy Ventures, Demeter, the Ecotechnologies Fund of Bpifrance, (the French national industrial bank), IKEA Group, the venture capital arm of IKEA, Sofinnova Partners, and Supernova Invest.
Aledia’s LED displays are based on WireLED (trademarked) 3D nanowire technology, which allows manufacturing of 3D LEDs on 8-inch (200 mm) or larger silicon wafers in existing microelectronics foundries and straightforward integration with electronics. The company says the 3D GaN-nanowires-on-silicon technology delivers increased brightness and more energy-efficient displays at a cost point that is lower than that of conventional planar (2D) microLEDs.
“The opportunity for Aledia’s breakthrough nanowire-LED display technology is huge,” said Giorgio Anania, CEO, chairman and co-founder of Aledia. “Today more than 3 billion people interface to the Internet with mobile displays, and LED technology is expected to be used in a majority of these displays in the next few years. The unique advantages that 3D LED technology delivers position it as the driver of a once-in-a-generation shift.
Tomi Engdahl says:
Ćuk’s resonant buck slashes magnetics
https://www.edn.com/electronics-blogs/benchtalk/4460524/-uk-s-resonant-buck-slashes-magnetics?utm_source=Aspencore&utm_medium=EDN&utm_campaign=social
The name of Dr. Slobodan Ćuk (pronounced, roughly, chook) is familiar to most engineers as the originator of the eponymous Ćuk DC-DC converter architecture, justly famed for its low input & output ripple currents, and ability to act as a buck-boost.
So when a new converter architecture of his was recently brought to my attention, my interest was very definitely piqued.
While Ćuk seems to like the idea of keeping the switching frequency low, I see no reason not to increase it to reap the usual rewards of smaller LC values and faster transient response
Tomi Engdahl says:
Ruggedized Connectors: Protecting Power and Data in Adverse Conditions
http://www.electronicdesign.com/industrial-automation/ruggedized-connectors-protecting-power-and-data-adverse-conditions?code=NN8DK002&utm_rid=CPG05000002750211&utm_campaign=16450&utm_medium=email&elq2=2945ceb6a18a466898444a7a668cbc7b
Sponsored by Digi-Key and TE Connectivity: Just one component’s failure can cause an entire machine or system to completely break down, which has led to advances in connectors using a variety of metals and other materials.
Tomi Engdahl says:
A lifetime designing PCBs: A new beginning
https://www.edn.com/electronics-blogs/all-aboard-/4460427/A-lifetime-designing-PCBs–A-new-beginning
Lessons learned
Throughout this series of articles, I’ve written about lessons learned. Here is a list of what I believe are the most significant ones:
Respect – When starting a new job, the most important thing to do is earn the respect of coworkers. This requires listening, and understanding their perspective and motivations.
Writing specs – Documenting innovative ideas by choosing precise wording, creating meticulous images, and adding humor, make the specs convincing, clear, and engaging.
Management – My boss said, “My most important role is to remove the obstacles preventing you from becoming successful.” That was a mic-drop moment.
Teamwork – Whether designing a board or implementing software, enabling team members to contribute their talents along with my own defines the line between success and failure.
Knowledge – Signal speeds and manufacturing technology are continually evolving. Designers who learn the problems and participate in creating solutions will be the industry leaders of the future.
Designer frustration – The best way to keep designers content with their software design tools is to address the problems and limitations that frustrate them.
Tomi Engdahl says:
Design Services Need Uber-izing
https://www.eetimes.com/document.asp?doc_id=1333161
A wide swath of semiconductor design services companies are seeking their breakout moment. Samir Patel thinks that he has found one in the ability to customize standard products for an increasingly applications-centric chip market.
“There are 200–400 design service companies, and half of them are in Bangalore … [this sector] will get Uber-ized to provide more efficiency,” said the chief executive of Sankalp Semiconductor at an event here.
Just as Uber defined the new market of ride-sharing, design companies need to create new business models to deliver services faster and more cheaply. As the standalone, people-intensive part of the semiconductor industry, design services are “ripe to be Uber-ized,” said Patel in a talk at the D&R IP-SoC Days.
Tomi Engdahl says:
February Chip Sales Down From January
https://www.eetimes.com/document.asp?doc_id=1333163
Global semiconductor sales declined in January compared to February, but still remained well ahead of last year’s pace, according to the Semiconductor Industry Association (SIA).
The three-month average for chip sales in February totaled $36.8 billion, down 2 percent from January but up 21 percent compared with February 2017, according to the SIA. It was the 19th consecutive month that the three-month average of sales increased on an annual basis.
The SIA said the decline in sales compared with January represented typical seasonal market trends. The SIA reports sales estimates compiled by the World Semiconductor Trade Statistics (WSTS) organization, a group of more than 50 chip makers that pool sales data.
Tomi Engdahl says:
Bangalore Hotbed of Semiconductor Design Services
https://www.eetindia.co.in/news/article/18040604-bangalore-hotbed-of-semiconductor-design-services
A wide swath of semiconductor design services companies are seeking their breakout moment. Samir Patel thinks he has found one in the ability to customize standard products for an increasingly applications-centric chip market.
“There are 200-400 design service companies, and half of them are in Bangalore…[This sector] will get Uber-ized to provide more efficiency,” the chief executive of Sankalp Semiconductor said at an event here.
Tomi Engdahl says:
Global chip industry boom to continue for another year: BOK
http://english.yonhapnews.co.kr/news/2018/04/08/0200000000AEN20180408003700320.html
SEOUL, April 8 (Yonhap) — The global chip industry is anticipated to enjoy another year of strong demand, the central bank said Sunday, claiming local chipmakers should still focus on building capabilities for non-memory products to prepare for future developments.
“The industrywide boom, which started in the second half of 2016 for DRAM products will continue throughout the first half of 2019 and gradually fade out afterwards,” the Bank of Korea (BOK) said in a report. The bank, however, said the rising demand from the self-driving cars and artificial-intelligence segments may prolong the boom further.
The global chip industry was estimated at US$412.2 billion in 2017, up 22 percent from a year earlier. Memory chips, such as DRAM and NAND flash products, accounted for 30.1 percent of the global chip market, with DRAM accounting for 58.7 percent.
Tomi Engdahl says:
Activist fund says Toshiba chip unit worth as much as $40 billion
https://www.reuters.com/article/us-toshiba-chips/activist-fund-says-toshiba-chip-unit-worth-as-much-as-40-billion-idUSKCN1HD0GT
A Hong Kong-based activist investment fund said Toshiba Corp’s (6502.T) chip unit was worth as much as $40 billion, double the sale price agreed with a Bain-led consortium, as it escalated its opposition to the deal.
The sale failed to close by an agreed March 31 deadline as the two sides are still waiting on regulatory approval from China.
Tomi Engdahl says:
Samsung Electronics Aims to Overtake TSMC by Developing 7-Nm Foundry Process
http://www.businesskorea.co.kr/english/news/ict/21486-foundry-war-samsung-electronics-aims-overtake-tsmc-developing-7-nm-foundry-process
According to the semiconductor industry on April 5, Samsung Electronics completed the development of a seven-nanometer foundry process using extreme ultraviolet (EUV) equipment. One nanometer (nm) equals one billionth of one meter. The Korean semiconductor giant originally intended to complete the development of the process in the second half of this year, but finished it six months earlier. Mass production will start this year. It was reported that Qualcomm was preparing samples to supply large volume of mobile application processors (APs) to Qualcomm, the first corporate customer.
At the same time, Samsung Electronics also started the development of a five-nm foundry process and the construction of an EUV-only line in Hwaseong, Korea. The company has also fought a speed battle that were shown in memory semiconductors at the foundry. Based on its overwhelming technology and production capability, Samsung Electronics has set its goal of holding the TSMC in Taiwan and climbing to the top of the foundry industry.
Tomi Engdahl says:
New FPGA maker targets cost-sensitive space
https://www.edn.com/electronics-products/electronic-product-reviews/other/4460483/New-FPGA-maker-targets-cost-sensitive-space?utm_source=Aspencore&utm_medium=EDN&utm_campaign=social
Anyone with a spare garage can start a semiconductor company these days, but it takes a special kind of chutzpah to tilt against the FPGA establishment. After all, writing place & route software is no walk in the park, and having enough good FAEs to hold customers’ hands can be a challenge. And of course there’s the silicon itself. It’s not easy to differentiate your product given the wide range already available, albeit from a small pool of manufacturers.
Enter Efinix, with their Trion FPGA family. From the start, Efinix decided to target cost-sensitive applications, though the top of the line chip is no slouch, at 150 kLEs (plus 8 Mb RAM & 500 multipliers). At the bottom is a mere 4 kLE part, with six more sizes in-between those. You’ll also find varying numbers of PLLs, LVDS & GPIO pins, DDR3 & MIPI interfaces, and even PCIe on the top two chips.
Tomi Engdahl says:
In Reversal, Wolfspeed Buys Infineon’s Radio Frequency Power Business
http://www.mwrf.com/semiconductors/reversal-wolfspeed-buys-infineons-radio-frequency-power-business?NL=MWRF-001&Issue=MWRF-001_20180410_MWRF-001_860&sfvc4enews=42&cl=article_2_b&utm_rid=CPG05000002750211&utm_campaign=16493&utm_medium=email&elq2=9a74588541294da0887674fa505f87ca
Last year, Infineon agreed to pay $850 million for Cree’s power and radio frequency business unit, Wolfspeed. But American officials refused to approve the deal and, after weakly toying with fixes and compromises, Infineon waved the white flag and pulled out of the deal.
Now both companies have hammered out a deal in the opposite direction, following Cree’s vow to aggressively invest in its Wolfspeed business through the end of the decade.
On Tuesday, Wolfspeed said that it had acquired Infineon’s radio frequency power business for about $430 million, bolstering its catalog of power amplifiers used in wireless infrastructure and radar. That includes chips manufactured with gallium nitride layered onto silicon carbide to handle the wider bandwidths and higher frequencies of 5G.
Tomi Engdahl says:
DPA-Switch™ DC-DC Forward Converter Design Guide
https://www.eeweb.com/app-notes/dpa-switch-dc-dc-forward-converter-design-guide
The single-ended forward converter topology is usually the best solution for DC-DC applications in industrial controls, Telecom central office equipment, digital feature phones, and systems that use distributed power architectures.
https://ac-dc.power.com/sites/default/files/product-docs/an31.pdf
Tomi Engdahl says:
ADI 72V Hybrid Step-Down DC/DC Controller Reduces Solution Size
https://www.eeweb.com/profile/eeweb/news/adi-72v-hybrid-step-down-dc-dc-controller-reduces-solution-size
Analog Devices announces the Power by Linear™ LTC7821, an industry first hybrid step-down synchronous controller that merges a switched capacitor circuit with a synchronous step-down controller, enabling up to a 50% reduction in DC/DC converter solution size compared to traditional step-down solutions. This improvement is enabled by a 3X higher switching frequency without compromising efficiency. Alternatively, when operating at the same frequency, an LTC7821 based solution can provide up to a 3% higher efficiency. Other benefits include low EMI and reduced MOSFET stress due to a soft-switched front end, ideal for next generation non-isolated intermediate bus applications in power distribution, datacom and telecom as well as emerging 48V automotive systems.
The LTC7821 operates over a 10V to 72V (80V abs max) input voltage range and can produce an output voltage from 0.9V to 33.5V with currents in multiple 10s of amps, depending on the choice of external components. In a typical 48V to 12V/20A application, an efficiency of 97% is attainable with the LTC7821 switching at 500kHz.
Tomi Engdahl says:
Embedded Die Packaging Emerges
Why this technology approach is suddenly getting attention, and what hurdles still remain.
https://semiengineering.com/embedded-die-packaging-emerges/
Embedded die packaging is seeing renewed demand amid the push towards chips and systems that require smaller form factors.
ASE, AT&S, GE, Shinko, Taiyo Yuden, TDK, Würth Elektronik and others compete in the merchant embedded die packaging market, according to Yole Développement. In fact, ASE and TDK have a joint venture in the arena, which is beginning to ramp up production. Additionally, Texas Instruments and other IC makers develop their own embedded die packages.
Embedded die packaging is different than most package types. Generally, in many IC packages, the devices are situated on top of a substrate. The substrate serves as the bridge between the devices and a board in a system.
The term “embedded packaging” has different meanings. But in the world of embedded die packaging, the idea is to embed components inside the substrate using a multi-step manufacturing process. A die, multiple dies, MEMS or passives can be embedded in a side-by-side fashion in the core of an organic laminate substrate. The components are connected using copper-plated vias. All told, the embedded package resides on the board, which frees up space in a system.
Tomi Engdahl says:
“Quasi-Non-Volatile” Memory Looks to Fill Gap Between Volatile and Non-Volatile Memory
https://spectrum.ieee.org/nanoclast/semiconductors/devices/quasinonvolatile-memory-looks-to-fill-gap-between-volatile-and-nonvolatile-memory
Researchers at Fudan University in Shanghai, China have leveraged two-dimensional (2D) materials to fabricate a relatively new gate design for transistors that may fill the gap between volatile and non-volatile memory.
The result is what the researchers are dubbing a “quasi-non-volatile” device that combines the benefits of static random access memory (SRAM) and dynamic random access memory (DRAM). The new device will make up for DRAM’s limited data retention ability and its need to be frequently refreshed and SRAM’s high cost.
Tomi Engdahl says:
Get Ready For Integrated Silicon Photonics
https://semiengineering.com/preparing-for-integrated-silicon-photonics/
This more than Moore technology is still ramping up, and problems need to be solved, but it could lead to some fundamental changes.
Long-haul communications and data centers are huge buyers of photonics components, and that is leading to rapid advances in the technology and opening new markets and opportunities. The industry has to adapt to meet the demands being placed on it and solve the bottlenecks in the design, development and fabrication of integrated silicon photonics.
“Look at the networking bandwidth used across cloud computing, search and social networks,” says Brian Welch, director of product marketing for Luxtera. “These guys run mega data centers and they just consume outrageous amounts of bandwidth — far in excess of all of the other markets put together. The next place that could rival that scale is the 5G rollout for radio.”
But it is not just about bandwidth anymore. Integrated silicon photonics has the ability to fundamentally change some notions of computing. The industry is just beginning to see what may be possible.
Another advantage of going to 300mm is that foundries are more likely to be using advanced fabrication technologies. “While you don’t need great lithography for optics, it doesn’t hurt,” says Welch. “The structures are huge compared to transistors, and most optical structures have infinite bandwidth, so they don’t need to scale like you need to scale CMOS to make it faster.”
In fact, talking about node sizes doesn’t really make sense for optics. “The wavelength of a photon is quite a bit larger than the wavelength of an electron,” points out Nagarajan. “This is why electronics can go to a 7nm node. However, standard silicon photonic devices are at 130nm or 180nm node, and that is usually using a 245nm lithography line. Optical devices are different from electrical in that they are phase-sensitive. Sidewall roughness and losses matter. When these things are important it is not the node that is important. It is the quality of the lithography and etch that goes with the finer node, but at a larger scale.”
While you may not want to use a 7nm node, the development for that may indirectly help. “All of the progress we have made towards having reduced line roughness on small gates are applicable,”
The problem now is that photonics does not use a traditional CMOS process, and that has limited the number of foundries willing to manufacture the devices. “You want to use all of the tools that exist in the foundry and we want as few deviations as possible,”
Integration
Integration is the driver for data centers. “Integration really matters because it drives down costs,” says Welch. “As you optimize for cost or power, you will evolve towards more integration. So you can get closer to the switch, until eventually you are in the switch and achieve maximum density. This was the same for copper. It used to have discrete PHYs, but over time they got integrated at higher densities in the back of the switch itself. The same will play out in optics.”
“The photonics die is generally lower cost to manufacture,” says Chris Cone, product marketing manager in the Custom IC design group of Mentor, a Siemens Business. “They are generated at a lower technology node such as 130 or 65nm, and the photonics dies tend to be larger. This means they can be flip-bonded, with a CMOS die bonded on top of it. We are seeing large strides in this area. Imagine a CMOS die flip bonded on top of a photonics die, and this die is somewhat larger so you can use it as an interposer. Then you need access to the CMOS die and that would require some form of through-silicon vias (TSV) approach to gain access to the electrical signals.”
One significant problem remains. The laser itself. “A major issue is the integration of the active optical elements, which are typically compound semiconductor-based lasers,” says Martin Eibelhuber, deputy head of business development for the EV Group. “The performance of these lasers cannot be met by silicon-based devices and thus heterogeneous material integration is required, which is not common to a standard CMOS infrastructure. Direct wafer bonding has proven to be an excellent method of combining different materials — allowing high-quality integration at low costs. Due to geometrical constraints, a full wafer-to-wafer bonding approach is not preferred for silicon photonics and thus collective die transfer processes utilizing plasma activated direct bonding have been developed.”
Tomi Engdahl says:
Is 5 nm testing the same or different?
https://www.edn.com/design/integrated-circuit-design/4460545/Is-5-nm-testing-the-same-or-different-
Tomi Engdahl says:
Nvidia Moves Into Top 10 in Chip Sales
https://www.eetimes.com/document.asp?doc_id=1333181
Nvidia cracked the list of top 10 semiconductor vendors by sales for the first time in 2017, joining Qualcomm as the only other strictly fabless chip supplier to attain that distinction last year, according to market research firm IHS Markit.
Nividia’s 2017 sales total of $8.57 billion was good enough for the company to secure the 10th position among chip vendors last year, IHS said. Ironically, Nvidia edged out fellow fabless chip supplier MediaTek of Taiwan to crack the top 10, according to Len Jelinek, director and chief analyst for technology, media and telecommunications at IHS.
Tomi Engdahl says:
Nantero Nudges NRAM Forward
https://www.eetimes.com/document.asp?doc_id=1333172
It’s been more than a year since a research reportcame out predicting a bright future for the next-generation memory using carbon nanotubes known as NRAM, and now the company that’s been pioneering the technology has followed up with new investment, support from high-profile tech vendors, and new products in the pipeline.
He said that one of the most significant milestones for the company was Fujitsu Semiconductor and Mie Fujitsu Semiconductor committing to bring NRAM to market in 2019. Nantero already has more than a dozen partners and customers in the consumer electronics, enterprise systems, and semiconductor industries actively working on NRAM. Another milestone, said Schmergel, is Nantero’s 16-gigabit DDR4 compatible design that is price-competitive with DRAM because it uses a selector-free cross-point design. “That lets us do multiple layers of memory within the die. That product is initially being done at 28 nanometers, which is an advanced node, but not the most advanced node, but because it’s a multi-layer architecture. We can do that selector-free due in part to the unique characteristics of the carbon nanotube switch.”
Tomi Engdahl says:
The Concentration of Semiconductor Market Share
https://www.eetimes.com/author.asp?section_id=40&doc_id=1333179
The top five chipmakers accounted for 43 percent of all semiconductor sales last year, continuing a trend of market share concentration that began at least a decade ago. What’s going on here?
It should come as little surprise that with all of the consolidation that has taken place in the semiconductor industry in recent years, the industry’s market share is now more heavily concentrated in the hands of a few.
According to a new report by market research firm IC Insights, the world’s top five semiconductor suppliers accounted for roughly 43 percent of total chip sales in 2017, an increase of 10 percent from a decade earlier. According to the firm, the top five chip vendors last year — excluding foundries — were, in order: Samsung, Intel, SK Hynix, Micron and Broadcom.